JP2001210869A - Light emitting element array and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a driving element constituted of silicon is deteriorated, the light emitting intensity of a light emitting element is weak, a life is short, material cost and the mounting cost of a wire bonding process cannot be reduced, printing speed cannot be speeded up, an optical printer head cannot be miniaturized and a printing range cannot be extended. SOLUTION: In a light emitting element array, the light emitting element constituted of a compound semiconductor is installed on the surface of a silicon substrate and the driving element for driving the light emitting element is installed on the surface of the silicon substrate, the oxygen elements of 2×1017 to 1×1019 atom/cm3 are caused to exist in an area where the light emitting element on the surface of the silicon substrate is formed, and the light emitting element constituted of a compound semiconductor is formed on the surface part of the silicon substrate. In the manufacturing method of the light emitting array for forming a driving element driving the light emitting element on the surface part of the silicon substrate, the driving element is formed, the surface of the silicon substrate is pre-processed at a temperature below 850 deg.C, and the compound semiconductor is formed at a temperature below 850 deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a light emitting element array and a method of manufacturing the same, and more particularly, to a light emitting element array in which a light emitting element made of a compound semiconductor and a driving element made of silicon are formed on a silicon substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Compound semiconductor substrates such as GaAs and InP are mechanically brittle and difficult to handle. In addition, there is a problem that it is difficult to obtain a high-quality large-area crystal substrate.

In order to solve the problem, there has been proposed a method of growing a compound semiconductor such as GaAs on a low-cost, large-area, high-strength silicon substrate.

Conventionally, as shown in FIGS. 9 and 10,
An optoelectronic integrated circuit device (O) in which a light emitting element made of a compound semiconductor and a driving element made of silicon are provided on a silicon substrate.
EIC (OptoElectronic Integrated Circuits) has also been proposed. This optoelectronic integrated circuit device can be expected to exhibit high performance and exhibit new functions due to downsizing, high speed, low cost, and low mounting cost of the device.

That is, the light emitting element array shown in FIG.
After the driving element 25 made of silicon is formed on the silicon substrate 24, a part of the protective layer 34 is removed by etching to selectively form the light emitting element 24. Finally, the metal electrodes 41 and 4 are formed.
2 (US Pat. No. 4,774,205). The size of the opening of the light emitting element 24 is 50 μm square and 100 m
At A, the output is 6.5 μW.

In the light emitting element array shown in FIG. 10, a light emitting element 45 made of a compound semiconductor is formed on a silicon substrate, and then an output circuit 46 and a signal processing circuit 47, which are driving circuits for the light emitting element 45, are formed. And finally wiring 48
(US Pat. No. 4,587,717).

A light emitting element array in which such a driving element and a light emitting element are integrated can greatly reduce the number of pads for wire bonding, and can reduce the number of mounting steps such as wire bonding and the number of external driving ICs. The optical printer head can be significantly reduced in price. Further, the size of the optical printer head can be reduced by wire bonding and the reduction in the number of components.

[0008]

However, according to the conventional method of forming a driving element made of silicon in advance, when a compound semiconductor such as GaAs is grown on a silicon substrate, the difference in lattice constant between the two materials and the thermal conductivity are increased. Crystal defects such as dislocations occur in the compound semiconductor due to the difference in expansion coefficient.

The dislocations (crystal defects) decrease the efficiency of the process of recombination of electrons and holes, so that the luminous intensity of the light emitting element of the optical device decreases. Since the service life is shortened, it cannot be put to practical use.

Various methods have been proposed for reducing the dislocation density. For example, 200n formed by holographic photolithography on a silicon substrate
A saw-toothed grating at intervals of m is formed, and GaAs is formed on the substrate by guiding the grating to its periodic surface unevenness pattern.
There is a method of growing s by grapho-epitaxial growth by a two-step growth method (Appl. Phys. Lett. 59, 2418 (1991)).
However, photolithography for forming a 200 nm pattern involves forming a nitride film, an oxide film, and an anti-reflection film as patterns on a silicon substrate, and performing complicated processes such as holographic photolithography, dry etching of reactive ion etching, and wet etching. Need.

There is also a thermal cycle annealing method in which high and low temperatures are repeated during formation of a compound semiconductor. This method combines dislocations at high temperature to reduce dislocations. Material Research Society Vol. 116, p-79 reports that when only thermal cycle annealing is repeated five times, the dislocation density is 5 × 10 ⁶ cm ⁻² . And
When the thermal cycle annealing and the formation of the compound semiconductor are repeated four times, the dislocation density becomes 2.5 × 10 ⁶ cm ⁻² . However, the dislocation density does not become 2 × 10 ⁶ cm ⁻² or less only by the thermal cycle annealing method. Further, the pretreatment temperature needs to be 900 to 950 ° C. and the maximum temperature of the thermal cycle annealing needs to be 930 ° C. In such a high-temperature process, thermal diffusion of impurities in the drive element made of silicon occurs remarkably, and the drive element made of silicon Since the leak current of the device increases and the device does not operate normally, it is not practical. For example, phosphorus having high thermal diffusion in silicon is 900 ° C., 1
It diffuses to a thermal diffusion distance of 16 nm in 0 minutes. Since this distance is greater than the processing accuracy of the photolithography, the driving element made of silicon does not operate normally.

As another dislocation reduction method, Materi
al Research Society Vol. 116, p-91, In
There is a method of inserting GaAs and a GaAs superlattice structure. Since there is a difference in lattice constant between the InGaAs layer and the GaAs layer, stress acts on the interface. By this stress, dislocations penetrating from near the interface can be bent laterally to reduce dislocations in the active layer. At this time, the In composition ratio and the film thickness of the InGaAs layer to be used need to be set to be equal to or less than the critical film thickness at which dislocation occurs if the film thickness exceeds the film thickness. Also,
Conversely, when an InGaAs layer exceeding the critical thickness is inserted,
Dislocations in GaAs are reduced in the InGaAs layer. This is because most of the dislocations are concentrated at the interface between the InGaAs layer and the GaAs layer and do not penetrate upward.
By inserting these InGaAs layers, dislocations are 2 × 10
^It can only be reduced to ⁷ cm ^-2 .

Further, as disclosed in Japanese Patent Application Laid-Open No. 6-69136, as a method combining the two dislocation reduction methods, the dislocation density can be reduced by performing thermal cycle annealing four times and stacking a superlattice composed of InGaAs and GaAs in multiple stages. It has been reduced to 3 × 10 ⁵ cm ⁻² . However,
Stacking superlattices in multiple stages requires a lot of processing time and increases costs. Further, the thickness is required to be about 4 μm, and there are problems such as the warpage of the epitaxial substrate and the occurrence of cracks in the epitaxial film, so that practical use is difficult. Also in this case, the maximum temperature of the thermal cycle annealing needs to be 850 ° C. or more, and thermal diffusion of impurities in the drive element made of silicon occurs, and the leak current of the drive element made of silicon increases, so that normal operation cannot be performed. .

In the method of forming a driving element made of silicon after forming a light emitting element made of a compound semiconductor, a method of forming a driving element made of silicon, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or indium aluminum gallium phosphide (InAlGaP), is used. Since a compound semiconductor capable of forming a transition-type efficient light-emitting element has a lower melting point than silicon, it is used at 800 ° C. for ion implantation and gate oxide film formation when a driving element made of silicon is formed.
It cannot withstand the high temperature process described above, and its light emitting characteristics are significantly deteriorated, so that it cannot be put to practical use.

[0015]

SUMMARY OF THE INVENTION The light emitting element array according to the first aspect of the present invention has been made in view of such a problem of the prior art. In a light emitting element array provided with a light emitting element made of a compound semiconductor and a driving element for driving the light emitting element, 2 × 10 ¹⁷ to 1 × 10 ¹⁹ in a region of the silicon substrate surface where the light emitting element is formed. ato
This is in that m / cm ³ of oxygen element was present.

In this light emitting element array, the light emitting elements are gallium arsenide having a thickness of 2 to 3 μm,
It is desirable to have a structure in which indium gallium arsenide (In _x Ga _{1 -x} As) having an indium composition x of 0.2 to 0.2 μm and an aluminum gallium arsenide are sequentially laminated.

According to a third aspect of the invention, there is provided a method for manufacturing a light emitting element array, comprising: forming a light emitting element made of a compound semiconductor on a surface of a silicon substrate; and forming a driving element for driving the light emitting element. In the method of manufacturing an array, after forming the driving element, a surface portion of the silicon substrate is pre-treated at a temperature of less than 850 ° C., and thereafter, the compound semiconductor is formed at a temperature of less than 850 ° C. .

In this method of manufacturing a light-emitting element array, the light-emitting element is formed of gallium arsenide having a thickness of 2 to 3 μm and a thickness of 0.1 μm.
02 to 0.2 μm, and the indium composition x is 0.05 to
0.2 indium gallium arsenide (In _x Ga _1-x A
s) It is desirable to have a structure in which aluminum gallium arsenide is sequentially laminated.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a view showing one embodiment of a light emitting element array according to the present invention, wherein 1 is a p-type silicon substrate, and 2 is an n-type silicon substrate.
Well 3, 3 is a p ⁺ region, 4 is a gate electrode, 5 is a gate oxide film, 6 is an oxide film, 7 is a source region, 8 is a drain region, 9 is an insulating protective film, and 10 is gallium arsenide (n ⁺ Ga
As) and 11 are indium gallium arsenide (n ⁺ In _x Ga).
_{1 -x} As), 12 is gallium arsenide (n ⁺ GaAs), 13
Aluminum gallium arsenide _{(nAl y Ga 1-y As} ) is
14 is aluminum gallium arsenide (pAl _z Ga _{1 -z} A)
s) and 15 are insulating films, 16 is a metal wiring, 17 is an anode electrode, 18 is a cathode electrode, 19 is a protective film, 20 is a wire bonding pad, 21 is a driving element made of silicon, and 22 is a light emitting element.

The drive element 21 made of silicon is formed by:
A conventionally known method is used. The driving element 21 is a schematic diagram of a driving circuit of the light emitting element 22.
Shows a drive circuit including one integrated shift register and an output transistor.

The method of forming the compound semiconductor constituting the light emitting element 22 is as follows.

As shown in FIG. 2A, an insulating protective film 9 is formed on the surface of the silicon substrate on which the driving element 21 made of silicon is formed.

Next, as shown in FIG. 2B, the insulating protective film 9 other than the region where the driving element 21 made of silicon is formed is removed by etching to form an opening region.

In order to partially remove the natural oxide film on the silicon substrate 1 in the opening region other than the region where the driving element 21 made of silicon is formed, the silicon substrate 21 is pretreated in an arsine atmosphere at a substrate temperature of 770 ° C. Perform At this time, the oxygen concentration on the surface of the silicon substrate 1 is 2 × 10 ¹⁸ a
tom / cm ³ .

The oxygen concentration range (2
(× 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ) can be obtained by setting the pretreatment temperature of the silicon substrate to 700 ° C. to 850 ° C. FIG. 3 shows the pretreatment temperature dependence of the oxygen concentration at the interface between the silicon substrate and gallium arsenide by secondary ion mass spectrometry. Here, the background concentration of the oxygen element in the silicon substrate is 1 × 10 ¹⁷ atoms / cm ^3.
It is. It can be seen that the higher the pretreatment temperature, the lower the oxygen concentration and the more the natural oxide film is removed.

Next, gallium arsenide (n ⁺ GaAs) 10 is grown by using the two-stage MOCVD method.

Next, gallium arsenide (n ⁺ GaAs) 10
Thermal annealing at 350 ° C. and 800 ° C. is performed about four times in order to reduce the dislocation density. Thus, the dislocation density of gallium arsenide (n ⁺ GaAs) 10 is 5 × 10 ⁶ c
m ^-2 .

Thereafter, gallium arsenide (n ⁺ GaAs)
s) Form 10 and make the film thickness 3 μm.

Next, in order to further reduce threading dislocations, indium gallium arsenide (n ⁺ In _x Ga _{1 -x} As) 11 having an In composition x of 0.12 was formed to a thickness of 0.02 μm.

FIG. 6 shows indium gallium arsenide (In _x G
The relationship between the In composition x and film thickness of a _1-x As) 11 and the dislocation density of gallium arsenide 12 is shown. In this layer, as the In composition increases, the lattice constant difference from GaAs increases,
Also, as the film thickness increases, the strain at the interface with GaAs increases. In _x G with a dislocation density of 2 × 10 ⁶ cm ⁻² or less
It can be seen that the film thickness of a _1-x As11 is around 0.05 μm for both x = 0.06 and 0.12. It is considered that the vicinity of this film thickness has a strain that efficiently confines threading dislocations to the interface with GaAs.

Thereafter, gallium arsenide (n ⁺ GaAs) 1
2 having a dislocation density of 2 × 1
0 ⁶ cm ^-2 or less of forming a crystalline compound having good semiconductor buffer layer.

FIG. 5 shows the maximum temperature dependence of the dislocation density of gallium arsenide 12 in thermal cycle annealing. Maximum temperature 75
At 0 ° C. to 850 ° C., the dislocation density can be reduced to 2 × 10 ⁶ cm ⁻² or less. The higher the maximum temperature is, the easier the dislocations are to move and the dislocations are easily bonded to each other. However, the difference in thermal expansion coefficient becomes remarkable and impurities in the vacuum device at high temperature become more mixed, so that the temperature is 850 ° C. or more. It is thought that the dislocations increased at high temperatures. When the maximum temperature of the thermal cycle annealing was 800 ° C., the dislocation density of gallium arsenide 12 could be reduced most.

FIG. 4 shows the dependence of the dislocation density of the gallium arsenide 12 on the pretreatment temperature. Pretreatment temperature 700 ° C-850
At ℃, the dislocation density can be reduced to 2 × 10 ⁶ cm ⁻² or less. At a pretreatment temperature of 850 ° C. or higher, the natural oxide film on the silicon substrate is completely removed, and the gallium arsenide cannot be subjected to grapho-epitaxial growth, so that the dislocation density increases and the surface morphology becomes rough. At a temperature of 700 ° C. or less, gallium arsenide cannot be epitaxially grown on the silicon substrate because the natural oxide film on the silicon substrate cannot be removed. Since the natural oxide film is a few atomic layers, the natural oxide film is partially removed at a pretreatment temperature of 700 ° C. to 850 ° C., and the dislocation density can be reduced most because gallium arsenide is grown by grapho-epitaxial growth. It is thought that it is.

Subsequently, aluminum gallium arsenide (nAl _y Ga _{1 -y} As) 13 is formed to a thickness of 0.2 μm as a light emitting layer of the light emitting element 22. The Al composition y is 0.2, and the carrier density is n-type 2 × 10 ¹⁷ cm ⁻³ . Thereafter, aluminum gallium arsenide (pAl _z Ga ₁ -z As) 14 is
to form a PN junction. Al composition z is 0.
2. The carrier density is p-type 2 × 10 ¹⁸ cm ⁻³ .

At this time, one point from the opening end of the insulating protective film 9
As shown in FIG. 2C, the compound semiconductor that grows selectively epitaxially on the exposed surface of the silicon substrate in the region of about 00 μm has a growth rate that is about twice as large as that of normal epitaxial growth, and an abnormal growth part that rises at the end of the selective epitaxial growth area. 23 occurs. This is because, during the selective epitaxial growth, the reaction intermediate generated from the raw material of the compound semiconductor decomposed on the insulating protective film 9 does not immediately crystallize on the insulating protective film 9 but the insulating protective film 9
It is thought that it moves upward and crystallizes on the surface of the compound semiconductor formed on the silicon substrate. This abnormal growth
This makes the film thickness non-uniform, hinders the subsequent photolithography and etching processes, and lowers the yield.

Next, as shown in FIG. 2D, the abnormally grown portion 23 is removed by mesa etching so that the light emitting element formation region has a film thickness distribution that does not affect the etching step after the light emitting element. .

Further, as shown in FIG.
In order to expose the element isolation and the gallium arsenide (n ⁺ GaAs) 12 serving as a cathode electrode as a common electrode, step etching is performed.

Next, an insulating film 15 was formed, and a contact hole was formed in the insulating film 15 on the driving element 21 and the light emitting element 22 made of silicon by etching. And Al
By forming the metal wiring 18 of FIG.
Electrode 18 bonded to gallium arsenide (n ⁺ GaAs) 12, a wire bonding pad 20, and aluminum gallium arsenide (pAl _z Ga ₁ -z A
s) The anode electrode 17 bonded to 16 and the drain region of the drive element 21 made of silicon, the drive element 21 made of silicon, the wire bonding pad 20, and the signal line in the drive element 21 made of silicon are connected. In order to form an ohmic junction between each electrode and the semiconductor, a Cr / Au electrode is formed on the anode 17, an AuGe / Ni / Au electrode is formed on the cathode 18, and a source region 7 and a drain region 8 of a driving element made of silicon are formed. Contains Si / A
1 are joined.

Here, the cathode electrode 18 of each light emitting element
Are connected to each other by gallium arsenide (n ⁺ GaAs) 14 as a common electrode.

Next, as shown in FIG. 2E, a protective film 19 made of SiN is formed on the driving element 21 and the light emitting element 22 made of silicon, and the wire bonding pad 2 is formed.
The protective film 19 on the substrate 0 is removed by etching to expose the wire bonding pad 20.

Thereafter, thermal annealing at 400 ° C. is performed to form an ohmic junction of the ohmic electrode.

[0043]

Next, the experimental results will be shown.

As in the prior art, by setting the pretreatment temperature of the silicon substrate to 860 ° C. or higher, a driving element 21 made of silicon, which is a driving element of the light emitting element, is formed. When a -V group compound semiconductor is grown and a light emitting element 22 having a dislocation density of 2 × 10 ⁶ cm ⁻² is formed using a silicon substrate on which a driving element 21 made of silicon is formed, leakage of the driving element 21 made of silicon is caused. The current was 50 μA, and it could not be used as a driving element of the light emitting element array.

On the other hand, pretreatment at 770 ° C. and heat cycle
Annealing and indium gallium arsenide (In)_xGa_1-xA
s) By inserting the layer, the oxygen concentration on the silicon substrate surface is reduced to 1
× 10 ¹⁸atom / cm^ThreeOf existence and dislocation
By suppressing coupling and dislocation propagation, the driving of light-emitting
A driving element 21 made of silicon as a driving element is formed.
Of III-V compound semiconductors using a silicon substrate
The maximum temperature is less than 850 ° C and the dislocation density is 2 × 10
⁶cm^-2When the light emitting element 22 is formed, silicon
Current of the driving element 21 is 5 μA and is
When the light emitting element 22 is formed.
Drive element 21 made of silicon deteriorates due to heat history of
I didn't.

Therefore, according to the present invention, the dislocation density of a III-V compound semiconductor is reduced to 2 × 10 ⁶ cm ⁻² or less by a III-V compound semiconductor growth process at a temperature lower than 850 ° C. which does not deteriorate a silicon drive element. As a result, a practical light-emitting element array can be manufactured.

The size of the opening of each light emitting element 22 is 2 width.
It has 0 μm and a length of 40 μm square.

FIG. 7 shows the relationship between the light output of the light emitting element and the current. The light output required for the optical printer head is 7 mA.
The light emission output of the light-emitting element is 80 μW with respect to the DC current of

The difference between the light emission outputs is that the dislocation density of the light emitting device of Conventional Example 1 is as high as about 1 × 10 ⁷ cm ^−2, and the dislocation density of the light emitting device of the present invention is reduced to 2 × 10 ⁶ cm ^−2. It depends. That is, as the dislocation density is lower, the number of dislocation defects in which carriers are trapped decreases, the efficiency of electron-hole recombination increases, and the luminous efficiency improves.

In the continuous direct current test (10 mA),
FIG. 8 shows the relationship between the lifetime at which the emission intensity decreases by 10% and the dislocation density. In the case of a printer head, since the light emitting element array is normally pulsed, if the deterioration life is 10 ² hours or more in the continuous DC conduction test, the light emitting element array is at a practical level. Dislocation density is 2 × 10 ⁶ cm
^{When the value is} less than ^-2 , the deterioration life becomes 10 ² hours or more, which indicates that it is practical in terms of reliability.

[0051]

As described above, according to the light emitting device array of the first aspect, the light emitting device made of the compound semiconductor is provided on the surface of the silicon substrate, and the light emitting device is provided on the surface of the silicon substrate. In a light emitting element array provided with a driving element to be driven, 2 × 10 ¹⁷ to 1 × 10 ¹⁹ a is formed on a region of the surface of the silicon substrate where the light emitting element is formed.
Since the oxygen element of tom / cm ³ is present, the process temperature for forming the light-emitting element can be lower than 850 ° C., and the light-emitting element can be formed without deteriorating the driving element made of silicon.

According to the light emitting element array of the second aspect, the light emitting element has a gallium arsenide having a thickness of 2 to 3 μm, a thickness of 0.02 to 0.2 μm, and an indium composition x of 0.05 to 0.2 μm. 0.2 indium gallium arsenide (In _x G
a _1-x As) and aluminum gallium arsenide are sequentially laminated, so that the process temperature of forming the light emitting element is lower than 850 ° C., the driving element made of silicon is not deteriorated, and the dislocation density is 2 × 10 ⁶ cm. ^-2 or less light emitting elements can be formed.

According to a third aspect of the present invention, there is provided a method for manufacturing a light emitting element array, comprising forming a light emitting element made of a compound semiconductor on a surface of a silicon substrate and driving the light emitting element on the surface of the silicon substrate. In the method for manufacturing a light emitting element array for forming an element, after forming the driving element, a surface portion of the silicon substrate is pre-treated at a temperature of less than 850 ° C., and then the compound semiconductor is heated to 850 ° C.
Since the light-emitting element is formed at a temperature lower than the above, the light-emitting element can be formed without deteriorating the driving element made of silicon.

Further, according to the method of manufacturing a light emitting element array according to the fourth aspect, the light emitting element is gallium arsenide having a thickness of 2 to 3 μm, a thickness of 0.02 to 0.2 μm, and an indium composition x of 0.1 to 0.2 μm. Indium gallium arsenide (I-I)
_{n x Ga 1-x As)} , and since it has a sequentially stacked structure of aluminum gallium arsenide, the formation process temperature of the light emitting element is less than 850 ° C., without deteriorating the driving element composed of silicon, dislocation density 2 × A light emitting element of 10 ⁶ cm ^-2 or less can be formed.

Therefore, according to the present invention, the dislocation density of the light emitting element is reduced by 2 × without deteriorating the driving element made of silicon.
By reducing the light emission to 10 ⁶ cm ^-2 or less, the light emission intensity of the light emitting element can be increased, and the life of the light emitting element can be extended to a printer practical use level (continuous lighting of 10 ² hours or more). The element can be driven directly.

Further, by forming a light emitting element array of a compound semiconductor on a silicon substrate on which a driving element made of silicon is formed, a material such as a silicon semiconductor element externally attached to an optical printer head or a light emitting element array mounting substrate can be obtained. The cost can be reduced, the mounting cost such as a wire bonding process can be reduced, the printing speed can be increased, the size of the optical printer can be reduced, and the printing range can be lengthened.

[Brief description of the drawings]

FIG. 1 is a sectional view of a light emitting element array according to the present invention.

FIG. 2 is a process diagram of a light emitting element array according to the present invention.

FIG. 3 shows the dependence of the oxygen concentration at the silicon-gallium arsenide interface on the pretreatment temperature.

FIG. 4 is a relationship between pretreatment temperature and dislocation density.

FIG. 5 shows the relationship between the maximum temperature of thermal cycle annealing and dislocation density.

FIG. 6 shows the relationship between the In composition x and film thickness of In _x Ga _1-x As and dislocation density.

FIG. 7 shows a relationship between a light emitting output of a light emitting element and a current.

FIG. 8 shows the relationship between the lifetime of a light emitting element and the dislocation density.

FIG. 9 is a sectional view showing a driving circuit integrated type light emitting device of Conventional Example 1.

FIG. 10 is a top view showing a drive circuit integrated type light emitting element array of Conventional Example 2.

[Explanation of symbols]

1: silicon substrate, 10: gallium arsenide (n ⁺ GaAs)
^{s), 11: n + In} x Ga 1 -x As, 12: gallium arsenide ^{(n + GaAs), 13:} nAl y Ga 1- y As, 1
_{4: pAl z Ga 1- z As} , 21: driving device made of silicon, 22: light-emitting element

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeo Aono 3-5 Koikodai, Seika-cho, Soraku-gun, Kyoto Prefecture Inside the Central Research Laboratory, Kyocera Corporation (72) Inventor Hideyoshi Tanabe 3-chome, Koikadai, Soraku-gun, Kyoto No. 5 Kyocera Corporation Central Research Laboratory F-term (reference) 4H001 CA02 CA05 XA13 XA31 XA33 XA49 5F041 AA04 AA31 CA12 CA34 CA36 CA54 CA65 CB22 CB33

Claims (4)

[Claims] 1. A light emitting element array in which a light emitting element made of a compound semiconductor is provided on a surface of a silicon substrate and a driving element for driving the light emitting element is provided on a surface of the silicon substrate. 2 × 10 ¹⁷ to 1 × 10 ¹⁹ at is formed in a region where the light emitting element is formed.
A light-emitting element array in which om / cm ³ of oxygen element is present. 2. The light-emitting device according to claim 1, wherein the light-emitting element is gallium arsenide having a thickness of 2 to 3 μm, a thickness of 0.02 to 0.2 μm, and an indium composition x of 0.05 to 0.2.
_{n x Ga 1-x As)} , and the light emitting element array according to claim 1, characterized in that it comprises a sequentially laminated structure of the aluminum gallium arsenide. 3. The method of manufacturing a light emitting element array, wherein a light emitting element made of a compound semiconductor is formed on a surface of a silicon substrate and a driving element for driving the light emitting element is formed on the surface of the silicon substrate. After forming the device, the surface of the silicon substrate is pre-treated at a temperature lower than 850 ° C., and then the compound semiconductor is heated at 850 ° C.
A method for manufacturing a light-emitting element array, wherein the method is performed at a temperature of less than. 4. The light-emitting device according to claim 1, wherein the light-emitting element is gallium arsenide having a thickness of 2 to 3 μm, a thickness of 0.02 to 0.2 μm, and an indium composition x of 0.05 to 0.2.
_{n x Ga 1-x As)} , and a manufacturing method of a light-emitting element array according to claim 3, characterized in that it comprises a sequentially laminated structure of the aluminum gallium arsenide.