JP2621850B2 - Light emitting diode - Google Patents

Light emitting diode

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Publication number
JP2621850B2
JP2621850B2 JP5061084A JP5061084A JP2621850B2 JP 2621850 B2 JP2621850 B2 JP 2621850B2 JP 5061084 A JP5061084 A JP 5061084A JP 5061084 A JP5061084 A JP 5061084A JP 2621850 B2 JP2621850 B2 JP 2621850B2
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JP
Japan
Prior art keywords
layer
light emitting
emitting diode
gaalas
crystal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5061084A
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Japanese (ja)
Other versions
JPS60194585A (en
Inventor
洋久 阿部
恒夫 古川
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Toshiba Corp
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Toshiba Corp
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Priority to JP5061084A priority Critical patent/JP2621850B2/en
Publication of JPS60194585A publication Critical patent/JPS60194585A/en
Application granted granted Critical
Publication of JP2621850B2 publication Critical patent/JP2621850B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は砒化ガリウムアルミニウム（GaAlAs）より成
る発光ダイオードに関するものである。Description: TECHNICAL FIELD The present invention relates to a light emitting diode made of gallium aluminum arsenide (GaAlAs).

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

GaAlAsを用いた赤色発光ダイオード（ピーク発光波長
λｐが660nm付近のもの）として、ｐ−GaAs（ｐ型砒化
ガリウム）基板上にｐ−GaAlAs（ｐ型砒化ガリウムアル
ミニウム）層および約30μｍの層厚のｎ−GaAlAs（ｎ型
砒化ガリウムアルミニウム）層を液相成長法により積層
形成したシングルヘテロ接合型のものが一般に市販され
ている。このような素子は、製造歩留りが高く安価であ
るが、得られる輝度はせいぜい300mcdどまりであつた。As a red light emitting diode using GaAlAs (having a peak emission wavelength λp near 660 nm), a p-GaAlAs (p-type gallium aluminum arsenide) layer and a layer having a thickness of about 30 μm are formed on a p-GaAs (p-type gallium arsenide) substrate. A single heterojunction type in which an n-GaAlAs (n-type gallium aluminum arsenide) layer is formed by a liquid phase growth method is generally commercially available. Such a device has a high manufacturing yield and is inexpensive, but the brightness obtained is at most 300 mcd.

ところで、最近、活性層の両側に異なつた結晶層を有
するダブルヘテロ構造の素子が開発されるに至つた。こ
のダブルヘテロ構造の発光ダイオードの構造は例えば次
のようなものである。すなわち、ｐ−GaAs基板上に順に
ｐ−Ga1-xAlxAs（０＜ｘ＜１）、ｐ−Ga1-yAlyAs（０＜
ｙ＜1,x＜ｙ）、ｎ−Ga1-zAlzAs（０＜ｚ＜1,y＜ｚ）を
積層せしめたもので、上記GaAs基板は光を吸収し易いた
め、最終的には除去される。By the way, recently, a device having a double hetero structure having different crystal layers on both sides of an active layer has been developed. The structure of the light emitting diode having the double hetero structure is, for example, as follows. That is, p-Ga 1-x AlxAs (0 <x <1) and p-Ga 1-y AlyAs (0 <
y <1, x <y) and n-Ga 1-z AlzAs (0 <z <1, y <z) are laminated. Since the GaAs substrate easily absorbs light, it is finally removed. Is done.

このようなダブルヘテロ構造の赤色発光ダイオードで
はかなり高輝度のものが得られているが、ダブルヘテロ
構造での活性層（ｐ−Ga1-yAlyAs層）は１μｍ程度の層
厚しかなく、この活性層の成長の制御が極めて困難で、
製造方法が複雑である。このため、ウエハの歩留りが低
く、量産も困難で従つて値段も高いという問題がある。
加えて、GaAs基板を除去した場合にはその後の工程にお
いてウエハ割れがしばしば生じ、歩留りがさらに低下す
るという欠点がある。Although a red light emitting diode having such a double hetero structure has a considerably high brightness, the active layer (p-Ga 1-y AlyAs layer) in the double hetero structure has a layer thickness of only about 1 μm. It is extremely difficult to control the growth of the active layer,
The manufacturing method is complicated. Therefore, there is a problem that the yield of the wafer is low, mass production is difficult, and the price is high.
In addition, when the GaAs substrate is removed, wafer cracking often occurs in the subsequent steps, and the yield is further reduced.

ところで、従来、前述のｐ−GaAs基板/p−GaAlAs/n−
GaAlAs構造のpnシングルヘテロ接合型発光ダイオードに
おける最上層のｎ−GaAlAs層はpn接合を構成する層では
あるが理論的には発光層として機能せず、光学的には単
に光の透過層となると考えられていた。このため、従来
の発光ダイオードでは、ｎ−GaAlAs層は薄い方が良いと
考えられ、製造上の容易さ等の点から、一般に15μｍ乃
至35μｍの層厚に設定されていた。By the way, the conventional p-GaAs substrate / p-GaAlAs / n-
The uppermost n-GaAlAs layer in a pn single heterojunction light emitting diode with a GaAlAs structure is a layer that constitutes a pn junction, but does not theoretically function as a light emitting layer, and optically simply serves as a light transmission layer. Was thought. For this reason, in the conventional light emitting diode, it is considered that the n-GaAlAs layer is preferably thinner, and the thickness is generally set to 15 μm to 35 μm from the viewpoint of easiness in manufacturing and the like.

ところが本発明者らがｎ−GaAlAs層厚と発光ダイオー
ドの光出力との関係を調べてみたところ、ｎ−GaAlAs層
を厚くした方が高い光出力を得られることが判明した。However, the present inventors have examined the relationship between the thickness of the n-GaAlAs layer and the light output of the light emitting diode. As a result, it has been found that a higher light output can be obtained by increasing the thickness of the n-GaAlAs layer.

〔発明の目的〕[Object of the invention]

本発明は上記のような点に鑑みなされたもので、歩留
り良く低価格で量産可能な高輝度の発光ダイオードを提
供することを目的とする。The present invention has been made in view of the above points, and has as its object to provide a high-brightness light-emitting diode that can be mass-produced at a low cost with good yield.

〔発明の概要〕[Summary of the Invention]

すなわち本発明による発光ダイオードでは、ｐ−GaAs
基板上に成長形成されたｐ−Ga1-yAlyAs層と、このｐ−
Ga1-yAlyAs層上に積層形成された層厚が40μｍ以上のｎ
−Ga1-xAlxAs層とを具備するものである。（但し、変数
x,yは０＜ｘ1,0ｙ＜1,x＞ｙの関係を満足する。） 〔発明の実施例〕 第１図は、ｐ−GaAs基板上にｐ−Ga1-yAlyAs層および
ｎ−Ga1-xAlxAs層（但し、０ｙ＜ｘ１）を順に積層
して形成した発光ダイオードの、ｎ−GaAlAs層の層厚と
発光出力との関係を調べた結果を示すグラフである。こ
のグラフの光出力は従来のｎ−GaAlAs層厚がおよそ30μ
ｍの発光ダイオードにおける光出力で規格化したもので
ある。That is, in the light emitting diode according to the present invention, p-GaAs
A p-Ga 1-y AlyAs layer grown and formed on a substrate;
N having a layer thickness of 40 μm or more laminated on the Ga 1-y AlyAs layer
-Ga 1-x AlxAs layer. (However, variables
x and y satisfy the relationship of 0 <x1,0y <1, x> y. Embodiment of the Invention FIG. 1 shows light emission formed by sequentially stacking a p-Ga 1-y AlyAs layer and an n-Ga 1-x AlxAs layer (0y <x1) on a p-GaAs substrate. 4 is a graph showing a result of examining a relationship between a layer thickness of an n-GaAlAs layer and a light emission output of a diode. The optical output of this graph shows that the thickness of the conventional n-GaAlAs layer is about 30 μm.
It is standardized by the light output of the m light emitting diodes.

このグラフから明らかなようにｎ−GaAlAs層の厚い方
が薄いものに比らべて大きい光出力が得られる。As is clear from this graph, a thicker n-GaAlAs layer provides a larger light output than a thinner n-GaAlAs layer.

尚、上記発光ダイオードにおいて、ｐ−Ga1-yAlyAs層
とｎ−Ga1-xAlxAs層との間にｘ＞ｙの条件が必要である
が、これはこれらのエピタキシヤル層中にｘ＜ｙなる条
件の領域があつた場合、ｐ−GaAlAs層で発光した光がｎ
−GaAlAs層で吸収され発光出力が低下することを防ぐた
めである。In the above-mentioned light-emitting diode, the condition of x> y is required between the p-Ga 1-y AlyAs layer and the n-Ga 1-x AlxAs layer. This is because x <y in these epitaxial layers. When there is a region under the condition of y, the light emitted from the p-GaAlAs layer becomes n
-This is for preventing the light emission output from being reduced due to absorption by the GaAlAs layer.

次に、上記ｐ−GaAs基板/p−GaAlAs/n−GaAlAs構造の
発光ダイオードの製造過程を具体的に説明する。Next, the manufacturing process of the light emitting diode having the p-GaAs substrate / p-GaAlAs / n-GaAlAs structure will be specifically described.

第１実施例 ｐ型成長溶液溜およびｎ型成長溶液溜を有するカーボ
ンボードを用意し、次のような手順で液相成長を行う。
上記ｐ型成長溶液溜には例えばそれぞれガリウム150g、
砒化ガリウム6.8g、アルミニウム190mg、亜鉛230mgを入
れ、上記ｎ型成長溶液溜にはGa150g、砒化ガリウム4.5
g、アルミニウム405mg、テルル7mgを入れて融液と成
す。そして、第22図に示す温度スケジユールに従い、H2
雰囲気中でまずボートを850℃に設定し溶液を均質化さ
せる。そして第２図のＡ点において、ｐ型底長溶液とｐ
型GaAs基板とを接触させ、−0.5℃／分の冷却速度で830
℃まで降温する。そして830℃を５分保持した後、Ｂ点
でｐ型成長溶液を基板から分離し、直ちにｎ型成長溶液
と接触させ−0.5℃／分で650℃まで降温した後、Ｃ点で
基板から溶液を分離し自然放冷する。First Example A carbon board having a p-type growth solution reservoir and an n-type growth solution reservoir is prepared, and liquid phase growth is performed in the following procedure.
For example, each of the p-type growth solution reservoirs has 150 g of gallium,
6.8 g of gallium arsenide, 190 mg of aluminum, and 230 mg of zinc were put, and 150 g of Ga and 4.5 g of gallium arsenide were added to the n-type growth solution reservoir.
g, 405 mg of aluminum and 7 mg of tellurium are added to form a melt. Then, according to the temperature schedule shown in FIG. 22, H 2
First set the boat to 850 ° C in the atmosphere and homogenize the solution. Then, at the point A in FIG. 2, the p-type bottom length solution and p
GaAs substrate at a cooling rate of -0.5 ° C / min.
Cool down to ° C. After maintaining the temperature at 830 ° C. for 5 minutes, the p-type growth solution is separated from the substrate at the point B, immediately brought into contact with the n-type growth solution, and the temperature is lowered to 650 ° C. at −0.5 ° C./min. And allowed to cool naturally.

この工程によつて、ｐ型CaAs基板上に層厚がおよそ20
μｍのｐ−Ga1-yAlyAs層（ｙはおよそ0.35以下）および
層厚がおよそ55μｍのｎ−Ga1-yAlxAs層（ｘは0.6乃至
0.7程度）が積層した発光ダイオードウエーハが形成さ
れる。By this step, a layer thickness of about 20 is formed on the p-type CaAs substrate.
μm p-Ga 1-y AlyAs layer (y is about 0.35 or less) and n-Ga 1-y AlxAs layer having a layer thickness of about 55 μm (x is 0.6 to
(Approximately 0.7) to form a light-emitting diode wafer.

第２実施例 ｐ型成長溶液溜および第1,第２のｎ型成長溶液溜を有
するカーボンボートを用意する。そして、ガリウム150
g、砒化ガリウム6.8g、アルミニウム190mgおよび亜鉛23
0mgを、ｐ型成長溶液溜に入れ、第1n型成長溶液溜およ
び第２型成長溶液溜のいずれにも、ガリウム150g、砒化
ガリウム4.5g、アルミニウム405mgおよびテルルηmgを
入れる。その後、H2雰囲気中で第３図に示す温度スケジ
ユールに従い結晶成長を行なう。すなわち、ボート全体
を850℃一定とすることにより、溶液を均質化せしめ
る。次に第３図のＡ点において、ｐ型成長溶液とｐ型Ga
As基板とを接触させ、−0.5℃／分の冷却速度で830℃ま
で降温する。そして、830℃を５分保持した後、Ｂ点で
ｐ型成長溶液を基板から分離し、直ちに第1n型成長溶液
を接触させ、−0.5℃／分で650℃まで降温し、Ｃ点で基
板から溶液を分離する。さらに830℃までボートを昇温
後、１時間保持し第2n型成長溶液を均質化せしめた後、
Ｄ点で基板に接触させ、−0.5℃／分の冷却速度で650℃
まで降温する。そして、Ｅ点で基板から溶液を分離し、
結晶成長を終了し自然放冷させる。この工程により、ｐ
型基板上に層厚がおよそ20μｍのｐ−Ga1-yAlyAs（ｙは
およそ0.35以下）および層厚がおよそ75μｍのｎ−Ga
1-xAlxAs（ｘは0.6〜0.7程度）の積層したエピタキシヤ
ル層が形成される。Second Embodiment A carbon boat having a p-type growth solution reservoir and first and second n-type growth solution reservoirs is prepared. And gallium 150
g, gallium arsenide 6.8 g, aluminum 190 mg and zinc 23
0 mg is placed in the p-type growth solution reservoir, and 150 g of gallium, 4.5 g of gallium arsenide, 405 mg of aluminum and η mg of tellurium are placed in both the first n-type growth solution reservoir and the second-type growth solution reservoir. Thereafter, crystal growth is performed in an H 2 atmosphere according to the temperature schedule shown in FIG. That is, the solution is homogenized by keeping the entire boat at 850 ° C. Next, at the point A in FIG. 3, the p-type growth solution and the p-type Ga
The substrate is brought into contact with the As substrate, and the temperature is lowered to 830 ° C. at a cooling rate of −0.5 ° C./min. Then, after maintaining the temperature at 830 ° C. for 5 minutes, the p-type growth solution is separated from the substrate at the point B, immediately brought into contact with the first n-type growth solution, and the temperature is lowered to −650 ° C. at −0.5 ° C./min. From the solution. After the boat was further heated to 830 ° C, it was maintained for 1 hour to homogenize the 2n-type growth solution,
Contact the substrate at point D, 650 ℃ at a cooling rate of -0.5 ℃ / min
Cool down to Then, the solution is separated from the substrate at point E,
The crystal growth is completed and the mixture is allowed to cool naturally. By this step, p
P-Ga 1-y AlyAs having a layer thickness of about 20 μm (y is about 0.35 or less) and n-Ga having a layer thickness of about 75 μm
A stacked epitaxial layer of 1-x AlxAs (x is about 0.6 to 0.7) is formed.

以上のようにして得られた発光ダイオードでは、ｎ−
GaAlAs層の層厚を40μｍ以上とすることで、10％乃至30
％程度の光出力の増加がみられた。このようにｎ−GaAl
As層を厚くすることで発光出力の増加が見られる原因に
ついては明らかでない。In the light emitting diode obtained as described above, n-
By setting the thickness of the GaAlAs layer to 40 μm or more, 10% to 30%
% Increase in light output was observed. Thus, n-GaAl
It is not clear why the emission output is increased by increasing the thickness of the As layer.

尚、第１図において、比較のために示したｎ−GaAlAs
層の層厚が30μｍよりも薄い発光ダイオードは、通常の
製造工程によりｐ−GaAlAs液相成長層にまず約30μｍの
ｎ−GaAlAs層を有する発光ダイオードを形成した後、エ
ツチングによりｎ−GaAlAs層を薄層化して得たものであ
る。In FIG. 1, n-GaAlAs shown for comparison is shown.
For a light emitting diode having a layer thickness of less than 30 μm, a light emitting diode having an n-GaAlAs layer of about 30 μm is first formed on a p-GaAlAs liquid phase growth layer by a normal manufacturing process, and then the n-GaAlAs layer is etched. It was obtained by thinning.

また、本発明による発光ダイオードは、発光ダイオー
ドランプ用の外囲器に組み込んだ場合、さらに次のよう
な効果が見られる。Further, when the light emitting diode according to the present invention is incorporated in an envelope for a light emitting diode lamp, the following effects are further obtained.

すなわち、第４図に示すように、発光ダイオードチツ
プ10はリードフレーム11の素子配設台12に形成された反
射皿13にマウントされ導電性ペースト14により接着され
るのであるが、この反射皿13は深さが300μｍ程度と浅
い。このため、発光ダイオードチツプ10の発光層位置は
できるだけ反射皿13の底に近い方が効果的である。一
方、一般に発光ダイオードチツプ10では、ある一定以上
のチツプの厚みが必要であるが、上記のように本実施例
装置では最上層となるｎ−GaAlAs層103が厚いため、GaP
基板101を薄くでき発光層となるｐ−GaAlAs層102の位置
が相対的に低くなるからである。That is, as shown in FIG. 4, the light emitting diode chip 10 is mounted on a reflection plate 13 formed on the element mounting table 12 of the lead frame 11 and is adhered by a conductive paste 14. Has a shallow depth of about 300 μm. For this reason, it is effective that the light emitting layer position of the light emitting diode chip 10 is as close to the bottom of the reflection plate 13 as possible. On the other hand, the general light emitting diode multichip 10, it is necessary thickness of more than a certain chip, for thicker n-GaAlAs layer 10 3 is the top layer in the present embodiment apparatus as described above, GaP
Position of the p-GaAlAs layer 10 2 as an emission layer can be made thin the substrate 10 1 is because the relatively low.

尚、ｎ−GaAlAs層を100μｍ以上の層厚で形成するの
は、製造技術上困難であり、コスト高にもなるので現実
的ではない。It is not practical to form the n-GaAlAs layer with a layer thickness of 100 μm or more, because it is difficult in terms of manufacturing technology and increases the cost.

〔発明の効果〕〔The invention's effect〕

以上のように本発明によれば、シングルヘテロ接合型
であるためダブルヘテロ接合型のものに比らべ活性層の
層厚の制御等の製造工程が容易となり、量産的に優れ、
さらに従来のシングルヘテロ接合型のものに比らべ発光
出力が高く、安価に歩留り良く生産可能な発光ダイオー
ドを提供することができる。As described above, according to the present invention, the manufacturing process such as control of the layer thickness of the active layer is easier than that of the double hetero junction type because of the single hetero junction type, which is excellent in mass production,
Further, it is possible to provide a light-emitting diode that has a higher light-emitting output than conventional single-heterojunction-type devices and that can be produced inexpensively and with good yield.

【図面の簡単な説明】[Brief description of the drawings]

第１図はｎ−GaAlAs層厚と発光出力との関係を示すグラ
フ、第２図および第３図はそれぞれ本発明の一実施例に
係る発光ダイオードの製造工程における温度スケジユー
ルを示す図、第４図は発光ダイオードランプの要部の断
面構造を示す図である。 10……発光ダイオードチツプ、101……ｐ−GaAs基板、1
02……Ｐ−GaAlAs層、103……ｎ−GaAlAs層。FIG. 1 is a graph showing the relationship between the n-GaAlAs layer thickness and the light emission output, and FIGS. 2 and 3 are diagrams showing temperature schedules in the manufacturing process of a light emitting diode according to one embodiment of the present invention. The figure is a diagram showing a cross-sectional structure of a main part of a light emitting diode lamp. 10 ... LED chip, 10 1 ... p-GaAs substrate, 1
0 2 ... P-GaAlAs layer, 10 3 ... N-GaAlAs layer.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】ｐ型Gal−yAlyAsからなる第１の結晶層
と、この第１の結晶層上に形成され、x,yがそれぞれ０
≦ｙ＜1,0＜ｘ≦1,x＞ｙを満足する変数として示された
ｎ型Gal−xAlxAsからなる第２の結晶層とを具備し、上
記第１の結晶層と第２の結晶層との接合面でx,yを不連
続にすることにより、上記第１の結晶層と第２の結晶層
との接合面付近の第１結晶層を主たる発光領域とするシ
ングルヘテロ接合型発光ダイオードにおいて、上記第２
の結晶層の膜厚が40μｍ以上100μｍ未満であることを
特徴とする発光ダイオード。1. A first crystal layer made of p-type Gal-yAlyAs, and a first crystal layer formed on the first crystal layer, wherein x and y are each 0.
A second crystal layer made of n-type Gal-xAlxAs indicated as a variable satisfying ≦ y <1,0 <x ≦ 1, x> y, wherein the first crystal layer and the second crystal layer By making x and y discontinuous at the junction surface with the layer, a single heterojunction type light emission having the first crystal layer near the junction surface between the first crystal layer and the second crystal layer as a main light emitting region In the diode, the second
Wherein the thickness of the crystal layer is 40 μm or more and less than 100 μm.
JP5061084A 1984-03-16 1984-03-16 Light emitting diode Expired - Lifetime JP2621850B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5061084A JP2621850B2 (en) 1984-03-16 1984-03-16 Light emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5061084A JP2621850B2 (en) 1984-03-16 1984-03-16 Light emitting diode

Publications (2)

Publication Number Publication Date
JPS60194585A JPS60194585A (en) 1985-10-03
JP2621850B2 true JP2621850B2 (en) 1997-06-18

Family

ID=12863736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5061084A Expired - Lifetime JP2621850B2 (en) 1984-03-16 1984-03-16 Light emitting diode

Country Status (1)

Country Link
JP (1) JP2621850B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947478B2 (en) * 1974-05-28 1984-11-19 アレクサンドロウイツチ シヤルマカドゼ レバズ Semiconductor light emitting diode and manufacturing method
JPS5866375A (en) * 1981-10-16 1983-04-20 Fujitsu Ltd Light emitting diode

Also Published As

Publication number Publication date
JPS60194585A (en) 1985-10-03

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