JPH0645470A - Package for storing semiconductor chip - Google Patents

Package for storing semiconductor chip

Info

Publication number
JPH0645470A
JPH0645470A JP4193618A JP19361892A JPH0645470A JP H0645470 A JPH0645470 A JP H0645470A JP 4193618 A JP4193618 A JP 4193618A JP 19361892 A JP19361892 A JP 19361892A JP H0645470 A JPH0645470 A JP H0645470A
Authority
JP
Japan
Prior art keywords
lid
semiconductor element
package
semiconductor chip
insulating base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4193618A
Other languages
Japanese (ja)
Other versions
JP2962939B2 (en
Inventor
Hiroshi Matsumoto
弘 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4193618A priority Critical patent/JP2962939B2/en
Publication of JPH0645470A publication Critical patent/JPH0645470A/en
Application granted granted Critical
Publication of JP2962939B2 publication Critical patent/JP2962939B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a package for storing a semiconductor chip so that the inside of the package consisting of an insulating base body and a lid body can be hermetically sealed and that the semiconductor chip inside the package can be normally and stably operated. CONSTITUTION:This package for storing a semiconductor chip consists of an insulating base body 1 and a lid body 2 and has a space inside the package for storing the semiconductor chip, and the lid body 2 is less than 0.4mm thick and a protrusion 2a is formed on the inner wall of the lid body 2 so as to be opposite to the space for storing the semiconductor chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.

【0002】[0002]

【従来の技術】従来、LSI(大規模集積回路素子) 等の半
導体素子を収容するためのパッケージ、例えばガラス封
止型の半導体素子収納用パッケージは図2 に示すように
通常、酸化アルミニウム質焼結体、ムライト質焼結体、
窒化アルミニウム質焼結体、窒化珪素質焼結体等の電気
絶縁材料から成り、中央部に半導体素子23を載置収容す
るための凹部21a を有し、上面に封止用のガラス層24が
被着された絶縁基体21と、同じく電気絶縁材料から成
り、中央部に半導体素子23を収容する空所を形成するた
めの凹部を有し、下面に封止用のガラス層25が被着され
た蓋体22と、内部に収容する半導体素子23を外部の電気
回路に電気的に接続するための外部リード端子26とによ
り構成されており、絶縁基体21の上面に外部リード端子
26を載置させるとともに予め被着させておいた封止用の
ガラス層24を溶融させることによって外部リード端子26
を絶縁基体21上に仮止めし、次に前記絶縁基体21の凹部
21a 底面に半導体素子23を取着するとともに該半導体素
子23の各電極をボンディングワイヤ27を介して外部リー
ド端子26に接続し、しかる後、絶縁基体21と蓋体22とを
その相対向する主面に被着させておいた各々の封止用の
ガラス層24、25を約400℃の温度で溶融一体化させ、
絶縁基体21と蓋体22とから成る容器を気密に封止する
ことによって製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a package for housing a semiconductor element such as an LSI (Large Scale Integrated Circuit Element), for example, a glass-sealed type semiconductor element housing package is usually made of aluminum oxide as shown in FIG. Union, mullite sintered body,
It is made of an electrically insulating material such as an aluminum nitride sintered body or a silicon nitride sintered body, has a recess 21a for mounting and housing the semiconductor element 23 in the center, and a glass layer 24 for sealing on the upper surface. The insulating substrate 21 that has been deposited and the same electrically insulating material, which has a recess for forming a cavity for accommodating the semiconductor element 23 in the center, and a glass layer 25 for sealing is deposited on the lower surface. Lid 22 and an external lead terminal 26 for electrically connecting the semiconductor element 23 housed inside to an external electric circuit, and the external lead terminal is provided on the upper surface of the insulating base 21.
The external lead terminals 26 are formed by placing 26 and melting the glass layer 24 for sealing which has been previously attached.
Is temporarily fixed on the insulating base 21, and then the concave portion of the insulating base 21 is
The semiconductor element 23 is attached to the bottom surface of the semiconductor device 21a, and each electrode of the semiconductor element 23 is connected to the external lead terminal 26 via the bonding wire 27. Thereafter, the insulating base 21 and the lid 22 are opposed to each other. The glass layers 24 and 25 for sealing which have been adhered to the surfaces are melted and integrated at a temperature of about 400 ° C.,
A semiconductor device as a product is obtained by hermetically sealing a container composed of the insulating base 21 and the lid 22.

【0003】尚、前記絶縁基体21及び蓋体22は、例えば
酸化アルミニウム質焼結体から成る場合、一般にアルミ
ナ(Al 2 O 3 ) 、シリカ(SiO2 ) 等に適当な有機溶剤、
溶媒を添加混合して得た原料粉末を所定形状のプレス金
型内に充填するとともに一定圧力で押圧して成形し、し
かる後、前記成形品を約1500℃の温度で焼成することに
よって製作されている。
When the insulating substrate 21 and the lid 22 are made of, for example, an aluminum oxide sintered body, generally, an organic solvent suitable for alumina (Al 2 O 3 ) or silica (SiO 2 ) is used.
The raw material powder obtained by adding and mixing the solvent is filled in a press die of a predetermined shape and pressed at a constant pressure to be molded, and thereafter, the molded product is manufactured by firing at a temperature of about 1500 ° C. ing.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、近時、
ICカード等、情報処理装置は薄型化が急激に進み、該
情報処理装置に搭載される半導体装置もその厚みを薄く
したものが要求されるようになり、同時に半導体装置を
構成する半導体素子収納用パッケージも蓋体の厚みを0.
4mm 以下としてパッケージ全体の厚みを薄型化すること
が要求されるようになってきた。
However, in recent years,
Information processing devices such as IC cards are rapidly becoming thinner, and semiconductor devices mounted on the information processing devices are required to have thinner thicknesses, and at the same time, for semiconductor element storage that constitutes the semiconductor device. The thickness of the lid of the package is 0.
It has become necessary to reduce the thickness of the entire package to 4 mm or less.

【0005】そこで上述した従来の半導体素子収納用パ
ッケージの蓋体の厚みを0.4mm 以下とし、パッケージ全
体の厚みを薄くした場合、パッケージの蓋体は酸化アル
ミニウム質焼結体等の電気絶縁材料より成り、該酸化ア
ルミニウム質焼結体等は脆弱で機械的強度が弱いことか
ら絶縁基体と蓋体とから成る容器内部に半導体素子を気
密に収容した後、蓋体に外力が印加されると該外力によ
って蓋体が容器内部側に撓んで破損し、その結果、容器
内部の気密封止が破れ、内部に収容する半導体素子を長
期間にわたり正常、且つ安定に作動させることができな
いという欠点を招来した。
Therefore, if the thickness of the lid of the conventional package for accommodating semiconductor elements described above is set to 0.4 mm or less and the thickness of the entire package is reduced, the lid of the package is made of an electrically insulating material such as an aluminum oxide sintered body. Since the aluminum oxide sintered body and the like are fragile and have low mechanical strength, when the semiconductor element is hermetically housed in the container formed of the insulating base and the lid, an external force is applied to the lid. External force causes the lid body to bend and damage the inside of the container, and as a result, the airtight seal inside the container is broken, resulting in the drawback that the semiconductor element housed inside cannot operate normally and stably for a long period of time. did.

【0006】また同時に蓋体に外力が印加され、蓋体が
容器内部側に撓んだ場合、蓋体が絶縁基体と蓋体とを接
合させている封止用ガラス層を引っ張って割れやクラッ
クを発生させ、その結果、これによっても容器内部の気
密封止が破れ、内部に収容する半導体素子を長期間にわ
たり正常、且つ安定に作動させることができないという
欠点を有していた。
At the same time, when an external force is applied to the lid body and the lid body bends toward the inside of the container, the lid body pulls the sealing glass layer joining the insulating substrate and the lid body to break or crack. As a result, the airtight seal inside the container is broken as a result, and the semiconductor element housed inside cannot be operated normally and stably for a long period of time.

【0007】[0007]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は絶縁基体と蓋体とから成る容器内部の気
密封止を完全とし、内部に収容する半導体素子を長期間
にわたり正常、且つ安定に作動させることができる半導
体素子収納用パッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and its object is to complete hermetically sealing the inside of a container composed of an insulating base and a lid, and to store a semiconductor element housed therein for a long period of time. It is an object of the present invention to provide a package for accommodating a semiconductor element, which can operate normally and stably.

【0008】[0008]

【課題を解決するための手段】本発明は絶縁基体と蓋体
とから成り、内部に半導体素子を収容するための空所を
有する半導体素子収納用パッケージであって、前記蓋体
はその厚みが0.4mm 以下で、且つ半導体素子を収容する
空所に対接する面に突起が形成されていることを特徴と
するものである。
SUMMARY OF THE INVENTION The present invention is a semiconductor element housing package comprising an insulating base and a lid, and having a cavity for housing a semiconductor element therein, wherein the lid has a thickness of It is characterized in that a protrusion is formed on the surface of 0.4 mm or less and in contact with the void for housing the semiconductor element.

【0009】[0009]

【作用】本発明の半導体素子収納用パッケージによれ
ば、半導体素子を収容するための容器を構成する蓋体の
半導体素子を収容する空所に対接する面に突起を設けた
ことから蓋体の厚みが0.4mm 以下と薄くなったとしても
外力印加によって大きく撓むことはなく、該撓みに起因
して破損することは皆無となる。
According to the package for accommodating semiconductor elements of the present invention, since the projections are provided on the surface of the lid constituting the container for accommodating the semiconductor elements, the surface facing the cavity for accommodating the semiconductor elements, Even if the thickness is reduced to 0.4 mm or less, it is not largely bent by the application of an external force, and there is no possibility of damage due to the bending.

【0010】また蓋体の大きな撓みがなくなることから
絶縁基体と蓋体とを接合させる封止用ガラス層に割れや
クラック等が発生することもなくなり、その結果、絶縁
基体と蓋体とから成る容器内部の気密封止を完全とし内
部に収容する半導体素子を長期間にわたり正常且つ安定
に作動させることが可能となる。
Further, since the lid is not largely bent, the glass layer for sealing which joins the insulating base and the lid is not cracked or cracked. As a result, the insulating base and the lid are formed. The airtight sealing inside the container is completed, and the semiconductor element housed inside can be normally and stably operated for a long period of time.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 は本発明の半導体素子収納用パッケージの一実
施例を示し、1 は絶縁基体、2 は蓋体である。この絶縁
基体1 と蓋体2 とで半導体素子3 を収容するための容器
4 が構成される。
The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a package for housing a semiconductor device of the present invention, in which 1 is an insulating base and 2 is a lid. A container for housing the semiconductor element 3 with the insulating base 1 and the lid 2.
4 are composed.

【0012】前記絶縁基体1 は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体等の電気絶縁材料から成り、その上面略
中央部に半導体素子3 を収容するための凹部1aが設けて
あり、該凹部1a底面には半導体素子3 がガラス、樹脂、
ロウ材等の接着材を介して取着固定される。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. A recess 1a for accommodating 3 is provided, and the semiconductor element 3 is provided on the bottom surface of the recess 1a with glass, resin,
It is attached and fixed via an adhesive material such as a brazing material.

【0013】前記絶縁基体1 は例えば酸化アルミニウム
質焼結体から成る場合、アルミナ(Al 2 O 3 ) 、シリカ
(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等に適当
な有機溶剤、溶媒を添加混合してセラミック原料粉末を
調整するとともに該セラミック原料粉末を従来周知のプ
レス成形法によって成形し、しかる後、前記成形体を約
1500℃の温度で焼成することによって製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, alumina (Al 2 O 3 ) or silica is used.
(SiO 2 ), calcia (CaO), magnesia (MgO), etc. are mixed with a suitable organic solvent and solvent to prepare a ceramic raw material powder and the ceramic raw material powder is molded by a conventionally known press molding method. After that, the molded body is
It is manufactured by firing at a temperature of 1500 ° C.

【0014】また前記絶縁基体1 はその上面に金属材料
から成る外部リード端子5 が封止用のガラス層6 を介し
て仮止めされており、該外部リード端子5 は内部に収容
する半導体素子3 を外部電気回路に接続する作用を為
し、その一端には半導体素子3の各電極がボンディング
イヤ7 を介して接続され、また他端は外部電気回路に半
田等のロウ材を介して接続される。
An external lead terminal 5 made of a metallic material is temporarily fixed to the upper surface of the insulating substrate 1 through a glass layer 6 for sealing, and the external lead terminal 5 is a semiconductor element 3 housed inside. Is connected to an external electric circuit, each electrode of the semiconductor element 3 is connected to one end of the same through a bonding ear 7, and the other end is connected to an external electric circuit through a brazing material such as solder. It

【0015】前記外部リード端子5 はコバール金属(Fe-
Ni-Co 合金) や42アロイ(Fe-Ni合金) 等の金属材料から
成り、該コバール金属等のインゴット( 塊) を従来周知
の圧延加工法や打ち抜き加工法等を採用することによっ
て所定の板状に形成される。
The external lead terminals 5 are made of Kovar metal (Fe-
Ni-Co alloy), 42 alloy (Fe-Ni alloy), or other metal material, and the ingot (lump) of Kovar metal or the like is formed into a prescribed plate by adopting the conventionally known rolling or punching method. Formed into a shape.

【0016】尚、前記外部リード端子5 はその表面にニ
ッケル、金等から成る良導電性で、且つ耐蝕性に優れた
金属をメッキ法により1.0 乃至20.0μm の厚みに層着さ
せておくと、外部リード端子5 の酸化腐食を有効に防止
するとともに外部リード端子5 とボンディングワイヤ7
及び外部電気回路との電気的接続を良好となすことがで
きる。従って、前記外部リード端子5 はその表面にニッ
ケル、金等をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくことが好ましい。
It should be noted that the external lead terminal 5 is formed by depositing a metal of nickel, gold or the like, which has good conductivity and corrosion resistance, on the surface thereof by plating to a thickness of 1.0 to 20.0 μm. Effectively prevents oxidative corrosion of the external lead terminals 5, and also prevents external lead terminals 5 and bonding wires 7
And good electrical connection with an external electric circuit can be achieved. Therefore, it is preferable to deposit nickel, gold or the like on the surface of the external lead terminal 5 by plating to a thickness of 1.0 to 20.0 μm.

【0017】また前記外部リード端子5 が仮止めされた
絶縁基体1 の上面には蓋体2 が該蓋体2 の下面に被着さ
せた封止用のガラス層8 と絶縁基体1 の上面に被着させ
たガラス層6 とを溶融一体化させることによって接合さ
れ、これによって絶縁基体1と蓋体2 とから成る容器4
内部に半導体素子3 が気密に封止される。
On the upper surface of the insulating base body 1 to which the external lead terminals 5 are temporarily fixed, the lid body 2 is attached to the lower surface of the lid body 2 for sealing, and on the upper surface of the insulating base body 1. The adhered glass layer 6 and the glass layer 6 are joined together by fusion, whereby a container 4 composed of an insulating base 1 and a lid 2 is formed.
The semiconductor element 3 is hermetically sealed inside.

【0018】前記蓋体2 は酸化アルミニウム質焼結体、
ムライト質焼結体、窒化アルミニウム質焼結体、炭化珪
素質焼結体等の電気絶縁材料から成り、例えば酸化アル
ミニウム質焼結体から成る場合には絶縁基体1 と同様の
方法、即ち、アルミナ、シリカ、カルシア、マグネシア
等に適当な有機溶剤、溶媒を添加混合してセラミック原
料粉末を調整するとともに該セラミック原料粉末を従来
周知のプレス成形法によって成形し、しかる後、これを
約1500℃の温度で焼成することによって製作される。
The lid 2 is an aluminum oxide sintered body,
If it is made of an electrically insulating material such as a mullite sintered body, an aluminum nitride sintered body, or a silicon carbide sintered body, for example, if it is made of an aluminum oxide sintered body, the same method as that for the insulating substrate 1, that is, alumina is used. , Silica, calcia, magnesia, etc., an appropriate organic solvent, a solvent is added and mixed to prepare a ceramic raw material powder, and the ceramic raw material powder is molded by a conventionally known press molding method. It is manufactured by firing at a temperature.

【0019】また前記蓋体2 は半導体素子を収容する空
所に対接する面に突起2aが形成されている。
Further, the lid 2 has a protrusion 2a formed on a surface thereof which is in contact with a space for housing a semiconductor element.

【0020】前記突起2aは蓋体2 が0.4mm 以下と薄く成
り、外力印加によって撓もうとするのを阻止する補強部
材として作用し、これによって絶縁基体1 と蓋体2 とか
ら成る容器内部に半導体素子3 を気密に収容した後、蓋
体2 に外力が印加されたとしても蓋体2 が容器内部側に
撓んで破損することは皆無となり、その結果、容器内部
の気密封止を完全として、内部に収容する半導体素子3
を長期間にわたり正常、且つ安定に作動させることがで
きる。
The projections 2a are thinned to 0.4 mm or less in the lid body 2 and act as a reinforcing member for preventing the lid body 2 from trying to bend due to the application of an external force. After the semiconductor element 3 is housed in an airtight manner, even if an external force is applied to the lid body 2, the lid body 2 is never bent and damaged inside, and as a result, the inside of the vessel is completely hermetically sealed. , Semiconductor element 3 housed inside
Can be operated normally and stably for a long period of time.

【0021】更に前記蓋体2 は突起2aによって撓むこと
が殆どないことから蓋体2 の撓みに起因して発生する封
止用ガラス層6 、8 の破損も殆どなく、これによっても
半導体素子を収容する容器の気密封止を完全となすこと
ができる。
Further, since the lid body 2 is hardly bent by the protrusion 2a, the sealing glass layers 6 and 8 caused by the bending of the lid body 2 are hardly damaged. It is possible to completely seal the container for housing

【0022】尚、前記蓋体2 に設ける突起2aはその面積
が0.01mm2 未満であり、且つ高さが0.05mm未満であると
蓋体2 の撓みを有効に阻止するのが困難となるため面積
は0.01mm2 以上に、高さは0.05mm以上にするのが好まし
い。また突起2aは蓋体2 の中央部に正方形状、長方形
状、十字形状に設けておくと蓋体2 の撓みを極めて有効
に阻止することができる。
If the area of the projection 2a provided on the lid 2 is less than 0.01 mm 2 and the height is less than 0.05 mm, it is difficult to effectively prevent the lid 2 from bending. The area is preferably 0.01 mm 2 or more and the height is preferably 0.05 mm or more. If the protrusion 2a is provided in the central portion of the lid body 2 in a square shape, a rectangular shape, or a cross shape, the bending of the lid body 2 can be very effectively prevented.

【0023】また一方、前記絶縁基体1 の上面に被着さ
せた封止用のガラス層6 及び蓋体2の下面に被着させた
ガラス層8 はそれぞれ絶縁基体1 及び蓋体2 が酸化アル
ミニウム質焼結体から成る場合には酸化鉛50.0乃至60.0
重量%、酸化珪素1.0 乃至5.0 重量%、酸化ホウ素3.0
乃至13.0重量%、酸化ビスマス3.0 乃至13.0重量%に、
フィラーとしてのコージライトを10.0乃至20.0重量%、
チタン酸錫系化合物を10.0乃至20.0重量%含有させたガ
ラスが好適に使用され、両ガラス層6 、8 を加熱溶融さ
せ一体化させることによって絶縁基体1 と蓋体2 とから
成る容器4 内部に半導体素子3 が気密に封止される。
On the other hand, the glass layer 6 for sealing which is adhered to the upper surface of the insulating base 1 and the glass layer 8 which is adhered to the lower surface of the lid 2 are made of aluminum oxide as the insulating base 1 and the lid 2, respectively. Lead oxide 50.0 to 60.0 when composed of a porous sintered body
% By weight, silicon oxide 1.0 to 5.0% by weight, boron oxide 3.0
To 13.0 wt%, bismuth oxide 3.0 to 13.0 wt%,
10.0 to 20.0% by weight of cordierite as a filler,
A glass containing 10.0 to 20.0% by weight of a tin titanate-based compound is preferably used, and both glass layers 6 and 8 are heated and melted to be integrated into a container 4 composed of an insulating substrate 1 and a lid 2. The semiconductor element 3 is hermetically sealed.

【0024】前記封止用のガラス層6 、8 はその軟化溶
融温度が約400 ℃と低く、そのため封止用ガラス層6 、
8 を溶融一体化させて絶縁基体1 と蓋体2 とから成る容
器4内部に半導体素子3 を気密に封止する際、半導体素
子3 に封止用ガラス層6 、8を溶融させるための熱が印
加されたとしても半導体素子3 に熱破壊や特性に熱変化
を生じさせることはなく、内部に収容する半導体素子3
を正常、且つ安定に作動させることが可能となる。
The glass layers 6 and 8 for sealing have a low softening and melting temperature of about 400 ° C. Therefore, the glass layers 6 and 8 for sealing are
When the semiconductor element 3 is hermetically sealed in the container 4 composed of the insulating base 1 and the lid 2 by melting and integrating 8 with each other, the heat for melting the sealing glass layers 6 and 8 in the semiconductor element 3 is used. Is applied, it does not cause thermal damage to the semiconductor element 3 or thermal change in its characteristics, and
Can be operated normally and stably.

【0025】前記封止用のガラス層6 、8 はまたその熱
膨張係数が7.1 ×10-6/ ℃であり、絶縁基体1 及び蓋体
2 を構成する酸化アルミニウム質焼結体の熱膨張係数
(6.5〜7.5 ×10-6/ ℃) と近似することから、絶縁基体
1 と蓋体2 とを封止用のガラス層6 、8 を溶融一体化さ
せ、絶縁基体1 と蓋体2 とから成る容器4 内部に半導体
素子3 を気密に封止する際、絶縁基体1 と蓋体2 と封止
用のガラス層6 、8 との接合を極めて強固として容器4
内部に半導体素子3 を完全に気密封止することが可能と
なる。
The glass layers 6 and 8 for sealing also have a thermal expansion coefficient of 7.1 × 10 −6 / ° C., and the insulating substrate 1 and the lid body are
Coefficient of thermal expansion of aluminum oxide-based sintered compacts that constitute No. 2
(6.5 to 7.5 × 10 -6 / ℃)
When the semiconductor element 3 is hermetically sealed inside the container 4 composed of the insulating base 1 and the lid 2, the glass layers 6 and 8 for sealing the 1 and the lid 2 are fused and integrated. The container 4 with the lid 2 and the glass layers 6 and 8 for sealing made extremely strong.
The semiconductor element 3 can be completely hermetically sealed inside.

【0026】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹部1a底面に半導体素子3 を
取着固定するとともに該半導体素子3 の各電極をボンデ
ィングワイヤ7 により外部リード端子5 に接続させ、し
かる後、絶縁基体1 と蓋体2とをその各々の相対向する
主面に被着させておいた封止用ガラス層6 、8 を加熱溶
融させ、接合することによって絶縁基体1 と蓋体2 とか
ら成る容器4 内部に半導体素子3 を気密に封止し、これ
によって製品としての半導体装置が完成する。
Thus, according to the package for accommodating a semiconductor element of the present invention, the semiconductor element 3 is attached and fixed to the bottom surface of the recess 1a of the insulating substrate 1 and each electrode of the semiconductor element 3 is connected to the external lead terminal 5 by the bonding wire 7. After that, the sealing glass layers 6 and 8 having the insulating substrate 1 and the lid body 2 adhered to the respective opposing main surfaces thereof are heated and melted, and bonded to form the insulating substrate 1 and The semiconductor element 3 is hermetically sealed in the container 4 composed of the lid 2 and the semiconductor device as a product is completed.

【0027】尚、本発明は上述の実施例に限定さるもの
ではなく、本発明の要旨を逸脱しない範囲であれば種々
の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention.

【0028】[0028]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子を収容するための容器を構成する蓋
体の半導体素子を収容する空所に対接する面に突起を形
成したことから蓋体の厚みが0.4mm 以下の薄いものとな
ったとしても蓋体が外力印加によって撓むことはなく、
その結果、蓋体に撓みに起因する破損が発生することは
皆無で絶縁基体と蓋体とから成る容器の気密封止を完全
とし、内部に収容する半導体素子を長期間にわたり正
常、且つ安定に作動させることができる。
According to the package for accommodating semiconductor elements of the present invention, since the projections are formed on the surface of the lid constituting the container for accommodating the semiconductor elements, which is in contact with the space for accommodating the semiconductor elements, the lid is formed. Even if the thickness of the body is as thin as 0.4 mm or less, the lid will not bend due to the application of external force,
As a result, there is no possibility that the lid will be damaged due to bending, and the container consisting of the insulating base and the lid will be completely hermetically sealed, and the semiconductor element housed inside will be normally and stably for a long period of time. Can be activated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【図2】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 2 is a cross-sectional view of a conventional semiconductor element housing package.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 2・・・・・蓋体 2a・・・・突起 3・・・・・半導体素子 4・・・・・容器 5・・・・・外部リード端子 1 ... Insulating substrate 2 ... Lid 2a ... Protrusion 3 ... Semiconductor element 4 ... Container 5 ... External lead terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体と蓋体とから成り、内部に半導体
素子を収容するための空所を有する半導体素子収納用パ
ッケージであって、前記蓋体はその厚みが0.4mm 以下
で、且つ半導体素子を収容する空所に対接する面に突起
が形成されていることを特徴とする半導体素子収納用パ
ッケージ。
1. A semiconductor element housing package comprising an insulating base and a lid, and having a cavity for housing a semiconductor element therein, wherein the lid has a thickness of 0.4 mm or less and a semiconductor. A package for accommodating a semiconductor element, characterized in that a protrusion is formed on a surface facing a space for accommodating the element.
JP4193618A 1992-07-21 1992-07-21 Package for storing semiconductor elements Expired - Fee Related JP2962939B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4193618A JP2962939B2 (en) 1992-07-21 1992-07-21 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4193618A JP2962939B2 (en) 1992-07-21 1992-07-21 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH0645470A true JPH0645470A (en) 1994-02-18
JP2962939B2 JP2962939B2 (en) 1999-10-12

Family

ID=16310938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4193618A Expired - Fee Related JP2962939B2 (en) 1992-07-21 1992-07-21 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2962939B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008182236A (en) * 2007-01-25 2008-08-07 Osram Opto Semiconductors Gmbh Electronic device
US8330360B2 (en) 2006-12-29 2012-12-11 Osram Opto Semiconductors Gmbh Light-emitting device with supported cover

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180315894A1 (en) * 2017-04-26 2018-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8330360B2 (en) 2006-12-29 2012-12-11 Osram Opto Semiconductors Gmbh Light-emitting device with supported cover
JP2008182236A (en) * 2007-01-25 2008-08-07 Osram Opto Semiconductors Gmbh Electronic device
US8830695B2 (en) 2007-01-25 2014-09-09 Osram Opto Semiconductors Gmbh Encapsulated electronic device

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