JP2997367B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2997367B2 JP2997367B2 JP4186980A JP18698092A JP2997367B2 JP 2997367 B2 JP2997367 B2 JP 2997367B2 JP 4186980 A JP4186980 A JP 4186980A JP 18698092 A JP18698092 A JP 18698092A JP 2997367 B2 JP2997367 B2 JP 2997367B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- weight
- lid
- insulating base
- glass layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Packaging Frangible Articles (AREA)
- Glass Compositions (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.
【０００２】[0002]
【従来の技術】従来、LSI(大規模集積回路素子) 等の半
導体素子を収容するためのパッケージ、例えばガラス封
止型の半導体素子収納用パッケージは図2 に示すように
通常、酸化アルミニウム質焼結体、ムライト質焼結体、
窒化アルミニウム質焼結体、高珪素質焼結体等の電気絶
縁材料から成り、中央部に半導体素子23を載置収容する
ための凹部21a を有し、上面に封止用のガラス層24が被
着された絶縁基体21と、同じく電気絶縁材料から成り、
中央部に半導体素子23を収容する空所を形成するための
凹部を有し、下面に封止用のガラス層25が被着された蓋
体22と、内部に収容する半導体素子23を外部の電気回路
に電気的に接続するための外部リード端子26とにより構
成されており、絶縁基体21の上面に外部リード端子26を
載置させるとともに予め被着させておいた封止用のガラ
ス層24を溶融させることによって外部リード端子26を絶
縁基体21上に仮止めし、次に前記絶縁基体21の凹部21a
底面に半導体素子23を取着するとともに該半導体素子23
の各電極をボンディングワイヤ27を介して外部リード端
子26に接続し、しかる後、絶縁基体21と蓋体22とをその
相対向する主面に被着させておいた各々の封止用のガラ
ス層24、25を約400 ℃の温度で溶融一体化させ、絶縁基
体21と蓋体22とから成る容器を気密に封止することによ
って製品としての半導体装置となる。2. Description of the Related Art Conventionally, a package for accommodating a semiconductor element such as an LSI (large-scale integrated circuit element), for example, a package for accommodating a glass-encapsulated semiconductor element is usually made of aluminum oxide as shown in FIG. Sintered, mullite sintered body,
It is made of an electrically insulating material such as an aluminum nitride-based sintered body or a high silicon-based sintered body, and has a concave portion 21a for placing and housing the semiconductor element 23 in the center, and a sealing glass layer 24 on the upper surface. The insulating base 21 attached and also made of an electrically insulating material,
A lid 22 having a concave portion for forming a cavity for accommodating the semiconductor element 23 in the center, a sealing glass layer 25 adhered to the lower surface, and the semiconductor element 23 accommodated therein are externally provided. An external lead terminal 26 for electrically connecting to an electric circuit.The external lead terminal 26 is placed on the upper surface of the insulating base 21 and a sealing glass layer 24 previously applied. To temporarily fix the external lead terminals 26 on the insulating base 21, and then to the concave portions 21 a of the insulating base 21.
The semiconductor element 23 is attached to the bottom surface and the semiconductor element 23
Each electrode is connected to an external lead terminal 26 via a bonding wire 27, and thereafter, each of the sealing glass in which the insulating base 21 and the lid 22 are adhered to the opposing main surfaces thereof The layers 24 and 25 are melted and integrated at a temperature of about 400 ° C., and a container formed of the insulating base 21 and the lid 22 is hermetically sealed to provide a semiconductor device as a product.
【０００３】尚、前記絶縁基体21及び蓋体22は、例えば
酸化アルミニウム質焼結体から成る場合、一般にアルミ
ナ(Al 2 O 3 ) 、シリカ(SiO2 ) 等に適当な有機溶剤、
溶媒を添加混合して得た原料粉末を所定形状のプレス金
型内に充填するとともに一定圧力で押圧して成形し、し
かる後、前記成形品を約1500℃の温度で焼成することに
よって製作されている。When the insulating base 21 and the lid 22 are made of, for example, an aluminum oxide sintered body, an organic solvent suitable for alumina (Al 2 O 3 ), silica (SiO 2 ) or the like is generally used.
The raw material powder obtained by adding and mixing the solvent is filled in a press mold of a predetermined shape and pressed at a constant pressure to be molded, and thereafter, the molded product is manufactured by firing at a temperature of about 1500 ° C. ing.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、絶縁基体
21及び蓋体22がプレス成形したアルミナ等の原料粉末を
焼成することによって製作されており、その表面の粗さ
はRaで0.6 μm 以上と粗く、塵等の異物が強く付着し易
い状態となっている。従って、絶縁基体21もしくは蓋体
22に一旦、異物が付着すると該異物は洗浄によっても完
全に除去されず、異物が付着している絶縁基体21と蓋体
22とで半導体素子23を収容し半導体装置と成した後、外
力が印加されると該外力によって絶縁基体21もしくは蓋
体22に付着する異物が離脱飛散し、内部に収容する半導
体素子23の表面に付着して半導体素子を誤動作させた
り、半導体素子の特性に劣化を招来したりするという欠
点を有していた。However, in this conventional package for accommodating a semiconductor element, an insulating substrate is not provided.
The lid 21 and the lid 22 are manufactured by firing raw material powder such as alumina that has been press-molded, and the surface roughness is as rough as 0.6 μm or more in Ra, so that foreign substances such as dust are easily adhered. ing. Therefore, the insulating base 21 or the lid
Once the foreign matter adheres to the substrate 22, the foreign matter is not completely removed even by washing, and the insulating base 21 and the lid to which the foreign matter is attached are attached.
After the semiconductor element 23 is accommodated in the semiconductor device 23 and the semiconductor device 23 is formed, when an external force is applied, foreign matter adhering to the insulating base 21 or the lid 22 is separated and scattered by the external force, and the surface of the semiconductor element 23 accommodated therein. There is a drawback that the semiconductor element may malfunction due to adhesion to the semiconductor device or the characteristics of the semiconductor element may be deteriorated.
【０００５】[0005]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は絶縁基体や蓋体に異物が付着するのを有
効に防止するとともに付着異物の洗浄を容易、且つ完全
とし、絶縁基体と蓋体とから成る容器内部に収容される
半導体素子を正常に作動させることができる半導体素子
収納用パッケージを提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to effectively prevent foreign substances from adhering to an insulating base and a lid, and to make cleaning of adhered foreign substances easy and complete. It is an object of the present invention to provide a package for housing a semiconductor element capable of normally operating a semiconductor element housed in a container including an insulating base and a lid.
【０００６】[0006]
【課題を解決するための手段】本発明は酸化アルミニウ
ム質焼結体で形成された絶縁基体と蓋体とから成り、内
部に半導体素子を収容するための空所を有する半導体素
子収納用パッケージであって、前記絶縁基体及び蓋体の
うち少なくとも一方の半導体素子を収容する空所に対接
する面に、酸化鉛40.0乃至60.0重量％、酸化ホウ素3.0
乃至13.0重量％、酸化珪素0.5 乃至3.0 重量％、酸化ア
ルミニウム0.5 乃至3.0 重量％にフィラーとしてのチタ
ン酸鉛系化合物を10.0乃至30.0重量％、ジルコニアンシ
リケート系化合物を5.0 乃至15.0重量％含有させたガラ
スと、粒径が20.0μｍ以下の金属粉末とから成るガラス
層が被着されており、かつ前記ガラスの量が20.0乃至5
0.0重量％、金属粉末の量が50.0乃至80.0重量％である
ことを特徴とするものである。SUMMARY OF THE INVENTION The present invention relates to a semiconductor element housing package comprising an insulating base and a lid formed of an aluminum oxide sintered body and having a space for housing a semiconductor element therein. The surface of at least one of the insulating base and the lid, which is in contact with a space for accommodating a semiconductor element, has 40.0 to 60.0% by weight of lead oxide and 3.0% of boron oxide.
To 13.0% by weight, 0.5 to 3.0% by weight of silicon oxide, 0.5 to 3.0% by weight of aluminum oxide, 10.0 to 30.0% by weight of a lead titanate compound as a filler, and 5.0 to 15.0% by weight of a zirconian silicate compound. A glass layer comprising glass and a metal powder having a particle size of 20.0 μm or less is applied, and the amount of the glass is 20.0 to 5
It is characterized in that the content of the metal powder is 0.0% by weight and the amount of the metal powder is 50.0 to 80.0% by weight.
【０００７】[0007]
【作用】本発明の半導体素子収納用パッケージによれ
ば、半導体素子を収容するための容器を構成する絶縁基
体や蓋体の半導体素子を収容する空所に対接する面にガ
ラス層を被着させたことから、絶縁基体や蓋体の表面粗
さはＲa で0.3 μm 以下、Ｒmax で5.0 μm 以下の平滑
なものとなり、その結果、絶縁基体や蓋体には異物が付
着し難く、また付着した異物も容易、且つ完全に洗浄除
去することができて、異物の付着していない絶縁基体や
蓋体で半導体素子を収容し、半導体素子を正常に作動さ
せることが可能となる。According to the package for housing a semiconductor element of the present invention, a glass layer is formed on a surface of an insulating base or a lid of a container for housing the semiconductor element, the surface being in contact with a space for housing the semiconductor element. As a result, the surface roughness of the insulating substrate and the lid becomes smooth with Ra of 0.3 μm or less and Rmax of 5.0 μm or less. As a result, foreign matter hardly adheres to the insulating substrate and the lid, and adheres. Foreign matter can be easily and completely removed by washing, and the semiconductor element can be accommodated in the insulating base or the lid to which the foreign matter does not adhere, and the semiconductor element can be normally operated.
【０００８】[0008]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 は本発明の半導体素子収納用パッケージの一実
施例を示し、1 は絶縁基体、2 は蓋体である。この絶縁
基体1 と蓋体2 とで半導体素子3 を収容するための容器
4 が構成される。BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a lid. A container for housing the semiconductor element 3 with the insulating base 1 and the lid 2
4 is configured.
【０００９】前記絶縁基体1 は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体等の電気絶縁材料から成り、その上面略
中央部に半導体素子3 を収容するための凹部1aが設けて
あり、該凹部1a底面には半導体素子3 がガラス、樹脂、
ロウ材等の接着材を介して取着固定される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, etc. A recess 1a for accommodating the semiconductor element 3 is provided on the bottom surface of the recess 1a.
It is attached and fixed via an adhesive such as brazing material.
【００１０】尚、前記絶縁基体1 は例えば酸化アルミニ
ウム質焼結体から成る場合、アルミナ(Al 2 O 3 ) 、シ
リカ(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等に
適当な有機溶剤、溶媒を添加混合してセラミック原料粉
末を調整するとともに該セラミック原料粉末を従来周知
のプレス成形法によって成形し、しかる後、前記成形体
を約1500℃の温度で焼成することによって製作される。When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an organic solvent suitable for alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), magnesia (MgO), etc. A ceramic raw material powder is prepared by adding and mixing a solvent, and the ceramic raw material powder is molded by a conventionally known press molding method. Thereafter, the molded body is fired at a temperature of about 1500 ° C.
【００１１】また前記絶縁基体1 の凹部1a内表面にはガ
ラス層5 が被着されており、該ガラス層5 によって絶縁
基体1 の凹部1a内表面の表面粗さはＲa で 0.3μm 以
下、Ｒmax で5.0 μm 以下の平滑なものとなっている。A glass layer 5 is adhered to the inner surface of the concave portion 1a of the insulating base 1, and the glass layer 5 has a surface roughness Ra of 0.3 μm or less and an Rmax of the inner surface of the concave portion 1a of the insulating base 1. And it is smoother than 5.0 μm.
【００１２】前記絶縁基体1 の凹部1a内表面はガラス層
5 によってその表面が平滑となっていることから凹部1a
内表面に塵等の異物が付着し難く、また一旦、異物が付
着したとしてもその異物は容易に洗浄除去できるため絶
縁基体1 の凹部1a内を異物のない綺麗なものとなすこと
ができ、その結果、絶縁基体1 の凹部1a内表面に付着す
る異物が離脱し、これが凹部1a内に収容する半導体素子
3 の表面に付着することはなくなる。The inner surface of the concave portion 1a of the insulating substrate 1 is made of a glass layer.
The concave surface 1a
Foreign matter such as dust hardly adheres to the inner surface, and even once the foreign matter adheres, the foreign matter can be easily cleaned and removed, so that the inside of the concave portion 1a of the insulating base 1 can be made clean without foreign matter, As a result, foreign substances adhering to the inner surface of the concave portion 1a of the insulating base 1 are separated, and this is the semiconductor element accommodated in the concave portion 1a.
It will not adhere to the surface of 3.
【００１３】尚、前記ガラス層5 は絶縁基体1 が酸化ア
ルミニウム質焼結体から成る場合、酸化鉛40.0乃至60.0
重量％、酸化ホウ素3.0 乃至13.0重量％、酸化珪素0.5
乃至3.0 重量％、酸化アルミニウム0.5 乃至3.0 重量％
にフィラーとしてのチタン酸鉛系化合物を10.0乃至30.0
重量％、ジルコニアンシリケート系化合物を5.0 乃至1
5.0重量％含有させたガラスが好適に使用され、該ガラ
スはその熱膨張係数が6.0 〜7.5 ×10-6/ ℃程度で絶縁
基体1 を構成する酸化アルミニウム質焼結体の熱膨張係
数(6.5〜7.5 ×10-6/ ℃) と近似することから絶縁基体
1 の凹部1a内表面に被着させた後、絶縁基体1 とガラス
層5 に熱が印加されても両者間に大きな熱応力が発生す
ることはなく、ガラス層5 を絶縁基体1 の凹部1a内表面
に強固に被着させておくことができる。When the insulating substrate 1 is made of an aluminum oxide sintered body, the glass layer 5 has a lead oxide content of 40.0 to 60.0%.
Wt%, boron oxide 3.0 to 13.0 wt%, silicon oxide 0.5
To 3.0% by weight, aluminum oxide 0.5 to 3.0% by weight
A lead titanate compound as a filler is 10.0 to 30.0
Weight%, zirconian silicate compound 5.0 to 1
A glass containing 5.0% by weight is preferably used. The glass has a coefficient of thermal expansion of about 6.0 to 7.5 × 10 −6 / ° C. and a coefficient of thermal expansion (6.5%) of the aluminum oxide sintered body constituting the insulating substrate 1. ~ 7.5 × 10 -6 / ℃)
After the heat is applied to the insulating substrate 1 and the glass layer 5 after application to the inner surface of the concave portion 1a, no large thermal stress occurs between them, and the glass layer 5 is attached to the concave portion 1a of the insulating substrate 1. It can be firmly adhered to the inner surface.
【００１４】また前記ガラスは軟化溶融温度が450 ℃と
高いことから、後述する絶縁基体1と蓋体2 とを封止用
のガラス層を介して接合させる際、封止用のガラス層を
軟化溶融させる熱が印加されたとしても軟化溶融するこ
とは一切なく、絶縁基体1 の凹部1a内表面に強固に被着
する。Further, since the glass has a high softening and melting temperature of 450 ° C., when the insulating substrate 1 and the lid 2 to be described later are joined via the glass layer for sealing, the glass layer for sealing is softened. Even if the heat for melting is applied, it does not soften and melt at all, and firmly adheres to the inner surface of the concave portion 1a of the insulating base 1.
【００１５】更に前記ガラス層5 はその内部に粒径20.0
μm 以下の銀等から成る金属粉末を50.0〜80.0重量％含
有させておくとガラス層5 が導電性となって磁気を遮断
することができる。従って、絶縁基体1 の凹部1a底面に
取着する半導体素子3 が外部磁気の影響を受けやすい場
合にはガラス層5 に粒径が20.0μm 以下の金属粉末を5
0.0〜80.0重量％含有させて導電性としておけば、該ガ
ラス層5 が外部から入り込もうとする磁気を遮断し、こ
れによって半導体素子3 を常に正常に作動させることが
可能となる。Further, the glass layer 5 has a particle size of 20.0
When 50.0 to 80.0% by weight of a metal powder composed of silver or the like having a size of μm or less is contained, the glass layer 5 becomes conductive and can cut off magnetism. Therefore, when the semiconductor element 3 attached to the bottom surface of the concave portion 1a of the insulating base 1 is easily affected by external magnetism, a metal powder having a particle size of 20.0 μm or less is added to the glass layer 5.
If the glass layer 5 is made conductive by containing 0.0 to 80.0% by weight, the glass layer 5 blocks the magnetism that tends to enter from the outside, so that the semiconductor element 3 can always operate normally.
【００１６】前記絶縁基体1 はまたその上面に金属材料
から成る外部リード端子6 が封止用のガラス層7 を介し
て仮止めされており、該外部リード端子6 は内部に収容
する半導体素子3 を外部電気回路に接続する作用を為
し、その一端には半導体素子3の各電極がボンディング
イヤ8 を介して接続され、また他端は外部電気回路に半
田等のロウ材を介して接続される。On the upper surface of the insulating substrate 1, an external lead terminal 6 made of a metal material is temporarily fixed via a glass layer 7 for sealing, and the external lead terminal 6 is a semiconductor element 3 housed inside. Is connected to an external electric circuit, one end of which is connected to each electrode of the semiconductor element 3 via a bonding ear 8, and the other end is connected to the external electric circuit via a brazing material such as solder. You.
【００１７】前記外部リード端子6 はコバール金属(Fe-
Ni-Co 合金) や42アロイ(Fe-Ni合金) 等の金属材料から
成り、該コバール金属等のインゴット( 塊) を従来周知
の圧延加工法や打ち抜き加工法等を採用することによっ
て所定の板状に形成される。The external lead terminal 6 is made of Kovar metal (Fe-
Ni-Co alloys) and 42 alloys (Fe-Ni alloys), etc., and the ingot (lumps) of the Kovar metal or the like is formed into a predetermined plate by employing a conventionally known rolling method or punching method. It is formed in a shape.
【００１８】尚、前記外部リード端子6 はその表面にニ
ッケル、金等から成る良導電性で、且つ耐蝕性に優れた
金属をメッキ法により1.0 乃至20.0μm の厚みに層着さ
せておくと、外部リード端子6 の酸化腐食を有効に防止
するとともに外部リード端子6 とボンディングワイヤ8
及び外部電気回路との電気的接続を良好となすことがで
きる。従って、前記外部リード端子6 はその表面にニッ
ケル、金等をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくことが好ましい。The external lead terminal 6 is preferably formed by plating a metal having good conductivity and excellent corrosion resistance made of nickel, gold or the like to a thickness of 1.0 to 20.0 μm by plating. It effectively prevents oxidative corrosion of the external lead terminals 6 and the external lead terminals 6 and bonding wires 8
In addition, good electrical connection with an external electric circuit can be achieved. Therefore, it is preferable that nickel, gold or the like be layered on the surface of the external lead terminal 6 to a thickness of 1.0 to 20.0 μm by plating.
【００１９】また前記外部リード端子6 が仮止めされた
絶縁基体1 の上面には蓋体2 が該蓋体2 の下面に被着さ
せた封止用のガラス層9 と絶縁基体1 の上面に被着させ
たガラス層7 とを溶融一体化させることによって接合さ
れ、これによって絶縁基体1と蓋体2 とから成る容器4
内部に半導体素子3 が気密に封止される。A lid 2 is provided on the upper surface of the insulating substrate 1 to which the external lead terminals 6 are temporarily fixed, and a sealing glass layer 9 attached to the lower surface of the lid 2 and an upper surface of the insulating substrate 1. The applied glass layer 7 is joined by melting and integrating, thereby forming a container 4 comprising an insulating base 1 and a lid 2.
The semiconductor element 3 is hermetically sealed inside.
【００２０】前記蓋体2 は酸化アルミニウム質焼結体、
ムライト質焼結体、窒化アルミニウム質焼結体、炭化珪
素質焼結体等の電気絶縁材料から成り、例えば酸化アル
ミニウム質焼結体から成る場合には絶縁基体1 と同様の
方法、即ち、アルミナ、シリカ、カルシア、マグネシア
等に適当な有機溶剤、溶媒を添加混合してセラミック原
料粉末を調整するとともに該セラミック原料粉末を従来
周知のプレス成形法によって成形し、しかる後、これを
約1500℃の温度で焼成することによって製作される。The lid 2 is made of an aluminum oxide sintered body,
It is made of an electrically insulating material such as a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. , Silica, calcia, magnesia, etc., an appropriate organic solvent, a solvent is added and mixed to adjust the ceramic raw material powder, and the ceramic raw material powder is molded by a conventionally known press molding method, and thereafter, this is heated to about 1500 ° C. It is manufactured by firing at a temperature.
【００２１】また前記絶縁基体1 の上面に被着させた封
止用のガラス層7 及び蓋体2 の下面に被着させたガラス
層9 はそれぞれ絶縁基体1 及び蓋体2 が酸化アルミニウ
ム質焼結体から成る場合には酸化鉛50.0乃至60.0重量
％、酸化珪素1.0 乃至5.0 重量％、酸化ホウ素3.0 乃至
13.0重量％、酸化ビスマス3.0 乃至13.0重量％に、フィ
ラーとしてのコージライトを10.0乃至20.0重量％、チタ
ン酸錫系化合物を10.0乃至20.0重量％含有させたガラス
が好適に使用され、両ガラス層7 、9 を加熱溶融させ一
体化させることによって絶縁基体1 と蓋体2 とから成る
容器4 内部に半導体素子3 が気密に封止される。The sealing glass layer 7 adhered to the upper surface of the insulating substrate 1 and the glass layer 9 adhered to the lower surface of the lid 2 are made of an aluminum oxide-based material. In the case of a sintered body, 50.0 to 60.0% by weight of lead oxide, 1.0 to 5.0% by weight of silicon oxide, and 3.0 to 5.0% by weight of boron oxide
Glass containing 13.0% by weight, 3.0 to 13.0% by weight of bismuth oxide, 10.0 to 20.0% by weight of cordierite as a filler, and 10.0 to 20.0% by weight of a tin titanate compound is preferably used. , 9 are heated and melted and integrated, whereby the semiconductor element 3 is hermetically sealed inside the container 4 including the insulating base 1 and the lid 2.
【００２２】前記封止用のガラス層7 、9 はその軟化溶
融温度が約400 ℃と低く、そのため封止用ガラス層7 、
9 を溶融一体化させて絶縁基体1 と蓋体2 とから成る容
器4内部に半導体素子3 を気密に封止する際、半導体素
子3 に封止用ガラス層7 、9を溶融させるための熱が印
加されたとしても半導体素子3 に熱破壊や特性に熱変化
を生じさせることはなく、内部に収容する半導体素子3
を正常、且つ安定に作動させることが可能となる。The sealing glass layers 7 and 9 have a low softening and melting temperature of about 400 ° C., so that the sealing glass layers 7 and 9
When the semiconductor element 3 is hermetically sealed inside the container 4 composed of the insulating base 1 and the lid 2 by melting and integrating the semiconductor glass 9, heat for melting the sealing glass layers 7 and 9 in the semiconductor element 3 is obtained. The semiconductor element 3 does not cause thermal destruction or change in characteristics even if the semiconductor element 3 is applied.
Can be operated normally and stably.
【００２３】前記封止用のガラス層7 、9 はまたその熱
膨張係数が7.1 ×10-6/ ℃であり、絶縁基体1 及び蓋体
2 を構成する酸化アルミニウム質焼結体の熱膨張係数
(6.5〜7.5 ×10-6/ ℃) と近似することから、絶縁基体
1 と蓋体2 とを封止用のガラス層7 、9 を溶融一体化さ
せ、絶縁基体1 と蓋体2 とから成る容器4 内部に半導体
素子3 を気密に封止する際、絶縁基体1 と蓋体2 と封止
用のガラス層7 、9 との接合を極めて強固として容器4
内部に半導体素子3 を完全に気密封止することが可能と
なる。The sealing glass layers 7 and 9 also have a coefficient of thermal expansion of 7.1 × 10 −6 / ° C., and include an insulating substrate 1 and a lid.
Coefficient of thermal expansion of aluminum oxide sintered body composing 2
(6.5 to 7.5 × 10 -6 / ℃)
When the semiconductor element 3 is hermetically sealed inside a container 4 composed of the insulating base 1 and the lid 2 by melting and integrating the sealing glass layers 7 And the lid 2 and the sealing glass layers 7 and 9
The semiconductor element 3 can be completely hermetically sealed inside.
【００２４】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹部1a底面に半導体素子3 を
取着固定するとともに該半導体素子3 の各電極をボンデ
ィングワイヤ8 により外部リード端子6 に接続させ、し
かる後、絶縁基体1 と蓋体2とをその各々の相対向する
主面に被着させておいた封止用ガラス層7 、9 を加熱溶
融させ、接合することによって絶縁基体1 と蓋体2 とか
ら成る容器4 内部に半導体素子3 を気密に封止し、これ
によって製品としての半導体装置が完成する。Thus, according to the semiconductor device housing package of the present invention, the semiconductor device 3 is attached and fixed to the bottom surface of the concave portion 1a of the insulating base 1, and each electrode of the semiconductor device 3 is connected to the external lead terminal 6 by the bonding wire 8. Thereafter, the sealing glass layers 7, 9 in which the insulating substrate 1 and the lid 2 are adhered to the opposing main surfaces of the insulating substrate 1 and the lid 2, respectively, are heated and melted, and are joined to each other. The semiconductor element 3 is hermetically sealed inside the container 4 including the lid 2, thereby completing a semiconductor device as a product.
【００２５】尚、本発明は上述の実施例に限定さるもの
ではなく、本発明の要旨を逸脱しない範囲であれば種々
の変更は可能であり、例えば上述の実施例では絶縁基体
1 の凹部1a内表面にガラス層5 を被着し、絶縁基体1 に
異物が付着するのを有効に防止したが、蓋体2 の半導体
素子3 を収容する空所に対接する下面にガラス層5 を被
着させておけば、蓋体2 に異物が付着するのを有効に防
止し、該蓋体2 に付着する異物が半導体素子3 に付着す
るのを有効に防止できる。またガラス層5 を絶縁基体1
及び蓋体2 の両方に被着させておけば絶縁基体1 及び蓋
体2 の両方に異物が付着するのを有効に防止でき、これ
によって半導体素子への異物の付着をより少ないものと
なすことができる。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
1, a glass layer 5 is applied to the inner surface of the concave portion 1a to effectively prevent foreign substances from adhering to the insulating base 1.However, the glass layer 5 is provided on the lower surface of the lid 2 which faces the space for accommodating the semiconductor element 3. If 5 is adhered, it is possible to effectively prevent foreign substances from adhering to the lid 2 and effectively prevent foreign substances adhering to the lid 2 from adhering to the semiconductor element 3. Further, the glass layer 5 is
If the cover is attached to both the cover 2 and the cover 2, foreign matter can be effectively prevented from adhering to both the insulating base 1 and the cover 2, thereby reducing the attachment of the foreign matter to the semiconductor element. Can be.
【００２６】更に前記実施例では封止用ガラスを使用し
て絶縁基体1 と蓋体2 を接合させるガラス封止型の半導
体素子収納用パッケージで説明したが、複数枚のセラミ
ックグリーンシート( セラミック生シート) を積層し、
焼結一体化させて製作されるマルチレイヤー型の半導体
素子収納用パッケージにも適用可能である。Further, in the above-described embodiment, the glass sealing type semiconductor element storage package in which the insulating base 1 and the lid 2 are joined using the sealing glass has been described, but a plurality of ceramic green sheets (ceramic green sheets) are used. Sheets)
The present invention is also applicable to a multi-layer type semiconductor element storage package manufactured by sintering and integration.
【００２７】[0027]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子を収容するための容器を構成する酸
化アルミニウム質焼結体で形成された絶縁基体や蓋体の
半導体素子を収容する空所に対接する面に、酸化鉛40.0
乃至60.0重量％、酸化ホウ素3.0 乃至13.0重量％、酸化
珪素0.5 乃至3.0 重量％、酸化アルミニウム0.5 乃至3.
0 重量％にフィラーとしてのチタン酸鉛系化合物を10.0
乃至30.0重量％、ジルコニアンシリケート系化合物を5.
0 乃至15.0重量％含有させたガラスと、粒径が20.0μｍ
以下の金属粉末とから成り、かつガラスの量が20.0乃至
50.0重量％、金属粉末の量が50.0乃至80.0重量％である
ガラス層を被着させたことから、絶縁基体や蓋体の表面
粗さはＲａで0.3 μｍ以下、Ｒmax で5.0 μｍ以下の平
滑なものとなり、その結果、絶縁基体や蓋体には異物が
付着し難く、また付着した異物も容易、且つ完全に洗浄
除去することができて、異物の付着していない絶縁基体
や蓋体で半導体素子を収容し、半導体素子を正常に作動
させることが可能となる。According to the package for housing a semiconductor element of the present invention, an empty space for housing a semiconductor element of an insulating base or a lid made of an aluminum oxide sintered body constituting a container for housing a semiconductor element. Lead oxide 40.0
To 30.0% by weight, boron oxide of 3.0 to 13.0% by weight, silicon oxide of 0.5 to 3.0% by weight, aluminum oxide of 0.5 to 3.
0% by weight of a lead titanate-based compound as a filler
To 30.0% by weight of the zirconian silicate compound in 5.
Glass containing 0 to 15.0% by weight and a particle size of 20.0 μm
The following metal powder, and the amount of glass is from 20.0 to
Since a glass layer with 50.0% by weight and a metal powder amount of 50.0 to 80.0% by weight was applied, the surface roughness of the insulating substrate and the lid was 0.3 μm or less in Ra and 5.0 μm or less in Rmax. As a result, foreign matter hardly adheres to the insulating base and the lid, and the attached foreign matter can be easily and completely removed by washing. The element can be accommodated, and the semiconductor element can be operated normally.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
【図２】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 2 is a cross-sectional view of a conventional semiconductor element storage package.
１・・・・・絶縁基体 ２・・・・・蓋体 ３・・・・・半導体素子 ４・・・・・容器 ５・・・・・ガラス層 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Glass layer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/18 H01L 23/08 H01L 23/02 H01L 23/10 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/18 H01L 23/08 H01L 23/02 H01L 23/10
Claims (1)
縁基体と蓋体とから成り、内部に半導体素子を収容する
ための空所を有する半導体素子収納用パッケージであっ
て、前記絶縁基体及び蓋体のうち少なくとも一方の半導
体素子を収容する空所に対接する面に、酸化鉛40.0乃至
60.0重量％、酸化ホウ素3.0 乃至13.0重量％、酸化珪素
0.5 乃至3.0 重量％、酸化アルミニウム0.5 乃至3.0 重
量％にフィラーとしてのチタン酸鉛系化合物を10.0乃至
30.0重量％、ジルコニアンシリケート系化合物を5.0 乃
至15.0重量％含有させたガラスと、粒径が20.0μｍ以下
の金属粉末とから成るガラス層が被着されており、かつ
前記ガラスの量が20.0乃至50.0重量％、金属粉末の量が
50.0乃至80.0重量％であることを特徴とする半導体素子
収納用パッケージ。1. A semiconductor element housing package comprising an insulating base formed of an aluminum oxide sintered body and a lid, and having a space for housing a semiconductor element therein, wherein the insulating base and the cover are provided. On the surface of at least one of the lids, which is in contact with the space for accommodating the semiconductor element, lead oxide 40.0 to
60.0 wt%, boron oxide 3.0 to 13.0 wt%, silicon oxide
0.5 to 3.0% by weight, aluminum oxide 0.5 to 3.0% by weight, and a lead titanate-based compound as a filler 10.0 to 3.0% by weight.
A glass layer comprising 30.0% by weight, a glass containing 5.0 to 15.0% by weight of a zirconian silicate compound, and a metal powder having a particle size of 20.0 μm or less is applied, and the amount of the glass is 20.0 to 50.0% by weight, the amount of metal powder
A semiconductor device storage package characterized by being 50.0 to 80.0% by weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4186980A JP2997367B2 (en) | 1992-07-14 | 1992-07-14 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4186980A JP2997367B2 (en) | 1992-07-14 | 1992-07-14 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637208A JPH0637208A (en) | 1994-02-10 |
| JP2997367B2 true JP2997367B2 (en) | 2000-01-11 |
Family
ID=16198098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4186980A Expired - Fee Related JP2997367B2 (en) | 1992-07-14 | 1992-07-14 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2997367B2 (en) |
-
1992
- 1992-07-14 JP JP4186980A patent/JP2997367B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0637208A (en) | 1994-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2997367B2 (en) | Package for storing semiconductor elements | |
| JP2962939B2 (en) | Package for storing semiconductor elements | |
| JP2931481B2 (en) | Package for storing semiconductor elements | |
| JP3318449B2 (en) | Package for storing semiconductor elements | |
| JP2750237B2 (en) | Electronic component storage package | |
| JP2842716B2 (en) | Package for storing semiconductor elements | |
| JP3292609B2 (en) | Package for storing semiconductor elements | |
| JP2922719B2 (en) | Package for storing semiconductor elements | |
| JP4514355B2 (en) | Electronic component storage container | |
| JPH0629330A (en) | Semiconductor device | |
| JP3971712B2 (en) | Electronic component storage container | |
| JP2545402Y2 (en) | Package for storing semiconductor elements | |
| JP2545401Y2 (en) | Package for storing semiconductor elements | |
| JP2873130B2 (en) | Package for storing semiconductor elements | |
| JP2545400Y2 (en) | Package for storing semiconductor elements | |
| JP2922718B2 (en) | Package for storing semiconductor elements | |
| JP2555178Y2 (en) | Package for storing semiconductor elements | |
| JP2750256B2 (en) | Package for storing semiconductor elements | |
| JP4325896B2 (en) | Semiconductor element storage package and semiconductor device using the same | |
| JP2548964Y2 (en) | Package for storing semiconductor elements | |
| JPH0645374A (en) | Package for containing semiconductor element | |
| JPH05326738A (en) | Package for semiconductor element | |
| JP2552554Y2 (en) | Package for storing semiconductor elements | |
| JPH05121581A (en) | Semiconductor device housing package | |
| JPH11233661A (en) | Package for electronic component accommodation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071029 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081029 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |