JPH0644772A - Memory circuit and system for refreshing it - Google Patents

Abstract

PURPOSE:To disperse current consumption and to reduce a noise by dividing plural D-RAMs in a memory circuit to plural blocks and refreshing them at every block in different timing from each other. CONSTITUTION:Plural D-RAMs in the memory circuit are divided to a first to a fourth D-RAM blocks 11-14. Then, signal lines 22-24 are provided at every blocks 11-14, and the blocks 11-14 are refreshed by a common refresh circuit in different timing from each other. By such a constitution, since current consumption at a refresh time is dispersed, the noise occurring from power source is reduced, and influence to other equipment is reduced as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit using a plurality of D-RAMs, and particularly to prevent a decrease in power supply voltage,
The present invention relates to a memory circuit capable of suppressing noise generated from a power supply and a refresh method thereof.

[0002]

2. Description of the Related Art First, a D-RA used in a memory circuit.
M stores information depending on the presence / absence of electric charge stored in the capacitor, but the electric charge stored in this capacitor is discharged with time. Therefore, it is necessary to periodically refresh (rewrite) the content of the data in order to retain the memory content by utilizing the time other than the original write / read operation as the memory.

Next, a memory circuit using a plurality of conventional D-RAMs and its refresh method will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic configuration diagram of a conventional memory circuit, and FIG. 4 is a timing chart of a conventional refresh operation.

Since the configuration of the memory circuit is premised on configuring a large capacity memory system using the D-RAM, a plurality of D-RAMs are used in the memory circuit. Then, in each D-RAM, a signal line necessary for performing the refresh operation, for example, an address line and a data line is provided.
Data lines, control lines, etc. are connected to each other, and when these signal lines are used in a plurality of D-RAMs, a common signal line is connected to each D-RAM. In FIG. 3, the address line, the data line, the control line and the like are collectively represented by one signal line 5.

In the refresh operation of the D-RAMs 1 to 4 in the memory circuit shown in FIG. 3, all the D-RAMs are periodically refreshed with the same timing signal as shown in FIG. In FIG. 4, the horizontal direction represents time, the upper signal waveform is the refresh timing signal given to the signal line 5, and the lower signal waveform is the consumed current generated by the refresh. That is, the refresh is performed every fixed time T (cycle T).

[0006]

However, in the above-described conventional refresh circuit having a plurality of D-RAMs and its refresh method, a plurality of D-RAMs are refreshed at the same time, so that the current consumption during refreshing is reduced. There is a problem that the voltage of the power supply line drops suddenly, and the drop of the power supply line causes noise, which causes abnormal operation of other ICs or radio noise in the air.

Therefore, in order to suppress the noise, a countermeasure such as inserting a bypass capacitor between the power supply and the ground of the board may be considered, but there is a problem that the number of parts as a whole circuit increases and the cost increases. there were.

The present invention has been made in view of the above circumstances, and requires a large number of parts and expensive parts by dividing a plurality of D-RAMs into some blocks and performing refresh at different timings. It is an object of the present invention to provide a refresh circuit and its refresh method that can suppress noise and the like without doing so.

[0009]

The invention according to claim 1 for solving the above-mentioned problems of the prior art is a plurality of D-RAMs.
In the memory circuit having, the plurality of D-RAMs are divided into a plurality of blocks, and a signal line for performing refresh control is connected to each of the blocks.

According to a second aspect of the present invention for solving the problem of the conventional example, in a refresh method of a memory circuit, a plurality of D-RAMs in the memory circuit are refreshed at different timings for each block. It has a feature.

[0011]

According to the invention of claim 1, a plurality of D-RAs are provided.
Since M is divided into several blocks and used as a memory circuit for connecting a signal line for refresh control to each block, if refreshing is performed at different timings, the current consumption of the D-RAM at the time of refreshing is dispersed. However, the noise generated from the power supply can be reduced, the number of parts for absorbing noise can be reduced, the cost can be reduced, and the influence on other devices can be reduced.

According to the second aspect of the present invention, since the plurality of D-RAMs in the memory circuit are refreshed in the memory circuit for refreshing at different timings for each block, the current consumption of the D-RAM at the time of refreshing. It is possible to reduce the noise generated from the power supply by reducing the number of parts for absorbing noise, reduce the cost, and reduce the influence on other devices.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of a memory circuit according to an embodiment of the present invention.

The memory circuit of this embodiment has a plurality of D-RAs.
M is divided into a plurality of blocks (four first to fourth D-RAM blocks 11 to 14 in the example of FIG. 1), and signal lines 21 to 2 such as independent address lines, data lines and control lines are provided.
4 is connected.

In this embodiment shown in FIG. 1, address lines and data are
The data lines, the control lines and the like are represented by one signal line, and the signal lines 21 to 24 are provided corresponding to the D-RAM blocks 12 to 14 divided into four blocks, and the D-R is formed by the address lines.
The data is refreshed (written) by designating the address of AM and using the data line and the control line.

Here, as a reference for dividing a plurality of D-RAMs into blocks, a plurality of D-RAMs included in one block are used.
When the RAM is refreshed at the same time with the refresh timing signal, to the extent that the power supply line drop described in the problems of the prior art does not generate noise, that is,
The number of D-RAMs included in one block is specified so that the current consumption during refreshing does not increase sharply even if a plurality of D-RAMs in one block are simultaneously refreshed.

Next, D- in the memory circuit of this embodiment
The RAM refresh timing will be described with reference to FIG. FIG. 2 is a timing chart of the refresh operation of this embodiment. In FIG. 2, the upper signal waveform represents the refresh timing signals a to d given to the signal lines 21 to 24, and the lower signal waveform represents the current consumption.

D-R of the first block in the memory circuit
The AM block 11 is refreshed from the signal line 21 at the timing of the pulse a of the refresh timing signal a shown in FIG. Then, from the pulse a, the time t
After the delay, the pulse b of the refresh timing signal b passes through the signal line 22 and the D-RAM block 12 of the second block.
In the same manner, the D-RAM block 13 of the third block also receives the time t from the pulse b via the signal line 23.
The pulse c of the refresh timing signal c is delayed, and the pulse d of the refresh timing signal d is also applied to the D-RAM block 14 of the fourth block via the signal line 24 later than the pulse c by time t. .

The pulse of the refresh timing signal given from each signal line is given to each D-RAM block at the cycle T, and the memory circuit is refreshed at the cycle T. The relationship between the period T and the pulse delay time t between the signal lines is T = 4t,
The peak of the current consumption in the entire memory circuit occurs every time t.

Therefore, compared with the signal waveform of the current consumption in the conventional refresh operation shown in FIG. 4, in the refresh operation of the present embodiment shown in FIG. 2, the number of refresh times is increased to disperse the peak of the current consumption and the current peak. The value can be lowered.

According to the memory circuit in which the plurality of D-RAMs of this embodiment are divided into a plurality of blocks and the refresh method thereof, the refresh operation can be dispersed by delaying the refresh timing for each block by time t. Therefore, it is possible to reduce the peak value of the consumption current and prevent the power supply voltage from being lowered due to the capacity overage of the power supply. Therefore, it is possible to suppress the noise generated from the power supply and the radio noise to the air.

Further, as described above, since the generation of noise is reduced, it is possible to reduce the number of parts such as a bypass capacitor for absorbing noise, which is effective in reducing the cost, and the radio noise is also reduced. Since the amount is small, the effect on other devices can be reduced. Furthermore, if the influence on other devices is reduced, it becomes possible to comply with the radio emission standards, VCCi, FCC and the like.

[0023]

According to the invention described in claim 1, a plurality of D's are provided.
-Since the RAM is divided into several blocks and used as a memory circuit for connecting a signal line for refresh control to each of them, if refreshing is performed at different timings, the current consumption of the D-RAM at the time of refreshing The effects of being able to reduce the noise generated from the power supply by reducing the number of parts for absorbing noise, reduce the cost, and reduce the influence on other devices.

According to the second aspect of the present invention, since the plurality of D-RAMs in the memory circuit are refreshed in the memory circuit for refreshing at different timings for each block, the consumption of the D-RAM at the time of refreshing. There is an effect that the current is dispersed, the noise generated from the power source is reduced, the number of parts for absorbing noise is reduced, the cost is reduced, and the influence on other devices can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a memory circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the refresh operation of the memory circuit of this embodiment.

FIG. 3 is a schematic diagram of the configuration of a conventional memory circuit.

FIG. 4 is a timing chart of a refresh operation of a conventional memory circuit.

[Explanation of symbols]

1, 2, 3, 4 ... D-RAM, 5 ... Signal line, 11,
12, 13, 14 ... D-RAM block, 21,
2, 23, 24 ... Signal line

Claims (2)

[Claims] 1. A memory circuit having a plurality of D-RAMs, wherein the plurality of D-RAMs are divided into a plurality of blocks, and a signal line for refresh control is connected to each of the blocks. . 2. A refresh method for a memory circuit, wherein a plurality of D-RAMs in the memory circuit are refreshed at different timings for each block.