JPH08106782A - Dynamic ram refreshing control circuit - Google Patents

Abstract

PURPOSE: To prevent the lowering of a processing speed of a microprocessor by performing a refreshing while shifting the timing for every group in the refreshing dynamic RAMs. CONSTITUTION: A control circuit comprising delay circuits 9 and 10 and logical circuits 7 and 8 is added to a DRAM controller 2 to control the reading/writing and refreshing operation of DRAMs 4-6 by an instruction from an MPU 1. The DRAMs 4-to are refreshed in order of from the DRAM 4 to the DRAM 6 continuously in sequence by setting a column address strobe signal (RAS1) signal 12 to '0' at time t12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM refresh control circuit for dividing a dynamic RAM in an electronic control unit into a plurality of groups and sequentially refreshing each group.

[0002]

2. Description of the Related Art A dynamic RAM (hereinafter, abbreviated as DRAM) holds stored data, so that it is necessary to perform a refresh operation within a predetermined fixed period. However, when a large number of DRAMs are used, if all the DRAMs are refreshed at the same time, the current consumption will momentarily increase and the power supply voltage and the ground level supplied to the circuit will become unstable, causing malfunctions. . Therefore, in the conventional technique, all the DRAMs are not refreshed at the same time, but the DRAMs are divided into a plurality of groups and refreshed for each group.

FIG. 5 is a block diagram showing the structure of a general electronic control unit using a large number of DRAMs.
3 is a time chart of a refresh operation according to a conventional technique. In FIG. 5, the electronic control unit includes a microprocessor (hereinafter, microprocessor is abbreviated as MPU) 1 that controls the entire electronic device, and a DRAM (4 in the illustrated example) divided into groups (4). ~ 6),
DRAM controller 2 for controlling these DRAMs
And these MPU1 and DRAM (4-6) and DRAM
The internal bus 3 is connected to the controller 2 by a bus.

FIG. 6 shows the timing relationship of a refresh operation according to the prior art, in which the horizontal axis represents the time axis and the vertical axis represents the access mode to the DRAM (4 to 6).
The lower part of the vertical axis shows an enlarged view of the refresh period (R4 to R6) when refreshing the DRAM (4 to 6), and D
The relationship between the refresh timings of the RAMs (4 to 6) will be described. In FIG. 6, the upper part of the vertical axis divides one refresh cycle (t41 to t71) into the number of groups obtained by dividing the DRAM (4 to 6) into groups, and the DRAM (4 to 6) by the MPU 1 shown in the period A. The refresh period of the DRAMs (4 to 6) divided into groups represented by R4, R5, and R6 is inserted during the access period to. In the illustrated example, the periods (t43 to t51), (t53 to t61), (t63 to
t71) corresponds to the period A and is a memory accessible period for performing the original control of the MPU 1 as the electronic control unit. Also, the period (t41 to t43) indicated by R4, R5, and R6, (t
51-t53), (t61-t63) are divided into DRs for each group
This is the refresh period of AM4, DRAM5, and DRAM6. The refresh period of the DRAMs (4 to 6) corresponds to, for example, the refresh period R4 of the DRAM 4 through the refresh periods R5 and R6 to the next refresh period R4,
This refresh cycle (t41 to t71) is refreshed every predetermined fixed cycle (for example, about 2 ms).

The lower part of the vertical axis of FIG. 6 is an enlarged view of the refresh operation period. For the sake of simplicity, the refresh period (t41 to t43) of the DRAM 4 indicated by R4 will be mainly described. The refresh operation of the DRAM 4 is controlled by a strobe control input terminal, a bar CAS (column addre) which will be described later.
"0" in ss strobe) and bar RAS (row address strobe)
Activated by adding input. That is, the time
At t41, the column address strobe signal CAS applied to the bar CAS pin of DRAM4 is set to "0", and at time t42, the row address strobe signal RAS applied to the bar RAS pin is set to "0".

By setting the column address strobe signal CAS to "0", the column address fetch is controlled, the column decoder, the output buffer, the data input circuit, etc. are controlled, and the row address strobe signal RAS is set to "0". By controlling the fetching of the row address,
The row decoder and sense amplifier are controlled. That is, DRA
The memory contents of M4 are set for the period (t42 to t43) by setting the memory access mode signal to refresh and setting the above-mentioned column / row address strobe signals CAS and RAS to "0".
The DRAM 4 can be refreshed in the meantime.

Similarly, DRAMs 5 and 6 designated by R5 and R6
Refreshing the column / row address strobe signal CAS
, RAS to "0", the DRAM 5 can be refreshed during the period (t52 to t53) and the DRAM 6 can be refreshed during the period (t62 to t63).

[0008]

In the above-mentioned prior art,
DR for simultaneously performing refresh operations in multiple DRAMs
When the AM group is divided into a plurality of groups, the refresh period that should be executed within one predetermined refresh cycle is multiplied by the number obtained by dividing the DRAM into a plurality of groups. An increase in the refresh period occupied in one refresh cycle results in a decrease in the time during which the MPU can perform a normal access operation as an electronic control device, and there is a drawback that the processing speed of the MPU is reduced.

The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems and to provide a DRA.
Even if the number of divisions of M into a plurality of groups increases, a dynamic RAM refresh that must be performed within one refresh cycle and that minimizes the increase in the refresh period of all DRAMs and prevents the processing speed of the MPU from decreasing. It is to provide a control circuit.

[0010]

In order to achieve the above object, in the present invention, a microprocessor, a plurality of dynamic RAMs, and a read / write operation and a refresh operation of the dynamic RAM are controlled based on an instruction from the microprocessor. In the dynamic RAM refresh control circuit of an electronic control device, the electronic control device includes a dynamic RAM divided into a plurality of groups, and the DRAM controller refreshes the dynamic RAM divided into a plurality of groups. At this time, each dynamic RAM of each group is provided with a delay circuit including a delay circuit and a logic circuit for sequentially shifting the timing at which the row address strobe signal becomes active.

Further, the DRA divided into a plurality of groups
When refreshing M, notify the DRAM controller of the refresh operation by the access mode signal, and
It is assumed that the column address strobe signal of AM is activated, the row address strobe signal is activated, and the row address strobe signal is activated, so that the DRAM is sequentially refreshed by the delay means.

[0012]

With the above-mentioned configuration means, the DRAM controller, when refreshing the DRAM divided into a plurality of groups, sequentially delays the timing at which the row address strobe signal input to the DRAM becomes active for each group and a logic circuit. By providing the delay means including a circuit, refresh control of all DRAMs can be performed in the following procedure.

First, the DRA divided into a plurality of groups
When refreshing M, notify the DRAM controller of the refresh operation by the access mode signal, and
The column address strobe signal of AM is activated.
Next, the row address strobe signal is activated.
By activating this row address strobe signal, the first DRAM is refreshed, then, after the elapse of the time for refreshing the first DRAM by the delay means, the next DRAM is refreshed, and then all the DRAMs are sequentially refreshed. can do.

[0014]

1 is a block circuit diagram of a delay means added to a DRAM controller according to an embodiment of the present invention, FIG.
Is a truth value correspondence diagram of a logic circuit used in the delay means of FIG. 1, FIG. 3 is a timing chart at the time of refresh operation according to the embodiment, FIG. 4 is a time chart during one refresh cycle, and FIGS. The same functional members corresponding to are given the same reference numerals.

The embodiment shown in FIG. 1 is a DR for refreshing DRAMs (4 to 6) divided into three groups.
FIG. 3 is a block circuit diagram of a delay unit added to the AM controller 2, and hereinafter, unless otherwise specified, description will be made by using three sets of group division numbers. In FIG. 1, the DRAM controller 2 that controls the read / write operation and the refresh operation of the DRAM (4 to 6) by the instruction from the MPU 1 has delay circuits 9 and 10 and the logical characteristics shown in the truth value correspondence diagram of FIG. A control circuit composed of the logic circuits 7 and 8 is added.

Further, the DRAM of this electronic control unit is
RAM4, DRAM5, DRAM6 is divided into three,
Each has a bar CAS terminal and a bar RAS terminal. D
RAM (4-6) bar CAS terminals are connected in parallel,
A column address strobe signal (CAS) signal 11 is input.
A row address strobe signal (RAS1) signal 12 is input to the bar RAS terminal of the DRAM 4, and this (RAS1) signal 12 is simultaneously input to the delay circuit 9 and the input terminals A of the logic circuits 7 and 8. The output signal of the delay circuit 9 is the input terminal B of the logic circuit 7.
And the delay circuit 10, and the output signal of the delay circuit 10 is input to the input terminal B of the logic circuit 8.

The input terminal D of the logic circuits 7 and 8 is a DRAM.
The access mode signal 13 for controlling the read / write operation or the refresh operation in the operation modes (4 to 6) is input, and the output terminal E of the logic circuit 7 outputs the (RAS2X) signal 16 of the DRAM 5 as the row address strobe signal of the DRAM 5. Bar RA
Input to S terminal. Similarly, the output terminal E of the logic circuit 8
As a row address strobe signal of the DRAM 6 (RA
The S3X) signal 17 is input to the bar RAS terminal of DRAM6.
The input terminals C of the logic circuits 7 and 8 are connected to the DRAMs 5 and 6 respectively.
Row address strobe signal (R
The AS2) signal 14 and the (RAS3) signal 15 are input to the corresponding input terminals C, respectively.

The operation of the delay means having the above structure will be described. First, a truth value correspondence diagram of the logic circuits 7 and 8 will be described with reference to FIG. In FIG. 2, in the input (A to D) columns
The output value corresponding to the value of "0" or "1" is output to the E column.
Also, the input value X is "0" at the place where the symbol X is written,
The output value is determined regardless of the value of "1", and the result is output to the E column. A DRAM is connected to the input terminals D of the logic circuits 7 and 8.
Access mode signal using (4-6) in read / write operation
When 13 is "0", the output E is the input terminal C of the logic circuits 7 and 8.
The same value that is input to is output. That is, when the access mode signal 13 is "0" and the DRAM (4 to 6) is used in the read / write operation, the row address strobe signal (RAS1) signal
12, (RAS2) signal 14, (RAS3) signal 15 directly correspond to DRA
It is input to the bar RAS terminal of M (4 to 6) and the corresponding DR
The AM is activated and necessary read / write operations are controlled.

Next, at the input terminals D of the logic circuits 7 and 8, D
When the access mode signal 13 which uses the RAM (4 to 6) in the refresh operation is "1", the output E is the logic circuit 7,
The logical sum of the eight input terminals A and B is output. That is, when the access mode signal 13 is "1", the control operation is performed regardless of the (RAS2) signal 14 and (RAS3) signal 15 input to the input terminals C of the logic circuits 7 and 8.

The refresh operation will be described with reference to FIGS. The access mode signal 13 is set to "1", and the column address strobe signal (CAS) signal 11 is set to "0" at time t11. In this state, the DRAMs (4 to 6) control fetching of column addresses, and also control column decoders, output buffers, data input circuits, and the like. The row address strobe signal (RAS1) signal 12 is set to "0" at time t12 after a predetermined time determined by the type of DRAM memory has elapsed.
The (RAS1) signal 12 accesses the DRAM 4, and the DRAM 4 immediately starts the refresh operation and completes the refresh operation by time t13. At time t12, the row address strobe signal “0” (RAS1) signal 12 is delayed by ΔT via the delay circuit 9 and the signal value “1” is input to the input terminal B of the logic circuit 7 at time t13. The change from "to" 0 "occurs.
In response to this signal change, the output terminal E of the logic circuit 7 (RAS2
X) The signal value of signal 16 changes from "1" to "0", and the DRAM
Refresh operation 5 starts. Further, after the elapse of ΔT, the output of the delay circuit 10 changes at time t14, and the signal value "1" changes to "0" at the input terminal B of the logic circuit 8. In response to this signal change, (R
AS3X) The signal value of signal 17 changes from "1" to "0", and DRA
The refresh operation of M6 starts. That is, time t12
Then, by setting the row address strobe signal (RAS1) signal 12 to "0", the DRAMs (4 to 6) are sequentially set to D
The refresh process from the RAM 4 to the DRAM 5 and the DRAM 6 is continuously executed.

FIG. 4 shows a time chart in one refresh cycle at this time. In the refresh period from time t11 to time t15 shown by R, the timing is given for each divided group DRAM (4 to 6). By shifting the row address strobe signal (RAS) signal to be active, all the DRAMs (4 to 6) are refreshed, and the remaining period (t15 to t21) can be made accessible by the MPU 1.

According to the present invention, as shown in FIG. 3, the (CAS) signal 11 is set to "0" at time t11 to activate the column address strobe signal, and then at time t12 (RAS).
1) If the signal 12 is set to "0", the row address strobe signal becomes active while sequentially shifting the timing, so the waiting period until the row address strobe signal becomes active is divided into multiple groups of DRAMs.
Even if you have, you only have to do the first time. The net time ΔT for refreshing only the number of DRAMs divided into a plurality of groups is unavoidable, but this refresh net time ΔT is usually shorter than the above-mentioned memory access time (waiting period). Therefore, it is possible to prevent the processing speed of the MPU 1 from decreasing.

In the example shown in FIG. 1, the DRAM is divided into groups, and the number of groups is three. However, when the number of divided groups is n, the number of delay circuits 9 and 10 is shown. (N-1) sets, and (n-1) sets of the number of logic circuits shown by 7 and 8 are provided, whereby the delay means of the present invention can be configured.

[0024]

As described above, according to the present invention, the dynamic RAM of the electronic control unit having a large number of dynamic RAMs is divided into a plurality of groups, and the timing of each group is shifted when the dynamic RAM is refreshed. By performing refreshing in this manner, it is necessary to prevent a momentary large consumption current from flowing in the electronic control unit and to perform the refreshing within one refresh cycle.
It is possible to minimize the increase in the refresh period of all DRAMs and prevent the decrease in the processing speed of the microprocessor.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a delay means added to a DRAM controller according to an embodiment of the present invention.

FIG. 2 is a truth value correspondence diagram of a logic circuit used in the delay means of FIG.

FIG. 3 is a timing chart during a refresh operation according to the embodiment.

FIG. 4 is a time chart during one refresh cycle.

FIG. 5 is a block diagram of a general electronic control unit using many DRAMs.

FIG. 6 is a time chart of a refresh operation according to a conventional technique.

[Explanation of symbols]

 1 MPU 2 DRAM controller 3 Internal bus 4 to 6 DRAM 7, 8 Logic circuit 9, 10 Delay circuit 11 CAS signal 12 RAS1 signal 13 Access mode signal 14 RAS2 signal 15 RAS3 signal 16 RAS2X signal 17 RAS3X signal A MPU access period R Refresh period of DRAMs 4, 5 and 6 R4 Refresh period of DRAM 4 R5 Refresh period of DRAM 5 R6 Refresh period of DRAM 6 t11 to t73 Time

Claims (2)

[Claims] 1. A dynamic RAM refresh control for an electronic control device comprising a microprocessor, a plurality of dynamic RAMs, and a DRAM controller for controlling read / write operations and refresh operations of the dynamic RAM based on instructions from the microprocessor. In the circuit, the electronic control device includes a dynamic RAM divided into a plurality of groups, and the DRAM controller refreshes the dynamic RAM divided into the plurality of groups, and a row address strobe for each dynamic RAM of each group. A dynamic RAM refresh control circuit, comprising: a delay circuit including a delay circuit that sequentially shifts the timing at which a signal becomes active and a logic circuit. 2. The dynamic RAM refresh control circuit according to claim 1, wherein when refreshing a DRAM divided into a plurality of groups, a DRAM controller is informed of a refresh operation by an access mode signal, and a column address strobe signal for all DRAMs. Is activated, then the row address strobe signal is activated, and the row address strobe signal is activated, whereby the DRAM is sequentially refreshed by the delay means, and the dynamic RAM refresh control circuit is characterized.