JPH04370597A - Refresh method of memory circuit - Google Patents

Abstract

PURPOSE:To refresh a memory circuit, which consists of plural DRAM elements, whithout making the configuration of peripheral circuits, such as a memory controlling circuit, complex and without lowering a power supply voltage during a refreshing period. CONSTITUTION:All DRAM elements are divided into plural blocks 11 to 14, each of the blocks consists of an arbitrary number (m) elements and the refreshing operation is sequentially performed for each block with a prescribed delay time between blocks so as to suppress the peak current value during the refreshing period. Furthermore, the refreshing operations of each block are performed within the same refreshing period thus, a simple configuration using delay elements 19 and 20 is realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for refreshing a memory circuit comprising a plurality of DRAM elements used in a memory circuit for storing measurement data in an X-ray CT apparatus.

0002

2. Description of the Related Art When configuring a memory circuit using DRAM elements, the current consumption is only about 2 mA per element when the DRAM element is not in operation;
Row address strobe of AM element
Strobe, hereinafter abbreviated as "RAS". ) or column address strobe (ColumnAddress Str
obe, hereinafter abbreviated as "CAS". ) When the signal rises, a current of 80 mA per element is generated at a rise of 10 mA.
~20 nsec, with a pulse width of about 50 nsec.
In a memory circuit consisting of a plurality of DRAM elements,
When changing the RAS and CAS signals, especially when performing a refresh operation specific to DRAM elements, conventionally the refresh operation is performed on all elements at once, so the DR
If the total number of AM elements is n, a large current of (n×80) mA will instantly flow. Therefore, this leads to a drop in the power supply voltage, and if this continues, a normal voltage will not be temporarily applied to the memory circuit (DRAM element), causing malfunction, and the stored contents will no longer be guaranteed.

Therefore, conventionally, for each DRAM element,
A decoupling capacitor is provided at a ratio of one decoupling capacitor, and the large current is covered by the charge stored in this capacitor. Incidentally, in recent years, X-ray CT apparatuses have come to perform continuous scans as many as 10 to 20 times. At this time, it is necessary to temporarily store the measurement data in a memory, which requires a memory board that can store 40 Mbytes or more of data.

On the other hand, with recent improvements in substrate technology, the mounting density of DRAM elements on a substrate has become higher. In other words, the number of DRAM elements that can be mounted has increased due to multi-layered boards and thinner patterns, and the adoption of zip packages for DRAM elements has increased the number of DRAM elements that can be mounted to 130 on a board about the size of an A3 sheet. It has now become possible to produce a memory substrate that can satisfy the requirements of the X-ray CT apparatus. When making a memory board based on the above specifications, due to the adoption of zip packages for DRAM elements, it has become difficult to provide individual (one-to-one) decoupling capacitors near the DRAM elements, so two decoupling capacitors are required. Currently, one decoupling capacitor is provided for each DRAM element.

Under such circumstances, if all DRAM elements are refreshed at the same time within the same refresh period, the current consumption due to refreshing cannot be sufficiently covered by the decoupling capacitor, which causes a drop in the power supply voltage. The contents of the memory circuit (DRAM element) are no longer guaranteed. So all DRA
A method is adopted in which an appropriate number of DRAM elements are grouped into one block and divided into a plurality of blocks, and the refresh operation is sequentially performed for each block with separate refresh periods, thereby reducing the number of DRAM elements that are refreshed at the same time. was.

[0006]

[Problems to be Solved by the Invention] However, in such conventional technology, the configuration of peripheral circuits for memory control becomes complicated, such as sequentially selecting DRAM elements to be refreshed during separate refresh periods, resulting in an increase in circuit scale. There was a problem in that it invited

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit refresh method that can refresh a DRAM element without complicating the configuration of peripheral circuits or causing a drop in power supply voltage. .

[0008]

[Means for solving the problem] The above purpose is to
In a refresh method for a memory circuit consisting of AM elements, all DRAM elements are grouped into one block in an appropriate number and divided into multiple blocks, and the refresh operation is performed within the same refresh period with a predetermined delay time between each block. This is achieved by giving and performing sequentially.

[0009]

[Operation] All DRAM elements are grouped into one block in an appropriate number and divided into a plurality of blocks, and the refresh operation is performed with a predetermined delay time (for example, 20 to 40 nsec) between each block.
), the number of DRAM elements that perform the refresh operation simultaneously is reduced, the peak current value during the refresh operation is reduced and dispersed, and a drop in the power supply voltage is prevented. Further, since the refresh operations described above are performed sequentially within the same refresh period of the memory circuit, the configuration of the peripheral circuits does not become complicated.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of a memory circuit configuration to which a memory circuit refresh method according to the present invention is applied. In this figure, one block has m blocks (the maximum value of m depends on the maximum capacity of the decoupling capacitor,
In the case of the X-ray CT apparatus, the number is, for example, 30 to 50. ) A memory circuit having a four-block configuration (DRAM element blocks 11 to 14) consisting of DRAM elements is illustrated.

In FIG. 1, RAS1 to RAS4 are block 1.
RAS input lines 1 to 14 are shown, and CAS1 to CAS4 are CAS input lines, respectively. These RAS1~RAS
4 and CAS1 to CAS4 are supplied with unique RAS and CAS signals for each block 11 to 14. For example, R
A RAS signal common to the m DRAM elements of the block 11 is supplied to AS1.

[0012] RAS1 to RAS4 and CAS1 to CAS
4, the RAS and CAS signals during normal operation and the RAS during refresh operation are connected by multiplexers 15 and 16.
, CAS signals are selectively supplied. R during normal operation
The AS and CAS signals are generated by memory control circuits 17 and 18 during memory read/write operations. During the refresh operation, the RAS signal starts from RAS1, and is sequentially delayed by a delay element, here the delay line 19, by a predetermined time, here 40 nsec, and then sent to RAS2 and RAS.
3, RAS4 is created. Similarly, the CAS signal starts at CAS1 and is sequentially transmitted by delay line 20 to 40
CAS2, CAS3, CAS4 with a delay of nsec,
It is created.

Reference numeral 21 denotes a memory control circuit for refresh operation, and a selection signal 22 for normal operation (memory read/write operation) and refresh operation is sent to a multiplexer 15,
16, and the memory control circuit 1 during normal operation.
The RAS and CAS signals from the memory control circuit 21 are applied to the blocks 11 to 14 during the refresh operation. A refresh operation of the memory circuit having the illustrated configuration will be described below. Here, a refresh address counter is not required, that is, the refresh address is externally DR.
CAS before, which does not need to be supplied to the AM element
e Refresh operation in RAS (CBR) mode will be explained.

FIG. 2 shows RAS and CAS signal waveforms during refresh operation in CBR mode. As shown in the figure, the CAS1 to CAS4 signals are at L level before the RAS1 to RAS4 signals are supplied. Also RAS, CA
Since the S signals are each supplied with a delay time of 40 nsec, the memory blocks 11 to 14 are each supplied with a delay time of 40 nsec.
The refresh operation is performed sequentially with a delay of c. Therefore, the current flowing during refresh is DR
Assuming 80mA per AM element, (4m x 80)
Instead of a peak current of mA flowing all at once, (m×
80) The current flows sequentially with a delay of 40 nsec while being suppressed to a peak value of mA. As a result, the peak value of the current flowing during the refresh operation is suppressed to m/n, where n is the total number of DRAM elements, the current value consumed as a whole is dispersed, and the instantaneous power supply voltage during the refresh operation is reduced. The descent will be kept low.

Furthermore, since the refresh operations described above are performed sequentially within the same refresh period, it is not necessary to complicate the configuration of peripheral circuits for memory control, such as by sequentially selecting DRAM elements to be refreshed during separate refresh periods. do not have. In the above embodiment, a delay line is used as a delay element for delaying the RAS and CAS signals during the refresh operation, but a shift register or the like may also be used.

[0016]

As explained above, according to the present invention, all DRAM elements are grouped into one block in an appropriate number and divided into a plurality of blocks, and the refresh operation is performed by giving a predetermined delay time between each block. Since the refresh operations are performed sequentially, the number of DRAM elements that perform refresh operations at the same time is reduced, the peak current value during the refresh operations is reduced and dispersed, and a drop in the power supply voltage is prevented. Furthermore, since the refresh operations described above are performed sequentially within the same refresh period, there is an advantage that the configuration of peripheral circuits is not complicated. In particular, the delay time can be provided by a delay element such as a delay line, without complicating the configuration of the memory control circuit. Note that the time difference (delay time) for performing the refresh operation is, for example, 20 to 40 ns.
c, the overall time required for the refresh operation is only slightly increased, and its influence is small.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a memory circuit configuration to which the method of the present invention is applied.

[Figure 2] RAS during refresh operation in the same circuit as above
, CAS signal waveform.

[Explanation of symbols]

11 Block (DRAM element block) 12 Block (DRAM element block) 13 Block (DR
AM element block) 14 Block (DRAM element block) RAS1 Row address (
Row address) Strobe input line RAS2 Row address (
Row address) Strobe input line RAS3 Row address (
Row address) Strobe input line RAS4 Row address (
Row address) strobe input line CAS1 Column address (column address) strobe input line CAS2 Column address (column address) strobe input line CAS3 Column address (column address) strobe input line CAS4 Column address (column address) strobe input line 15
Multiplexer 16 Multiplexer 19 Delay line 20 for CAS1 to CAS4 during refresh operation Delay line 21 for RAS1 to RAS4 during refresh operation Memory control circuit for refresh operation

Claims (1)

[Claims] 1. A method for refreshing a memory circuit consisting of a plurality of DRAM elements, in which all DRAM elements are divided into a plurality of blocks by dividing them into one block in an appropriate number, and a refresh operation is performed on each block within the same refresh period. A method for refreshing a memory circuit, characterized in that refreshing is performed sequentially with a predetermined delay time in between.