JP3224678B2 - Circuit and method for extending writing period of DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit and a method for extending a writing period of a dynamic random access memory (DRAM) for improving the timing and noise margin of the DRAM. Circuits and methods for extending the effective write period for a DRAM operating in a static column mode.

[0002]

2. Description of the Related Art Dynamic random access memories (DRAMs) belong to an operation mode of a device.
Classified into one of two groups. One group is static column mode devices and the other is fast page mode devices. While this fast page mode device is more widespread, static column mode devices are also widely used. The main difference between the two types of devices lies in the latching of address information.

The difference in latching of address information is as follows.
Each device has advantages and disadvantages. For example, the access time of a static column mode device may be slightly shorter than that of a fast page mode device, but the cycle time is generally longer. Certain control signals need to access the DRAM (ie, read data or write data). The initial control signals that need to access the DRAM include those shown in FIGS.
As shown in (d), the row address strobe / RA
S, a column address strobe / CAS (referred to as a column enable signal / CE), a write enable signal /
(Note that a forward slash preceding each signal indicates an inverted state of each signal. Generally, an inverted state of a signal requires an active-low signal as an input to a circuit.) Or when the circuit generates an active low output.)

The active low signal / RAS indicates that a valid row address has been supplied. Because both static column mode devices and fast page mode devices are "page mode" devices, additional data can be read from or written to memory without repeating certain address information. Can be. For example, the row address signal is held along with the row signal / RAS while the column address is being changed. Active low signal / C
AS indicates that an appropriate column address has been given.

The active low signal / WE indicates that a write function is performed and that data is written to the memory. These signals were established by actual use in the industry, and the specific pulse width of each signal has become a de facto measure. Active low signal / WE is shorter than active low signal / CAS, as defined by de facto standards established in the industry. For example, the pulse width of the active-low signal / CAS in a specific device (FIG. 4)
(B), t _CAS is 15 ns, but the pulse width of the active-low signal / WE (FIG. 4)
(Indicated as t _{WE in} (c)) is two-thirds of the / CAS pulse width, or 10 nanoseconds. As described in detail below, this difference in pulse width affects the writing period of the static column mode device. The / CAS pulse having a pulse width of 15 nanoseconds and 1
The 0 ns / WE pulse is used as an example, and different speeds of / CAS and /
It has a different pulse width from WE.

Address multiplex format DR
Within AM, / WE remains high when / CAS is low, so the difference between industry-established t _CAS and t _WE is whether it is a fast page mode device or a static column mode. It does not affect the reading of data from the DRAM, regardless of whether it is a device.

The circuit according to the present invention employs a DR for writing data.
AM operation is affected. Therefore, here, the DRAM
Only the operation of writing data to the memory will be described in detail.

In order to effectively write data to a DRAM, the following is required. That is, (i) valid data, (ii) a valid address for storing data, and (iii) a global write enable signal (“GW
E "), which is an active internal write enable signal (the global write enable signal is also referred to as the write strobe signal or referred to by some other name, but generally includes a write cycle). ) Associated with a signal indicating that all signals required for are received.)

[0009]

However, DRA
The control signals required to write data to M differ between the static column mode device and the fast page mode device. The industry-established control signals required to write data limit the effective write period in static column mode devices. In particular, control signals for latching valid addresses and determining the pulse width of the GWE are different between the fast page mode device and the static column mode device. Due to such a difference, the conventional static column mode device is inferior in speed as compared with the fast page mode device.

The basic difference in writing data to the fast page mode device and the static column mode device can be explained with reference to FIGS. 4 (a) to 4 (d). The display of the signal as the active high signal or the active low signal is not limited to this. Rather, an active high signal or an active low signal is merely selected as an example. When writing data to any DRAM, the time t ₀
Is at a low level. Unless recorded otherwise, / RAS is considered low. When writing data to the fast page mode device, the data goes low / CAS or / WE
Latched on the trailing edge. In the time t _1,
Both / CAS and / WE go low, latching data. The data is latched until either / RAS or / CAS becomes high level.

In the fast page mode device, the effective address is also at low level / CAS or / W
Latched on edge after E. The address holds the latched state, in the time t _3, is opened at the next edge of / CAS. That is, the address is latched as long as / CAS is at the low level (period of t _CAS ), no matter how the state of / WE changes. The latch releases the address when / CAS goes high. In addition, the global write enable signal of the fast page mode device generally does not depend on / WE, and is valid as long as / CAS is at a low level. Therefore, the GWE of the fast page mode device is extended in the period of t _{GWE (FPM)} as shown in FIG.

In the static column mode device,
Latched in the same way as fast page mode devices. However, the addresses are latched differently.
The address is latched at the edge after / CAS or / WE that goes low. Unlike the address latch of the fast page mode device, that of the static column mode device releases the address when either / CAS or / WE goes high. Since the active low / WE pulse is shorter than the active low / CAS pulse as established by industry standards, the validity period of the address is shorter in static column mode devices than in fast page mode devices. ing. In the static column mode device, when / RAS, / CAS and / WE are all at the low level, a GWE signal is generated, indicating that all the signals necessary for executing the writing have been supplied. . Since the signal / WE is shorter in the static column mode device, the active period required for the GWE signal is shorter than that in the fast page mode device (shown by t _{CWE (SCM)} in FIG. 4D). ). Unless this t _{CWE (SCM)} extends as shown by the dashed line in FIG. 4 (d), the device will be slow in terms of speed.

The present invention has been made in view of such a problem, and an object thereof is to make an effective write period of a static column mode device substantially the same as an effective write period of a fast page mode device.
An object of the present invention is to provide a circuit and a method for extending a writing period of a DRAM, which can guarantee appropriate writing of data in a static column mode device.

[0014]

[Means for Solving the Problems]

According to the first aspect of the present invention, there is provided a circuit for extending a write period of a DRAM, wherein a write enable signal from an external device is provided.
While receiving a write control signal including
Generates an internal write enable signal for the RAM.
Hold the internal write enable signal for a predetermined period.
A first circuit that is connected to the first circuit, write
And a mode signal indicating whether the DRAM is in a fast page mode or a static column mode.
Indicates that the operation mode is the static column mode, and the write cycle signal is active.
In response to this, the address input to the address latch circuit of the DRAM and used for writing in the DRAM can be changed without being affected by the external write enable signal changing from the active state to the inactive state. It functions to hold for a predetermined period, and generates an address delay signal such that the address continues to be held inside the address latch circuit even after the state change of the write enable signal during the predetermined period. Second
Circuit.

In this circuit for extending the write period of the DRAM, particularly in a DRAM operating as a static column mode device, an internal write enable signal (global write enable signal GWE) generated internally by the first circuit is predetermined. Extended period. The address is held by the address latch circuit so that a valid address is supplied during the extended period. As a result, the write timing in the static column mode device is improved, and the write speed of the static column mode device becomes equal to that of the fast page mode device.

A circuit for extending a write period of a DRAM according to claim 2, wherein the first circuit further comprises a first input terminal for receiving an external write enable signal, and a column address. A structure comprising a second input terminal for receiving a strobe signal, a third input terminal for receiving a row address strobe signal, and a first output terminal for generating the internal write enable signal It is.

According to a third aspect of the present invention, in the circuit for extending a write period of a DRAM, the first circuit logically converts an external write enable signal and a column address strobe signal when an internal write enable signal is generated. A write cycle signal received by the second circuit when the DRAM is in the static column mode after generating the internal write enable signal and for a predetermined period of time after the write cycle signal is received by the second circuit. The external write enable signal and the column address strobe signal are configured to be separated from each other, so that even if the external write enable signal changes from the active state to the inactive state, the internal write enable signal does not change to the inactive state. Is characterized by Thus, after the write enable signal and the column address strobe signal are first received, the two signals are separated and no noise is received, thereby improving the noise margin in the static column mode device.

According to a fourth aspect of the present invention, there is provided a circuit for extending a writing period of a DRAM, wherein the second circuit further includes a writing circuit.
A first input terminal for receiving a cycle signal, and a second input terminal for receiving a row address strobe signal, wherein the second circuit is responsive to a change in state of the row address strobe signal. Thus, the address delay signal is terminated.

According to a fifth aspect of the present invention, there is provided a circuit for extending a writing period of a DRAM, wherein the second circuit further includes a timing circuit for setting the predetermined period. .

The circuit for the writing period extension of the DRAM of claim 6 is the circuit of claim 5, wherein, Thailand
The timing circuit includes a capacitor, and the predetermined period is
It is determined by discharging the capacitor .

According to a seventh aspect of the present invention, there is provided a circuit for extending a write period of a DRAM, wherein the circuit responds to the internal write operation.
Enable signal status from inactive to active
External write enable to change to active state
A first input terminal for receiving Le signal, the circuit in the
Responds to the active state of the
The internal write enable for a predetermined period.
Cable signal does not change to the inactive state.
Active indicating active write cycle for
A second input terminal for receiving a write cycle signal, a first output terminal for outputting the internal write enable signal during active said predetermined period, said previously constant
Address latch that holds the address for the specified period
It is connected to the road, and a second output terminal you outputs an address latch signal.

The circuit for the writing period extension of DRAM according to claim 8, in the circuit according to claim 7, circuit
Resets the internal write enable signal in response
To receive a row address strobe signal for
Is further provided.

The circuit for the writing period extension of DRAM according to claim 9, in the circuit according to claim 8, Kola
Input for receiving the address strobe signal
Terminal, further comprising a write enable signal, a low address
Strobe signal and column address strobe signal
The internal write enable signal is generated in response to the internal write enable signal .

The circuit for the writing period extension of DRAM of claim 10, wherein, in the circuit according to claim 7, times
The path is further predetermined in response to the row address strobe signal.
A timing circuit for determining the set period .

A circuit for extending a writing period of a DRAM according to claim 11 is the circuit according to claim 10 ,
The timing circuit includes a capacitor and has a predetermined period.
The interval is determined by the discharge amount of the capacitor .

The circuit for the writing period extension of the DRAM of claim 12, wherein the write enable signal from the outside
Receiving the write control signal including the
A first input terminal for receiving a write enable signal, a second input terminal for receiving a column address strobe signal, and a circuit for receiving a row address strobe signal. A third input terminal, and a first output terminal for generating the internal write enable signal,
Activating the internal write enable signal
After the write enable signal from the outside and
Column address strobe signal from active state
Not be affected by the inactive state
In addition, during the predetermined period, the internal write
A first circuit for holding an enable signal in an active state; and a first input terminal for receiving an active write signal. A circuit for generating an address delay signal to be held in an address latch circuit, wherein a second input terminal for receiving a row address strobe for terminating the address delay signal, and the predetermined period are set. And a second circuit further including a timing circuit including a capacitor for the second circuit .

According to a thirteenth aspect of the present invention, there is provided a method for extending a writing period of a DRAM, comprising the steps of: receiving a write control signal;
Te, the method comprising: generating an internal write enable signal active DRAM, the write control signal
Status without being affected by changes in
In the write column mode, the internal write enable signal
Holding the active state for a predetermined period of time
And a step of holding an address in an address latch circuit in the DRAM for a predetermined period, and is applied to a DRAM configured as a static column mode.

According to a fourteenth aspect of the present invention, in the method for extending a write period of a DRAM, the step of receiving a write control signal includes receiving a write enable signal, a row address strobe signal, and a column address strobe signal, respectively. Things.

The method for extending a write period of a DRAM according to claim 15, wherein in the step of generating the internal write enable signal, it is determined whether or not the write control signal is in an active state.
When the built-in control signal is active,
The internal write enable signal is generated .

The method for writing term extension of the DRAM of claim 16, wherein during the predetermined period, in the step of holding the internal write enable signal, the outer
The write enable signal from the section is separated from the column address strobe signal, and the internal write enable signal is held for a predetermined period.

The method for extending a write period of a DRAM according to claim 17, wherein the step of holding the internal write enable signal further generates a first delay signal for determining the predetermined period. Things.

A method for extending a writing period of a DRAM according to claim 18 is characterized in that the predetermined period is determined by discharging a capacitor.

According to a nineteenth aspect of the present invention, in a method of extending a write period of a DRAM, a delay signal is generated in a step of holding an address in an address latch circuit in the DRAM, and the delayed signal is applied to the address latch circuit in the DRAM. It is characterized by doing. D according to claim 20
Method for writing term extension of RAM is, from the outside
Write enable signal, column address strobe signal
Signal and row address strobe signal, and the signal state of each received signal is all active.
Generating a DRAM internal write enable signal that changes from an inactive state to an active state when the internal write enable signal changes to an active state ;
External write to stay active
Enable signal and column address strobe signal
Between the input terminal and the output terminal of the internal write enable signal.
Internal write enable signal active in signal path
Turns off when the condition is reached, and is provided in the signal path.
Transistors with the function to deactivate certain circuit elements
Feeds the internal write enable signal through the
Back and the internal write enable signal
Is activated in the signal path when
Deactivates certain circuit elements by the action of transistors
State, a node provided in the signal path
External write enable signal and column address
Separating the dress strobe signal .
21. An extension of a writing period of the DRAM according to claim 20.
The method further includes an external write enable signal and
And before the column address strobe signal is disconnected.
The stage where the signal state at the node is held by the latch circuit
Floor and the signal state is active for a predetermined period
Signal and connected to the node,
Node to ground level when connected
Input the hold signal to another transistor that has a function and
Off other transistors for a specified period of time.
By keeping the signal state of the node constant,
After the write enable signal becomes active,
The internal write enable signal for a predetermined period
And maintaining an active state in advance by the holding signal
After a specified period, the row address strobe signal or
Indicates that one of the column address strobe signals is inactive.
Internal write enable
The signal changes from the active state to the inactive state.
And the step of causing The method for extending a write period of a DRAM according to claim 21, further comprising: receiving a write control signal, and changing an internal write enable signal of the DRAM from an inactive state to an active state based on the received write control signal. Generating an internal write enable signal from an active state to an inactive state substantially independently of a signal state of a write control signal during operation of the DRAM in the static column mode. Holding the address in the address latch circuit during the set period. Claim 2
2. The method for extending the writing period of the DRAM described in 2.
Receiving a write control signal and generating an internal write enable signal for the DRAM that changes from an inactive state to an active state based on the received write control signal;
Is in the fast page mode or the static column mode.
When the AM is in the fast page mode, the state of the internal write enable signal is changed based on the timing of the write control signal. When the DRAM is in the static column mode, the state of the internal write enable signal is changed by a timing circuit. Determining and changing the internal write enable signal from an active state to an inactive state substantially independently of a signal state of the write control signal.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration of a circuit 1 for extending a write period of a DRAM according to an embodiment of the present invention. This circuit 1 includes a delay circuit 10 as a second circuit.
And a global write enable signal generation circuit (hereinafter, referred to as a GWE generation circuit) 20 as a first circuit.

The delay circuit 10 has three input terminals 12, 1
4 and 16 and two output terminals 18 and 19. The delay circuit 10 has a write cycle signal / WTCY,
Row address strobe signal / RAS and fast page mode signal FPMPAD are received as input signals. Active-low signal / WTCY is DRAM
When both of the signals / CAS and / WE become low level, indicating that the active write cycle has started, the signals are received at the input terminal 12 of the delay circuit 10. In particular, the active low signal / WTCY is set to / CAS and / W
Each time E goes low, it is input to the delay circuit 10. As is well known in the art, some devices receive two / CAS or two / WE signals. For example, a "by-16"("x16") device receives two / CAS signals and one / WE signal, or one / CAS signal and two / WE signals. Thus, the method and circuit of the present invention provide at least one / CA
When S and one / WE become low level, a low signal / WT
It can be used with any DRAM that generates CY. Here, the start of the active write cycle
The write cycle signal / WTCY indicating
"Active write signal" and "active
Write cycle signal ".

An input terminal 14 provided for receiving / RAS is used to reset the circuit. Since both the static column mode device and the fast page mode device are page mode devices (ie, the row address is held while the column address is changing), / RAS is held at a low level. As will be described in detail later, when / RAS goes high, the circuit is reset.

Finally, the FPMPAD is received at the input terminal 16 of the delay circuit 10. FPMPAD indicates whether the device is a fast page mode device or a static column mode device. Certain output signals are not required in fast page mode devices.
As will be described, FPMPAD is selectively used to generate an inactive output signal in the circuit. F
The state of the PMPAD is determined by selecting a metal or a wire bond, or determined at an input terminal based on a program.

The delay circuit 10 supplies a static column holding signal / S as a first delay signal from a first output terminal 18.
HOLD, and a static column delay signal / SCDELA as a second delay signal from the second output terminal 19.
Outputs Y. / SCHOLD is input to a global write enable signal generation circuit (GWE generation circuit) 20 as described in detail in FIG. The active low signal / SCHOLD allows the GWE generation circuit 20 to generate an "extended" global write enable signal GWE at the output terminal 22. The active signal / SCHOLD causes the GWE circuit 20 to ignore / WE, retain an effective GWE, and extend the effective write period of the circuit. Here, the static column delay signal / SCDEL
AY is one specific example of the “address delay signal” in the present invention.
Corresponds to the example.

The second output signal / SCDE of the delay circuit 10
LAY holds an address in the address latch circuit 28. In order to extend the effective write period of the static column mode device, it is necessary to extend the internal global write enable signal GWE and hold the address in the address latch circuit 28.

FIG. 2 shows a specific logic circuit diagram of the delay circuit 10. The delay circuit 10 is a NAND gate 10
4 and 106 are provided. The NAND gate 104 has input terminals 108 and 110 (corresponding to the input terminal 12 in FIG. 1) and an output terminal 112. The NAND gate 106 has input terminals 114 and 11
6, and an output terminal 118. The NAND gates 104 and 106 are connected to each other so as to generate and latch / SCHOLD.

In the initial state, / SCHOLD and / WTCY supplied to the input terminal of the NAND gate 104 are both at a high level. When / WTCY goes low,
The output terminal 112 of the NAND gate 104 becomes high level. The output terminal 112 is the input terminal 1 of the NAND gate 106
14. Since the initial state of the input terminal 116 of the NAND gate 106 is at a high level, the output terminal 118 of the NAND gate 106 is at a low level, and generates a low signal / SCHOLD. As will be described in detail later, / SCHOLD is latched for a fixed period set according to the circuit or until the state of / RAS resets the circuit. As shown in detail in FIG.
GWE circuit 20 provides / WE and / CA during a given period.
Ignore S and receive / SCHOLD to generate an expanded GWE signal.

The output terminal 112 of the NAND gate 104 is also connected to the address control circuit 120 for generating / SCDELAY. As mentioned above, D
In order to write data to a desired address in the RAM, valid data and a valid address corresponding to the active GWE signal are required. That is, the extended GWE signal is useless if a valid address is not retained. Therefore, the delay circuit 10 also generates a signal to hold a valid address. / SCDEL
AY is output to an address latch circuit 28 in the DRAM to hold a valid address.

More specifically, a high-level signal output from the output terminal 112 of the NAND gate 104 is input to the NAND gate 122 through the input terminal 124.
Here, since the initial state of the input terminal 126 of the NAND gate 122 is at the high level, the output signal from the output terminal 128 of the NAND gate 122 is at the low level. An output signal from the output terminal 128 is input to the NOR gate 130 through the input terminal 132. On the other hand, FPMPAD is input to the NOR gate 130 through the input terminal 134. F
Each time PMPAD goes high, indicating that the device is a fast page mode device, the output signal from output terminal 136 goes low. The output terminal 136 is connected from the output terminal 142 to an inverter 138 for generating a high (inactive) signal / SCDELAY. Device is FPMPAD
Is a fast page mode device when is at high level, / SCDELAY does not need to hold a valid address in the address latch circuit 28.

When FPMPAD is at a low level, indicating that the device is a static column device, the input signal to input terminal 134 is at a low level. Therefore, the NOR gate 130 operates as an inverter of a signal input to the input terminal 132. When the output signal from the output terminal 112 of the NAND gate 104 goes high during the write cycle, the NAND gate 122
Input signals to the input terminals 124 and 126 are both at a high level. Therefore, the output signal of the NAND gate 122 becomes low level. This low signal is inverted by each of NOR gate 130 and inverter 138, and as a result, low (active) signal / SCDE is output from output terminal 142.
LAY occurs. Therefore, the address is held in the address latch circuit 28 by the row signal / SCDELAY while the GWE signal is held by the row signal / SCHOLD.

Active signals / SHOLD, / SCD
ELAY is held until reset by the reset circuit 150. The reset circuit 150 receives / RAS at an input terminal 151 (corresponding to the input terminal 14 in FIG. 1) of the inverter 152 for automatically resetting the delay circuit 10. Output terminal 15 of inverter 152
4 is connected to the input terminal 158 of another inverter 156. Output terminal 160 of inverter 156 is connected to control electrode 164 of N-channel transistor 162. When / RAS goes high to indicate the end of the write cycle, / RAS goes to the inverter 15 level.
2, 156 and the control electrode 1
A high level signal is input to 64. This high-level signal turns on the transistor 162 and pulls down the node 165 to low level.

The node 165 is connected to the input terminal 114 of the NAND gate 106, so that the input terminal 114 is pulled down to the initial low level state. Where / W
It is recalled that input terminal 114 was pulled high by output terminal 112 of NAND gate 104 after TCY went low during the active write cycle. Further, since the low level signal of the node 165 is input to the input terminal 114 of the NAND gate 106,
The output terminal 118 becomes high level. Therefore, / S
HOLD is reset to an initial high level state.
The input terminal 108 of the NAND gate 104 for receiving / SCHOLD is also reset to its initial state.
Therefore, when another low signal / WTCY is generated later to indicate that another write cycle has started, the output terminal 11
2 generates an appropriate signal. Since the low / WTCY signal is generated when a write cycle is detected, / WTCY input to the input terminal 110 is automatically reset at the end of the write cycle when / RAS goes high.

The low level signal at node 165 is also input to input terminal 124 of NAND gate 122,
Reset SCDELAY. NAND gate 122
Is at a low level,
A high level signal is generated at the output terminal 128. If the device is a static column mode device (ie, F
If PMPAD is at the low level), the high level output signal is inverted by the NOR gate 130 and output from the output terminal 136 as a low level signal.
This low level output signal is inverted by the inverter 138 to generate a high signal / SCDELAY. Therefore, / SCDELAY is also reset to its initial value.

Finally, the input terminal 1 of the NAND gate 106
16 and the input terminal 126 of the NAND gate 122 are also reset to the initial values and the appropriate / SCHOLD and / SCDE
An LAY occurs, ensuring that an active / WTCY pulse will be received later. When the node 165 goes low, the transistor 166 turns on. Therefore,
A current path is formed via the transistor 166 and the node 1
68 is charged to the VCC level. The high-level signal at the node 168 passes through the first inverter 174 and the second inverter 176, and becomes a high-level signal as the input terminal 116 of the NAND gate 106 and the NAND gate 122.
Is input to each of the input terminals 126. Therefore, the output signals / SCHOLD and / SCDELAY and the respective input signals to the latch circuit 102 and the address control circuit 120 can be reset by / RAS.

If the delay circuit 10 is not reset by / RAS, / SCHOLD and / SCDE
The LAY is controlled by the latch circuit 102 and the address control circuit 1 by the interruption of the reset circuit 150.
Reset with the input signal to 20. / WTCY
Becomes low level, and the output terminal 1 of the NAND gate 104 becomes
When a high level signal is output from 12, the transistor 166 is turned off by the high level signal. Therefore, the node 168 connected to the capacitor 172 is discharged via the power supply 170. The period required to discharge capacitor 172 is determined by the size of capacitor 172 and the amount of current flowing through power supply 170. The size of this capacitor 172 and the amount of current flowing through power supply 170 correspond to the speed of the device, ie, the desired minimum duration of GWE, / SCHOLD and / SCDELAY.

The capacitor 172 discharges and the node 168
Becomes low level, this low level signal passes through inverters 174 and 176, and the input terminal 116 of NAND gate 106 and the input terminal 1 of NAND gate 122
26 is input as a low level signal. The low-level signal input to the input terminal 116 of the NAND gate 106 is supplied to the output terminal 118 of the NAND gate 106 via / SCHOLD.
To its initial high level state. A low-level signal input to the input terminal 126 of the NAND gate 122 resets / SCDELAY. That is, when a low-level signal is input to the input terminal 126 of the NAND gate 122, a high-level signal is output from the output terminal 128. If the DRAM is a static column mode device and FPMPAD is low, NOR gate 130 acts as an inverter for the output signal from output terminal 128. Accordingly, the high-level signal output from the output terminal 128 is inverted by the NOR gate 130 and then further inverted by the inverter 138 to generate a high signal / SCDELAY.

When / WTCY goes high (or / WTCY goes high) after the interruption period by the reset circuit 150, the latch circuit 102
And each input signal to address control circuit 120 is reset, and active / SHOLD and / S
Ensures that the CDELAY signal occurs on the next active / WTCY. That is, after the interruption period, / SCH
OLD is at a high level as described later. If / W
When TCY is already at the high level (or when / WTCY is at the high level), the NAND gate 1
The output signal from the output terminal 112 at 04 becomes low level, and the input terminals 114 and 124 are reset to the initial low level state. When a low-level signal is output from the output terminal 112 of the NAND gate 104, the transistor 166 is turned on, and the capacitor 172 turns the node 16 off.
8 is charged. The high level signal at node 168 is inverted by inverters 174 and 176 and
6, 126 are input as high level signals. Thus, after a delay due to the interruption, / SCHOLD and / SCD
ELAY is reset together with the latch circuit 10
2 and the address control circuit 120 are / WTCY
Is reset when it goes high.

In summary, the delay circuit 1 shown in FIG.
0 generates a signal / SCHOLD input to the GWE generation circuit 20 shown in detail in FIG. Active signal / S
When a HOLD occurs, the GWE generation circuit 20 generates an expanded GWE signal. Delay circuit 10 also generates signal / SCDELAY. This / SCDELAY allows an address to be held in an address latch for a static column mode DRAM during an extended period between write cycles. Although the preferred configuration of the delay circuit 10 is shown in FIG.
8 holds a first delay signal (/ SC) for holding an address.
DELAY) and other circuits that generate a second delay signal (/ SCHOLD) to extend the GWE signal are also within the scope of the invention.

FIG. 3 shows a preferred circuit configuration of the GWE generation circuit 20. The GWE circuit 20 includes a GWE generator 202 that generates a GWE signal, and a static column hold circuit 204 that determines the duration of the GWE signal. First, the GWE generator 202 will be described in detail, and then the static column hold circuit 20
4 will be described in detail.

GWE generator 202 receives / WE and / CAS as inputs and generates output signal GWE. In particular, the input terminal 208 of the NOR gate 206 has / WE input terminal 2
10 is input with / CAS. / WE and / CAS
Are low level, indicating an active write cycle, the output terminal 21 of the NOR gate 206
2 becomes high level. An output signal from the output terminal 212 is input to the NOR gate 214 via the first input terminal 216. The GWE signal is input to the second input terminal 218 of the NOR gate 214 via the feedback path 219. That is, when a valid high-level GWE signal is generated, the high-level GWE signal is input from the input terminal 218 to the NOR gate 214, and is input to the GWE generator 202.
Causes changes in WE and / CAS to be ignored. That is, the high level signal input to the NOR gate 214 is applied to the NOR gate 214 regardless of the state of / WE or / CAS.
Is low level. This is especially important in static column mode devices, where the shorter the duration of / WE, the sooner the GWE is reset.

An incorrect / WE or / CAS signal is applied to the input terminal 208 or the input terminal 210 of the NOR gate 206.
A deglitching circuit 235 is provided to ensure that valid signals are input as the signals appear, and that valid GWE signals are generated. In particular, an output signal from the output terminal 220 of the NOR gate 214 is input to the inverter 222. Inverter 2
22 generates an output signal from the first node 224.
The node 224 is connected to a pair of inverters 226 and 228 for latching a signal at the node 224. Output terminal 220 of NOR gate 214 is also connected to inverter 232. The output signal of inverter 232 occurs at a second node 234. First
The signals generated at the node 224 and the second node 234 are input to the deglitching circuit 235, respectively.

The deglitching circuit 235 is connected to the node 2
24 and the node 234, and a valid signal / W
Determine if E and / CAS have been received. Node 234 is connected to delay capacitor 236.
A delay occurs as the delay capacitor 236 charges. The capacitance of the delay capacitor 236, that is, the capacitor 236
Is determined by the determined amount of glitching. As described above, the circuits and methods of the present invention can be applied to many DRAMs operating at different speeds.

When the delay capacitor 236 is charged, the high level signal at the node 234 is
8, 240 are sequentially input. The output signal of the inverter 204 is input to the NAND gate 242 via the input terminal 244. Node 224 is the second NAND gate 24
2 input terminal 246. Since the input signals represent the state of the signal at the output terminal 220 of the NOR gate 214 at different periods, the input signals determine whether / WE and / CAS are valid signals. If both of the input signals at the input terminals 244 and 246 are high,
To indicate WE and / CAS input signals,
The output signal of the NAND gate 242 is at a low level. The output signal of the NAND gate 242 is output from the inverters 248 and 25.
0, an inverted GWE signal is generated at node 251. The inverted GWE signal is supplied to the inverter 25
2 and becomes a high (active) GWE signal.

The GWE signal is supplied to the feedback loop 219.
To the control electrode 256 of the P-channel transistor 254 via The transistor 254 is connected to the enable terminal 258 of the inverter 222. When the GWE signal goes low, the transistor 254 turns on and the inverter 222 turns on the NOR gate 214.
Can be received. On the other hand, effective high GWE
When the signal is generated, the transistor 254 is turned off and the inverter 222 is deactivated. By this, NOR gate 2
14 is disconnected from / WE or / WE or /
CAS is ignored. Although the node 224 is disconnected, the state at the node 224 is determined by the inverters 226 and 228.
And is held by a latch circuit composed of Effective GWE
It is understood that when a signal is generated, the noise margin of the DRAM is improved by separating / WE and / CAS. That is, after a valid GWE signal is generated, no noise is generated in the input signal / WE or / CAS.

As described above, the GWE generator 202
Having described the generation of the signal, the static column hold circuit 204 for controlling the duration of the GWE signal will now be described. This static column hold circuit 204 guarantees that the GWE signal is extended in a static column mode device.

Static column hold circuit 204
Includes a fast page mode circuit 260 and a static column mode circuit 262. These circuits are connected to node 224, and / CAS and / WE
In response to the voltage at node 224 (and thus GWE).
Is changed when appropriate. Each circuit is at node 2
Form a current path from 24 to ground. When the transistor is turned on in each path, node 224 is pulled down to ground level and GWE via NAND gate 242 and inverters 248, 250, 252.
Reset. The operation of the circuit applied to the fast page mode device will be described first, and the operation of the circuit applied to the static column mode device will be described next.

In the fast page mode, a fast page mode circuit is transmitted from a node 224 through a series circuit of three transistors, a transistor 264 having a control electrode 266, a transistor 268 having a control electrode 270, and a transistor 272 having a control electrode 274. A current path to ground at 260 is formed. When transistors 264, 268, and 272 are turned on under the proper conditions, node 224 is pulled down to ground level, resetting GWE.

FRMPAD is input to the control electrode 266 of the transistor 264. When the device is a fast page mode device, and thus FPMPAD is high, transistor 264 turns on, connecting node 224 to fast page mode circuit 260. Also, the control electrode 27 of the transistor 268
0 is input with / CAS. As described above, the high signal / CAS resets the address latch in a fast page mode device. Eventually, the transistor 272
Is turned on, the fast page mode circuit 260
A series circuit is formed from the node 224 to the ground through the circuit. When the fast page mode is set and GWE goes high, the transistor 272 is turned on. Signals of both FPMPAD and GWE are input to the control electrode 274 of the transistor 272 via the NOR gate 276.

NOR gate 276 receives the inverted GWE signal from node 251 at input terminal 278.
NOR gate 276 receives the inverted FPMPAD signal at input terminal 280 via inverter 282. Therefore, when the device is a fast page mode device as indicated by high FPMPAD and GWE is high indicating an active write cycle, the output signal of NOR gate 276 is high and transistor 274 is turned on. . Thus, when the fast page mode device is in an active write cycle, two transistors 2 connected in series
Both 64 and 272 are turned on. Therefore, GWE is reset when / CAS goes high.

On the other hand, in the static column enable mode, FPMFAD is at the low level,
Transistor 264 turns on, disconnecting fast page mode circuit 260 from node 224. However, if the device is a static column mode device, a different current path from node 224 to ground is formed via static column mode circuit 262. That is, a current path is formed by an arrangement of transistors including a transistor 284 having a control electrode 286, a transistor 288 having a control electrode 290, a transistor 292 having a control electrode 294, and a transistor 296 having a control electrode 298.

Control electrode 2 of transistor 284
Reference numeral 86 denotes a signal / SCHOLD from the delay circuit 10 shown in FIG.
To receive. When / SCHOLD is low, indicating an active write cycle, transistor 28
4 turns off. A parallel circuit including a pair of transistors 288 and 292 is connected to the transistor 284 in series. The transistors / 288 and 292 each have / C
AS and / WE are input. Therefore, when one of / CAS and / WE goes high, node 2
24 is the ground level. Finally, transistor 2
96 is connected in series with the transistor 284 and the pair of transistors 288 and 292 between the node 224 and the ground. The control electrode 298 of the transistor 296 is connected to one output terminal of the NOR gate 300. FPMPAD is input to the input terminal 302 of the NOR gate 300, and the GWE signal before inversion is input to the other input terminal 304 from the node 251. During the active write cycle, in the static column mode, both FPMPAD and node 251 are low. Therefore, the output signal of the NOR gate 300 is at a high level, and the transistor 296 is turned on.

The significance of / SCHOLD generated by the delay circuit 10 shown in FIG. 2 is now apparent. That is, when the low signal / SCHOLD is generated to indicate that it is an active write cycle, the transistor 284
Is turned off, and / CAS and / WE are not accepted with a delay due to interruption. As a result, during the interruption delay, node 224, the GWE, remains high for the extension period caused by the interruption delay.
When / SCHOLD goes high (ie, / SC
When HOLD is reset by the delay circuit 10, the transistor 284 is turned on. So if G
If WE is high, node 224 is pulled down to ground level whenever either / CAS or / WE goes high. Write cycle is / R
The process ends each time AS goes high.

Finally, node 224 is connected to transistor 30
6 is connected. / RAS is input to the control electrode 308 of the transistor 306, and the node 224 (and GWE) is reset every time / RAS goes high. As described above, the write cycle automatically ends when / RAS goes high.

In summary, the GWE generation circuit 20 includes circuit elements for inputting / WE and / CAS, generates the global write enable signal GWE, and guarantees that the GWE is valid. The GWE generation circuit 20 is a fast page mode circuit 2
60, when / CAS goes high when the device is a fast page mode device,
Reset GWE. Finally, the GWE generation circuit 20
Includes a static column hold circuit 262 for receiving the delay signal / SCHOLD. This delayed signal / SCHOLD is input to control electrode 286 of transistor 284 for preventing / WE or / CAS from resetting GWE. Therefore, GW
E is extended in static column mode devices. Further, the address latch circuit 2 is generated by / SCDELAY generated from the delay circuit 10 shown in FIG.
Since the address is held at 8, the speed level in the static column mode is not inferior to the fast page mode in the present invention, and operates at the same speed as an equivalent fast page mode device.

Although the present invention has been described with reference to specific examples, the present invention is not limited to these.
It goes without saying that any changes are possible within the spirit of the invention. Many modifications and other embodiments will be apparent to persons skilled in the art from the description herein. The invention is set forth in the following claims.

[0072]

As described above, according to the circuit and method for extending the write period of the DRAM of the present invention, the effective write period of the static column mode device is substantially reduced to the effective write period of the fast page mode device. The same can be ensured, and proper writing of data in the static column mode device can be guaranteed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a circuit for extending a writing period of a DRAM according to an embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing an internal configuration of a delay circuit in a circuit for extending a writing period of the DRAM of FIG. 1;

FIG. 3 is a logic circuit diagram showing an internal configuration of a global write enable generation circuit in a circuit for extending a write period of the DRAM of FIG. 1;

FIG. 4 is a timing chart of various control signals used in a DRAM.

[Explanation of symbols]

Reference Signs List 10 delay circuit (second circuit) 12, 14, 16 input terminal 18, 19 output terminal 20 global write enable signal generation circuit (G
WE generation circuit) 22 output terminal 24, 26 input terminal 28 address latch circuit

Continued on the front page (73) Patent holder 592207131 United Memories Inc. United MEMORIES IN C. 80919, Colorado, Colorado Springs Suite 109, List Drive 4815 (72) Inventor Oscar Frederick Jones, Jr., Colorado, United States State 80919 Colorado Springs, Santand Place 7235 (56) References

Claims (22)

(57) [Claims] 1. A circuit for use in a static column mode DRAM, wherein a write period of the DRAM is longer than an active state of an external write enable signal applied to the DRAM. A first circuit that receives a write control signal including a write enable signal from the first circuit, generates an internal write enable signal of the DRAM, and holds the internal write enable signal for a predetermined period; and a first circuit. And receives a write cycle signal and a mode signal indicating whether the DRAM is in a fast page mode or a static column mode.
When the write mode signal indicates the active column mode is the static column mode, the write cycle signal becomes active.
In response to the state, the address input to the address latch circuit of the DRAM and used for writing in the DRAM is changed when the external write enable signal changes from an active state to an inactive state. It functions to hold for the predetermined period without being affected, and holds the address inside the address latch circuit during the predetermined period even after the state of the write enable signal changes. And a second circuit for generating an address delay signal that continues to be generated. A first input terminal for receiving the write enable signal from the outside, a second input terminal for receiving a column address strobe signal, and a row address strobe signal. 2. The circuit according to claim 1, further comprising a third input terminal for receiving a write command, and a first output terminal for generating the internal write enable signal. 3. The first circuit is configured to logically combine the external write enable signal and the column address strobe signal when the internal write enable signal is generated, and after generating the internal write enable signal, when the DRAM is in the static column mode, the write service
An external write enable signal and the column address strobe signal are separated from each other during the predetermined period after the cycle signal is received by the second circuit. 3. The circuit according to claim 2, wherein the internal write enable signal does not change to the inactive state even when the signal changes from the active state to the inactive state. 4. The write circuit according to claim 2, further comprising :
A first input terminal for receiving a cycle signal, and a second input terminal for receiving a row address strobe signal, wherein the second circuit is responsive to a change in state of the row address strobe signal. 2. The DRA according to claim 1, wherein the address delay signal is terminated.
Circuit for extending the writing period of M. 5. The circuit according to claim 4, wherein said second circuit further includes a timing circuit for setting said predetermined period. 6. The DR according to claim 5, wherein the timing circuit includes a capacitor, and the predetermined period is determined by discharging the capacitor.
Circuit for extending the writing period of AM. 7. A circuit used for a DRAM in a static column mode, wherein a write period of the DRAM is longer than an active state of an external write enable signal applied to the DRAM. A first input terminal for receiving the external write enable signal for changing a state of an internal write enable signal from an inactive state to an active state in response to a circuit, and wherein the circuit has an active state of the internal write enable signal; A second input terminal for receiving an active write cycle signal indicating an active write cycle for preventing the internal write enable signal from changing to the inactive state during a predetermined period; Active for the predetermined period A first output terminal that outputs an internal write enable signal; and a second output terminal that is connected to an address latch circuit that holds an address for the predetermined period and that outputs an address latch signal. A circuit for extending a writing period of a DRAM. 8. The DRAM of claim 7, further comprising a third input terminal for receiving a row address strobe signal for resetting the internal write enable signal in response to the circuit. Circuit for extending the period. 9. The semiconductor device further comprises a fourth input terminal for receiving a column address strobe signal, wherein the internal write enable signal is generated in response to the write enable signal, the row address strobe signal, and the column address strobe signal. 9. The circuit for extending a writing period of a DRAM according to claim 8, wherein: 10. The circuit for extending a write period of a DRAM according to claim 7, wherein said circuit further comprises a timing circuit for determining said predetermined period in response to a row address strobe signal. . 11. The circuit for extending a write period of a DRAM according to claim 10, wherein said timing circuit includes a capacitor, and said predetermined period is determined by a discharge amount of said capacitor. 12. A DRAM in a static column mode
A write control signal including an external write enable signal, wherein the write period of the DRAM is longer than an active state of an external write enable signal applied to the DRAM. Receiving a write enable signal in the DRAM, a first input terminal for receiving a write enable signal, a second input terminal for receiving a column address strobe signal, and a row address strobe. A third input terminal for receiving a signal, and a first output terminal for generating the internal write enable signal, after activating the internal write enable signal, the external write enable signal Signal and the column address strobe signal A first circuit for holding the internal write enable signal in an active state for the predetermined period without being affected by a change from an active state to an inactive state; and receiving an active write signal. A first input terminal for generating an address delay signal which is input to an address latch circuit of the DRAM and holds an address in the address latch circuit during the predetermined period, the address delay circuit comprising: A second input terminal for receiving a row address strobe for terminating the delay signal, and a second circuit further including a timing circuit including a capacitor for setting the predetermined period. Circuit for extending the writing period of the DRAM. 13. A DRAM in a static column mode
Receiving a write control signal, wherein the write period of the DRAM is longer than the active state of an external write enable signal applied to the DRAM. Generating an internal write enable signal for the active DRAM based on the reception of the signal; and pre-setting the internal write enable signal in a static column mode without being affected by a change in the state of the write control signal. Valid writing of a DRAM, comprising: holding an active state for a predetermined period; and holding an address in an address latch circuit in the DRAM during the predetermined period. How to extend the period. 14. The D according to claim 13, wherein the step of receiving the write control signal includes receiving a write enable signal, a row address strobe signal, and a column address strobe signal.
A method for extending a writing period of a RAM. 15. The method according to claim 15, wherein the step of generating the internal write enable signal comprises the step of:
Determines whether or not is in the active state, and
When the control signal is in the active state,
Generating an internal write enable signal.
The method for extending a writing period of a DRAM according to claim 13. 16. A step of holding the internal write enable signal for a predetermined period, disconnecting the external write enable signal and the column address strobe signal, and holding the internal write enable signal for a predetermined period. 14. The method for extending a write period of a DRAM according to claim 13, wherein the internal write enable signal is retained. 17. The method for extending a write period of a DRAM according to claim 16, wherein the step of holding the internal write enable signal further comprises generating a first delay signal for determining the predetermined period. . 18. The method according to claim 17, wherein the predetermined period is determined by discharging a capacitor. 19. A step of holding an address in an address latch circuit in a DRAM, generating a delay signal,
14. The method as claimed in claim 13, wherein the delay signal is applied to an address latch circuit in the DRAM. 20. A DRAM in a static column mode
Used in a method so that towards the writing period of the DRAM than the active state of the write enable signal from the applied external to the DRAM is increased, the write enable signal from the outside, a column address scan
While receiving the trobe signal and the row address strobe signal , the signal state of each received signal is all
Generating an internal write enable signal for the DRAM that changes from an inactive state to an active state when the active state is reached ;
External write enable signal
And the input end of the column address strobe signal and the
The signal path between the internal write enable signal and the output end
The internal write enable signal is active.
Off when it is in the state, provided in the signal path
A transformer having a function of deactivating a predetermined circuit element.
The internal write enable signal is
And when the internal write enable signal is in an active state.
When a predetermined circuit element provided in the signal path
To inoperative state the child by the action of said transistor
Thereby, from a node provided in the signal path,
The external write enable signal and the
Disconnecting the memory address strobe signal, the external write enable signal and the
Before the address strobe signal is disconnected.
Holding the signal state in the latch by a latch circuit
And that the signal state remains active for a predetermined period.
Signal, and is connected to the node and turned on.
Pull the node to ground level when in state
Input the holding signal to another transistor having the function of
The other transistor for the predetermined time period.
The signal state of the node by turning off the
And the internal write enable signal is activated.
Active state, the above-mentioned condition for a predetermined period
Maintain the active state of the external write enable signal
And after a predetermined period of time by the holding signal,
An address strobe signal or the column address strobe signal
One of the lobe signals becomes inactive
Activate the internal write enable signal accordingly
Changing the state from an inactive state to an inactive state . 21. A static column mode DRAM
And a method for making a write period of the DRAM longer than an active state of a write control signal including an external write enable signal applied to the DRAM, the method comprising receiving the write control signal. Generating an internal write enable signal of the DRAM that changes from an inactive state to an active state based on the received write control signal; and controlling the write control during operation of the DRAM in the static column mode. Changing the internal write enable signal from an active state to an inactive state substantially independently of a signal state of the signal; and holding an address in an address latch circuit for a predetermined period. Specially equipped DRAM to
For extending the writing period. 22. A DRAM in a static column mode
And a method for making a write period of the DRAM longer than an active state of a write control signal including an external write enable signal applied to the DRAM, the method comprising receiving the write control signal. And generating an internal write enable signal of the DRAM that changes from an inactive state to an active state based on the received write control signal; and wherein the DRAM is in either a fast page mode or a static column mode. In addition to determining whether the DRAM is in the operation mode, when the DRAM is in the fast page mode, the state of the internal write enable signal is changed based on the timing of the write control signal, and the DRAM is started in the static mode. In the column mode, the state of the internal write enable signal is determined by a timing circuit, and the internal write enable signal is changed from the active state to the inactive state substantially independently of the signal state of the write control signal. Changing to a state.
A method for extending a writing period of a RAM.