JPH0644072A - Instruction supplying system for parallel arithmetic circuit - Google Patents

Abstract

PURPOSE:To suppress the cost of a hardware and to improve a working rate by unifying a control storage for storing instruction sequences and execution- controlling respective execution units(EXU) at an exclusive execution management unit. CONSTITUTION:The execution management unit(EMU) 1 manages the operations of the EXUs 4-7, a control unit(CU) 2 reports the execution of instructions to the EMU 1 and the control storage(CS) 3 stores the instruction sequences to be supplied to the EXUs 4-7. Also, the execution units (EXU 1-4) 4-7 are controlled by signals from the EMU 1. Then, respective control lines 11-14 are for the EMU 1 to control the respective EXUs 4-7 and respectively constituted of request signals, Acknowledge signals, busy signals and the other control lines. In this case, the request signals request the transfer of the instructions from the EXUs 4-7 to the EMU 1, the acknowledge signals are outputted from the EMU 1 and indicate that the instructions to be fetched by the EXUs 4-7 are outputted on an instruction bus and the busy signals indicate that arithmetic operation is being executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction supply system for an arithmetic circuit that performs general arithmetic and a circuit that performs digital signal processing, and more particularly to an instruction supply system for a parallel arithmetic circuit.

[0002]

2. Description of the Related Art In a conventional parallel arithmetic circuit, as a method of supplying instructions to a plurality of arithmetic units, the same instruction sequence is given to all units, and each arithmetic unit has a control memory locally. However, there is a method in which each unit individually executes an instruction.

However, the former method is an effective means for vector data, but is not suitable for data in which arithmetic execution requests are randomly generated. Therefore, the latter method is adopted for such an application, for example, a simulation of a logic circuit.

Further, recently, a superscalar method has been proposed as a method for dynamically allocating a plurality of arithmetic units to a single instruction sequence. This is a method of determining what can be executed in parallel by hardware from a single instruction sequence and dynamically assigning it to a plurality of arithmetic units.

[0005]

In the above-mentioned conventional method, each arithmetic unit must be provided with a control memory individually. Moreover, in most of the systems, the same instruction sequence is stored in each control memory and each arithmetic unit simultaneously executes different instruction sequences. In this method, since each arithmetic unit operates independently, the cost of the circuit for synchronizing the units and the loss time due to the synchronization are large.

Although the sparse color system does not have such drawbacks, it is capable of executing only parallel processing suitable for its location because a single instruction string is given.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a plurality of operation executing units for performing an actual operation, a control storage unit for storing an instruction given to the operation executing units, an instruction supply to the operation executing units, and An execution management unit that controls the operation of the calculation execution unit;
And a control unit for controlling the entire calculation.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 is an execution management unit (EM
U) and manages the operation of the execution unit (EXU).
Reference numeral 2 is a control unit (CU) which notifies the EMU of execution of an instruction. Reference numeral 3 is a control memory (CS) which stores an instruction sequence given to the EXU. 4 is the execution unit 1 (E
XU1). Reference numeral 5 is an execution unit 2 (EXU2). Reference numeral 6 is an execution unit 3 (EXU3). And
Reference numeral 7 is an execution unit 4 (EXU4).

Each EXU4-7 is controlled by a signal from EMU1. A control bus 8 transfers commands and statuses between the CPU 2 and the EMU 1. An instruction address bus 9 gives an address of an instruction sequence to be transferred to each of the EXUs 4 to 7 to CS3. 10 is an instruction bus, CS
The instruction sequence read out from No. 3 is transferred to each EXU 4-7. This command bus 10 sends multiple commands at once,
The width is made wider than the bit width of the instruction. For example, when one instruction is expressed by 32 bits, if the bus width is 128 bits, 4 instructions can be sent to each EXU 4 to 7 in one transfer.

Reference numeral 11 is an EXU control line 1. Reference numeral 12 is an EXU control line 2. 13 is EXU control line 3
Is. And 14 is an EXU control line 4. Each control line is for the EMU 1 to control each of the EXUs 4 to 7, and is composed of a request signal, an acknowledge signal, a busy signal, and other control lines, respectively.
The request signal requests transfer of an instruction from the EXU to the EMU. The acknowledge signal is output from the EMU and indicates that the instruction to be fetched by the EXU is output on the instruction bus. The busy signal indicates that the EXU is performing an operation.

FIG. 2 shows the execution management unit (EMU) of FIG.
It is a figure which shows an example of a structure of 1. In FIG. 2, reference numeral 21 denotes a control unit that manages the entire EMU and allocates EXUs to requests from the control unit. An address register file 22 is composed of an address register group corresponding to each EXU on a one-to-one basis, and outputs an address to an instruction address bus according to a command from the arbiter. An arbiter 23 adjusts instruction transfer requests from the control unit and each EXU and allocates buses. Reference numeral 24 is a control bus. 25
Is the instruction address bus. 26 is EXU control line 1
Is. 27 is an EXU control line 2. 28 is EX
U control line 3. 29 is the EXU control line 4. These control bus 24, instruction address bus 25 and EXU control lines 1 to 4 (26 to 29) are the control bus 28, instruction address bus 9 and EXU shown in FIG.
It corresponds to the control lines 1 to 4 (11 to 14), respectively.
Next, the operation of this embodiment will be described.

FIG. 3 is a time chart showing the operation of this embodiment.

(1) First, when an operation request occurs in the parallel operation circuit shown in FIG. 1, CU2 notifies EMU1 of the start address of the operation instruction sequence to be executed (see 32), and E
Transmit the XU request command (see 33). And
EMU1 is the EX currently open for the request command
If U is present, send an operation acknowledge signal to CU2 (3
4), the instruction address register file 2 shown in FIG.
The address specified by CU2 is set in the address register corresponding to the two-open EXU (see 35), and the arbiter 2
Request bus rights from 3. Arbiter 23 EM bus
It is released to the control unit 21 of U1 and requests the address transmission to the instruction address register file 22. Then, the instruction address register file 22 sets the value of the address register to C
Send to S3 and read the contents of CS3 to the instruction bus 10 (see 36). When the value is confirmed, the arbiter 23
Sends an acknowledge signal to the EXU (see 38). This acknowledge signal also serves as a request signal for requesting the EXU to execute the operation.

The EXU receiving the acknowledge signal,
The instruction sequence on the instruction bus 10 is received, a busy signal is transmitted to the EMU 1 (see 39), and the execution of the instruction is started. EMU
1 receives the busy signal, releases the instruction bus 10, increments the value of the address register (see 35), and prepares for the next request.

When CU2 transmits an EXU request command, if all EXUs are in execution, EMU1 notifies CU2, and this command is suspended in EMU1. Then, when the execution of a certain EXU is completed and the ready state is reached, the pending request instruction is executed, and C
Notify U2 that the hold status has been released. The CU2 cannot generate the next request instruction until it receives this release status.

(2) If the instruction sequence held by the EXU being executed does not include the operation end instruction, it is assumed that the instruction sequence following the EXU is present, and the EXU sends the EMU1 again a bus request signal. Request the transfer of the instruction sequence (see 37). In the EMU 1 that receives the request, the arbiter 23 arbitrates the bus right, transfers the address corresponding to the right EXU from the instruction address register file 22 and reads CS3 (see 36), and sends an acknowledge signal to the EXU. Send (see 38). E receiving the signal
The XU again reads the instruction on the instruction bus 10, disables the request signal (see 37), and continues executing the instruction. EMU1 that received request signal disable
Returns an acknowledge signal to release the bus (see 38) and increments the address register to prepare for the next request (see 35). In this case, EMU1 to EXU
The acknowledge signal to is a response to the EXU request signal.

(3) The EXU which has executed the operation end instruction and completed the execution of the series of operation instruction sequences releases the busy signal and waits for the next execution request (see 39).

[0019]

As described above, according to the present invention, the control memory for storing the instruction sequence is one, and the execution control of each EXU is performed by the dedicated execution management unit, so that the hardware cost can be suppressed. ing. In addition, the execution management unit dynamically manages the calculation execution unit to reduce the load on the control unit, thereby reducing the idle time of the calculation unit and improving the operation rate of the calculation unit. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a configuration of an execution management unit (EMU) 1 in FIG.

FIG. 3 is a time chart showing the operation of this embodiment.

[Explanation of symbols]

 1 Execution Management Unit (EMU) 2 Control Unit (CU) 3 Control Memory (CS) 4 Execution Unit 1 (EXU1) 5 Execution Unit 2 (EXU2) 6 Execution Unit 3 (EXU3) 7 Execution Unit 4 (EXU4) 8, 24 Control Bus 9,25 Instruction Address Bus 10 Instruction Bus 11,26 EXU Control Line 1 12,27 EXU Control Line 2 13,28 EXU Control Line 3 14,29 EXU Control Line 4 21 Address Register File 23 Arbiter 31 Clock 32 Arithmetic Instruction Column start address (CU → EMU) 33 Operation request instruction (CU → EMU) 34 Operation acknowledge signal (EMU → CU) 35 Address register value (EMU → CS) 36 Instruction bus value (CS → EMU) 37 Request signal (EXU → EMU) 38 Ridge signal (EMU → EXU) 39 busy signal (EXU → EMU)

Claims (1)

[Claims] 1. A plurality of operation execution units for performing actual operation,
A control storage unit for storing an instruction to be given to the arithmetic execution unit,
An instruction supply system for a parallel arithmetic circuit, comprising: an execution management unit that controls the supply of instructions to the operation execution unit and the operation of the operation execution unit; and a control unit that controls the entire operation.