JPH0640618B2 - Eco-Cancer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In an echo canceller, after a received signal read from a storage circuit in an arithmetic cycle in the oldest order and a corresponding coefficient are added to the arithmetic circuit to update a coefficient used in the arithmetic cycle, The efficiency of the arithmetic circuit is improved and the operation of the memory circuit is performed by writing to the memory circuit in combination with the received signal read from the memory circuit and performing the arithmetic operation using the coefficient and the received signal updated by the arithmetic circuit. It is designed to reduce the speed.

[Industrial application field]

 The present invention relates to an improved echo canceller.

FIG. 4 shows an example of a line configuration diagram using an echo canceller.

As shown in the figure, the A side and the B side are connected by transmission lines 1 and 2, which are long-distance transmission lines, for example, satellite lines. Now, the signal x from the A side is applied to the hybrid circuit 4 on the B side via the transmission line 1, but the echo signal y is generated due to the impedance mismatch here.

Since the echo signal y returns to the A side again via the transmission line 2 and interferes with the call, the echo cancellers 5 and 6 are provided to sufficiently suppress such an echo signal.

The echo canceller 5 has a transmission characteristic close to the transmission characteristic of a portion that generates an echo (hereinafter referred to as an echo path), and takes in a signal x from the A side to approximate the echo signal (hereinafter referred to as a pseudo echo signal). Is generated and converted into a phase opposite to that of the actual echo signal y, the echo signal is canceled to some extent, and the attenuated echo signal (hereinafter referred to as residual echo signal) e returns to the A side.

Therefore, although the degree of call interference is improved, it is necessary to increase the operation efficiency of this echo canceller.

The echo canceller 6 is for suppressing the echo signal returning to the B side.

[Conventional technology]

FIG. 5 is a block diagram of the echo canceller, and FIG. 6 is an operation explanatory diagram of the convolution operation unit.

As shown in FIG. 5, the echo canceller has a coefficient storage circuit 8 for storing the coefficient h _i corresponding to the impulse response of the echo path and a reception signal storage circuit 7 for storing the reception signal x _n. A pseudo echo signal for suppressing the echo signal y _n generated in the echo path (not shown) by performing the convolution operation of the generated coefficient hi and the received signal x _n in the convolution operation unit 10. To occur.

And with the adder 11 With suppressing the echo signal by determining the adaptive controller using a residual echo signal e _n that can not be suppressed
12, and automatically h _i during a call by the coefficient updating calculation unit 9 close to the impulse response of the echo path, i.e. identified in the manner to suppress the echo signal.

Here, the echo canceller performs a convolution calculation and the like using the following equation.

・ Tampering operation (pseudo echo signal Occurrence of) - adding (Calculation of residual echo signal _{e n)} And coefficient change operation (calculation of _{h i)} However Here, since the convolution operation is a filter-like operation using the received signals x _ni and the coefficients h _i from the received signal storage circuit 7 and the coefficient storage circuit 8 as shown in FIG. 6, h _i is a tap coefficient, N is called the number of taps.

Further, in the equation (3), n represents a time series, and h _i at a certain time (n + 1) (i-th coefficient of a plurality of tap coefficients as shown in FIG. 6), that is, At time n before that That is, it is obtained using h _i . The K _n control coefficient is shown.

FIG. 7 shows a block diagram of a conventional example, and FIG. 8 shows an operation explanatory diagram of FIG. The symbols on the left side of FIG. 8 indicate the operation of the same signal portion in FIG.

The operation of FIG. 7 will be described below with reference to FIG. 8 assuming that the number of taps N = 512.

First, the input serial PCM signal x _n is converted into parallel data by a serial / parallel conversion circuit (not shown) and then corresponds to x _ni . Are written to the corresponding addresses in the reception signal storage circuit 7 and the coefficient storage circuit 8.

The signal x _ni read from this memory circuit is
Alternatively, since it is compressed to 8 bits by A-Law, it is assumed that the signal is expanded by a decompression part (not shown) in the multiplication circuit 13 and converted into a linear signal in order to facilitate the calculation.

In addition, it is assumed that the two memory circuits can be read and written independently.

Now, when the calculation start signal is input, the read address is added to the reception signal storage circuit 7 and the coefficient storage circuit 8 in order to calculate the above equation (1). Is read and multiplied by the multiplication circuit 13, and the calculation result is stored in the accumulator 15 via the addition / subtraction circuit 14. Is added to the input side of the adder / subtractor circuit (Fig. 8 (a)-~
reference).

Next, from the two storage circuits 7 and 8 in the same manner as above. Is read out and multiplied by the multiplication circuit 13. Is obtained, and this is added with the value of the previous accumulator 15 (hereinafter, abbreviated as ACC) in the adder / subtractor circuit 14. Is obtained and added to the accumulator 15, the value of the accumulator 15 is updated to this value and added to the addition / subtraction circuit 14 again.

When this operation is repeated 512 times, the accumulator 15 is shown in FIG.
(a)-Pseudo echo as shown in Is stored, and this is added to the addition / subtraction circuit 14.

On the other hand, from the terminal SIN echo signal y _n is addition and subtraction circuit 14 (-) since it is applied to the terminal operational in the above (2) is performed, the residual echo signal e _n obtained accumulator 1
5, output through the output register 16 (Fig. 8 (a)-
reference).

Next, the calculation of K _n is performed in the K calculation circuit 12 by using this e _n by the equation (4).

Furthermore, the tap coefficient at the next time is calculated by the above equation (3). X _n read from the received signal storage circuit 7 again by the operation of a selector (not shown) in the multiplication circuit 13 in order to obtain
_{K n} is multiplied by _K n · _{x n} is applied to the adder circuit 14 (FIG. 8 (b) - see ,,).

Here, it is read again from the coefficient storage circuit 8. Has been added, so it is added Is stored in the accumulator 15 and stored in the coefficient storage circuit 8. Is written at the address of and the coefficient is updated (Fig. 8
(b)-, see).

This is repeated 512 times and the stored coefficient is And a new signal x is stored in the received signal storage circuit.
_Since the oldest original signal x _n-511 is thrown in with _{n + 1} entered,
The above calculation is repeated again.

still, When updating Unlike the convolution operation, the reading of x and x _ni is shifted by one time strobe, so the timing of the read address is sent out as such (see FIG. 8 (b) -address).

[Problems to be solved by the invention]

As shown in the above, if formula (1) is calculated, formula (2) is calculated, and if it is completed, formula (3) will be calculated successively, so formulas (1) and (3) are calculated. _Therefore , the same signal x _ni and coefficient h _i have to be read and transferred twice, which reduces the efficiency of use of the arithmetic circuit.

Further, the two memory circuits are required to operate at the same operating speed as the arithmetic circuit, which causes two problems that power consumption increases.

[Means for solving problems]

As shown in FIG. 1, the above problem is caused by the i-th tap coefficient at time (n-1) that is one sample time older than time n. And the received signal x _ni that is older than the time n by i sample times as one word, a storage portion of N words that stores the received signals and tap coefficients for N taps, and 1 from the oldest received data in the N taps. Received signal x that is old by the sample time
A memory circuit having a dedicated register portion for storing _nN and an arithmetic circuit including a multiplication circuit and an addition / subtraction circuit are provided, and the arithmetic circuit receives the received signal x _nN from the dedicated register portion and the last tap from the memory portion. coefficient Is read out, the last tap coefficient is updated using the read received signal and tap coefficient, and a new tap coefficient is obtained only for one sample time. And update tap coefficient And the received signal x _{n- (N-2)} at the next sample time is written to the storage portion, and at the same time, the content of the dedicated register portion is changed to x
Updated to _{n- (N-1)} and updated tap coefficient And the received signal x _{n- (N-1)} are multiplied to start the cumulative operation, the address of the storage portion of N words is changed by one address, and (1) the received signal from the storage circuit and the tap coefficient are changed again. And (2) update the read tap coefficient and the received signal corresponding to the updated tap coefficient to the memory circuit, (3)
Repeated multiplication and accumulation of the updated tap coefficient and the received signal corresponding to the updated tap coefficient read from the storage circuit generate a pseudo echo, and cancel the echo by subtracting the pseudo echo from the signal including the echo. This is solved by the echo canceller of the present invention.

[Action]

 In the present invention, the calculation is performed by the following formula.

Here, (1) 'is obtained by substituting n-1 for n in the above formula (1).

Therefore, the old signal x _nN and the coefficient corresponding to the old signal x _nN are stored in the received signal storage portion and the coefficient storage portion of the storage circuit 20. And are read out, and K _n-1 · x _{nN is} calculated by the multiplication circuit in the arithmetic circuit 21.
After obtaining Was added to calculate and update equation (1) ′. Is supplied to the multiplication circuit and the coefficient storage section.

Then the multiplier circuit was formed Is used to perform the operation of the equation (2) 'for x _{n -N + 1,} and then the coefficient changing operation of the equation (1)' is performed again.

That is, the convolution operation and the coefficient update operation are alternately repeated in the arithmetic circuit. After obtaining, the equation (3) 'is further calculated to eliminate the echo signal y _n .

Further, K _n is calculated after executing the equation (3) ′.

With such an arithmetic method, the received signal and coefficient can be read and transferred only once, which improves the operating efficiency of the arithmetic circuit and reduces the operating speed of the memory circuit to half that of the conventional method.
I chose

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of FIG. 2. The symbols on the left side of FIG. 3 show the operations of the same symbols in FIG. In addition, the same symbols indicate the same objects throughout the drawings, and the conditions are the same as in the conventional example.

In addition, the reception signal storage portion 201, the coefficient storage portion 202, the register 20
3, 205 and selectors 204, 206 are multiplication circuits of the memory circuit 20.
13, adder / subtractor 14, accumulators 15, 18, output register
The 16, K calculation circuit 17 is a component of the arithmetic circuit 21.

The operation of FIG. 2 will be described below with reference to FIG. 3 with N = 512.

First, as described above, the present invention performs a coefficient update calculation. As a convolution operation By computing Ask for.

Therefore, the received signal corresponding to h ₅₁₁ when i = 511 is x _n-512 , as shown in the received signal storage portion 201 and the coefficient storage portion 202 in FIG. Since x _n-511 is written as one word corresponding to this, a register 203 is provided to write x _n-512, and when this is used and the signal of the received signal storage portion 201 is used. Therefore, the selector 204 driven by the control of an external control circuit (not shown) selects.

Also, as shown in Fig. 3- Since x and x _n-512 must be input to the multiplication circuit 13 at the same time, the latter is delayed by the register 205.

Now, x _n-512 read from the register 203 and the coefficient storage unit 202 The former and K _n-1 are multiplied by the multiplication circuit 13 and And are added by the adder / subtractor circuit 14 Is stored in the accumulator 18 by an erector (not shown) in the To To the multiplication circuit 13 as shown in FIG.
, And write address, write clock).

And updated The signal x _n-511 read from the received signal storage portion 201 is multiplied by the multiplication circuit 13. Is added by the addition / subtraction circuit 14 and stored in the accumulator 15,
It is added to the adder / subtractor circuit 14 (see Fig. 3,-, ...).

Next, the multiplication circuit 13 finds the multiplication of K _n-1 x ₅₁₁ , and And are added by the adder / subtractor circuit 14 Is stored in the accumulator 18, and the coefficient storage portion 202
of To And is added to the multiplication circuit 13. And And the read signal x _n-510 is multiplied by the multiplication circuit 13. Is added by the adder / subtractor circuit 14 and stored in the accumulator 15 and accumulated with the previous value. Is calculated.

To repeat this At the same time, the update of the coefficient is completed when is calculated. Therefore, And subtracting the echo signal y _n which is applied to the terminal SIN seeking residual echo signal e _n, then calculates the K _n repeats the above-described operation.

By performing such an operation, the arithmetic circuit can be used efficiently, and the memory circuit does not need to operate at high speed.

〔The invention's effect〕

As described in detail above, according to the present invention, since the convolution operation and the coefficient update operation are performed by reading the signal from the memory circuit once, the arithmetic circuit can be used efficiently and continuously, and at the same time, the memory circuit can be used. Has the effect of not requiring high speed operation.

[Brief description of drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an operation explanatory diagram of FIG. 2, and FIG. 4 is a line configuration example using an echo canceller, 5 is a block diagram of the echo canceller, FIG. 6 is an operation explanatory diagram of the convolution operation unit, FIG. 7 is a block diagram of a conventional example, and FIG. 8 is an operation explanatory diagram of FIG. In the figure, 13 is a multiplication circuit, 14 is an addition / subtraction circuit, 15 and 18 are accumulators, 16 is an output register, 17 is a K calculation circuit, 20 is a memory circuit, 21 is an arithmetic circuit, 203 and 205 are registers, and 204 and 206 are selectors. Indicates.

Claims (1)

[Claims] 1. An echo canceller for generating a pseudo echo by an adaptive filter calculation using a received signal (tap data) and a tap coefficient, and subtracting the pseudo echo from a signal including the echo to cancel the echo, and at 1 from time n. I-th tap coefficient at time (n-1) that is old by sample time (I = 0, 1, ... N-1 but N is a positive integer) and the received signal x _ni that is older than the time n by i sample times is set to 1
As a word, a storage part of N words for storing reception signals and tap coefficients for N taps, and a dedicated register part for storing a reception signal x _nN that is one sample time older than the oldest reception data in the N taps. a memory circuit having, an arithmetic circuit including a multiplier circuit and a subtraction circuit is provided, said operation circuit, the dedicated register portion from the received signal x _nN, the tap coefficients of the last from the storage portion Is read out, the last tap coefficient is updated using the read received signal and tap coefficient, and a new tap coefficient is obtained only for one sample time. And update tap coefficient And the received signal x _{n- (N-2)} at the next sample time is written to the storage portion, and at the same time, the content of the dedicated register portion is changed to x
Updated to _{n- (N-1)} and updated tap coefficient And the received signal x _{n- (N-1)} are multiplied to start the cumulative operation, the address of the storage portion of N words is changed by one address, and (1) the received signal from the storage circuit and the tap coefficient are changed again. (2) Update the read tap coefficient and the received signal corresponding to the updated tap coefficient in the memory circuit, and (3) Update the tap coefficient and the received signal corresponding to the updated tap coefficient read from the memory circuit. An echo canceller characterized in that it is configured to eliminate the echo by subtracting the pseudo echo from the signal containing the echo by repeatedly performing multiplication and accumulation with and.