JPH0669759A - Adaptive signal processor - Google Patents

Abstract

PURPOSE:To provide a new pipe line processor which can execute a high speed processing compared to a conventional case in an adaptive signal processing system used for a noise cancellor and an echo cancellor. CONSTITUTION:A memory circuit 4 storing a first input signal string, a counter circuit 7 setting the address of the circuit, a memory circuit 5 setting the initial value of a filter coefficient with respect to the first input signal string, a data holding circuit 14 holding output from the circuit 5, a multiplication circuit 1 multiplying the output of the holding circuit 14 and the output of the memory circuit 4, an addition circuit 2 adding the output of the multiplication circuit 1 with a second input signal, a selection circuit 10 switching the output of the data holding circuit 14 holding the output of the addition circuit and the output of the memory circuit 5, and outputting the signal as the second input signal, counter circuits 6 and 8 setting the address of the memory circuit 5 and a selection circuit 9 switching the outputs and supplying the output as the address of the memory circuit 5 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive signal processing apparatus, and more particularly to a system for calculating a filter coefficient for every fixed time period and performing signal processing using the coefficient.

[0002]

2. Description of the Related Art Conventional adaptive signal processing devices have been used in echo cancellers and noise cancellers for telephone lines and the like. An echo canceller using this adaptive signal processor adaptively estimates the frequency characteristics of the echo propagation path peculiar to the connected line as an impulse response of the time series, and creates a pseudo echo signal (pseudo echo) to generate an echo. It is subtracted from the signal, and the echo can be removed without attenuating the system like an echo suppressor, which enables a natural conversation. In addition, the noise canceller using the adaptive signal processing device has two signal input means,
When a noise-mixed voice signal and an observation signal containing only noise are given, noise can be removed from the noise-mixed signal to enhance the voice signal.

In a conventional adaptive signal processing device, a Widrow-Hoff LMS (Least-Me) for correcting a filter coefficient so as to minimize a mean square value of prediction errors.
An adaptive filter process based on the (an-Square) algorithm has been performed. First, an outline of this adaptive filter processing will be described.

The input signal sequence vector up to the present for the adaptive filter is S (k) = [s (k), s (k-1), s (k-2), ..., s (k-N + 1)] * T (1) and the filter coefficient vector is A (k) = [al (k), a2 (k), a3 (k) ..., aN (k)] T ... (2) The predicted value p (k-1) of the next input sample by the signal sequence is P (k + 1) = AT (k) S (k) (3) Further, the correction formula of the filter coefficient is A (k + 1) = A ( k) + K (k + 1) · e (k) (4) where e (k) is an error signal and the gain K is in the case of the LMS algorithm. K (k + 1) = S (k) (5) Practical To reduce the effect of transmission path error, (4)
The following formula is used instead of the formula. Here, w is a weighting coefficient between 0 and 1. A (k + 1) = w · A (k) + K (k + 1) · e (k) (6) FIG. 2 shows a signal flow diagram of such adaptive filtering. In the figure, 201 to 213 are multiplication processes, 22
0 to 226 are delay processes for delaying the input signal by a time corresponding to one sampling period, 203 to 236 are addition processes, and the same process as (C) is repeated in the part (c) shown by the broken line.

In the case of a noise canceller, the input signal S
(K) is an observed signal containing only noise, the predicted value p (k + 1) of the next input sample is the estimated value of noise, and the error signal e (k) is the difference between the speech signal containing noise and the estimated value of noise. To do.

Next, a conventional adaptive signal processing apparatus for executing this adaptive filter processing will be described with reference to the block diagram of FIG.

The multiplier 1 executes 16-bit × 16-bit multiplication in one instruction cycle (hereinafter referred to as one step) and outputs the multiplication result in 31 bits. The adder 2 outputs 31-bit two inputs in one step. to add. The accumulator 3 is a 31-bit accumulator that holds the output of the adder 2, the data RAM 4 and the coefficient RAM 5 each have 256 words × 6 bits of RAM, and the data RAM pointer (hereinafter referred to as DP) 7 specifies the address of the data RAM 4 8 The bit pointer and coefficient RAM pointer (hereinafter referred to as CP) 8 is an 8-bit pointer that specifies the address of the coefficient RAM 5. The multiplexer 10 selectively outputs one of the two inputs, and the data bus 20 is an internal data bus having a 16-bit width.

When the LMS algorithm is executed by the adaptive signal processor of FIG. 3, the predicted value p of the next input sample is p.
The formula (3) for obtaining (k + 1) can be executed by the process of one step per tap, but the correction formula (4) of the filter coefficient requires the process of four steps per tap.

Details of the processing of each step relating to the correction of the filter coefficient are as follows. (1) The coefficient ai (k) is loaded from the coefficient RAM 5 into the accumulator 33 via the internal data bus 20, the multiplexer 10 and the adder 2. (2) The multiplication of the second term of Expression (4) (S (k-i + 1) · e (k) in the case of the LMS algorithm) is performed. The data S (k-i + 1) is input from the data RAM 4 to one input latch of the multiplier 1 via the internal data bus 20.
The data e (k) may be latched in advance in one input latch of the multiplier, and need not be updated every time each tap is processed. (3) The first term and the second term of the equation (4) are added. The addition result is stored in the accumulator 33. The internal data bus 20 is not driven in this step. (4) The new coefficient ai (k + 1) is stored in the coefficient RAM 5 from the accumulator 33 via the internal data bus 20.

Therefore, the adaptive signal processing device shown in FIG. 3 requires processing of 5 steps per tap. As described above, the conventional adaptive signal processing device needs to process a large number of steps per tap of the adaptive filter of the LMS algorithm.

On the other hand, a practical adaptive filter system requires a very large number of taps. For example, in the case of an echo canceller, considering the transmission delay in the domestic communication network in Japan, the impulse response sequence covering the echo delay amount is 50
About 60 ms is required, and it is necessary to configure an adaptive filter with 400 to 500 taps. Further, in the case of controlling the sound field of an in-vehicle audio system, an impulse response sequence covering about 25 ms is required to cover the reflection delay time when the reflected sound or reverberant sound (higher-order reflected sound) in the acoustic space inside the car is considered. Therefore, it is necessary to configure a filter with about 1200 taps for 48 kHz sampling.

When the one-step execution time of FIG. 3 is 100 ns and one sampling period is 0.02 ms, the number of taps that can be executed in one sampling period is 40 taps. When the required number of taps of the adaptive filter is 1000, 25 adaptive signal processing devices of FIG. 3 had to be prepared.

[0013]

As described above, in the conventional adaptive signal processing device, an enormous amount of hardware is required to configure the adaptive filter. This is because the adaptive filter requires a very large number of taps,
Also, it is necessary to process a large number of steps per tap of the adaptive filter.

On the other hand, the sampling frequency is 8 kHz for telephone lines and 48 kHz or 4 for audio systems.
It is 4.1 kHz or the like, and it is necessary to execute the above-described filter processing with a huge number of taps during this sampling cycle.
Since a large number of step processes are performed to realize the process per tap, a huge amount of hardware is required.

The object of the present invention is to solve these problems,
An object of the present invention is to provide an adaptive signal processing device that can realize processing per tap of an adaptive filter with a very small number of steps.

[0016]

The adaptive signal processing apparatus according to the present invention has a first memory circuit for storing a first input signal sequence and a first memory circuit for setting an address of the first memory circuit. A counter circuit, a second memory circuit for setting an initial value of a filter coefficient for the first input signal sequence, a first data holding circuit for holding an output of the second memory circuit, and a first data holding circuit for holding the output of the second memory circuit. A multiplication circuit that multiplies the output of the data holding circuit and the output of the first memory circuit, an addition circuit that adds the output of this multiplication circuit and the second input signal, and the output of this addition circuit. A second data holding circuit; a first selection circuit for switching between the output of the second data holding circuit and the output of the second memory circuit for outputting as the second input signal; Setting the address of the memory circuit A third counter circuit, these second, characterized in that it comprises a second selection circuit for supplying as an address of the second memory circuit switching the output of the third counter circuit.

[0017]

1 is a block diagram showing a system according to an embodiment of the present invention. Since the present embodiment has a configuration in which the processing for one tap of the above-mentioned equation (4) for correcting the coefficient of the adaptive filter can be executed in one step, the following points are different from the conventional adaptive signal processing apparatus. ing.

(A) Coefficient RAM 5 to internal data bus 2
It has a path for directly transferring data to one input of the adder 2 without going through 0. (B) It has a path for directly transferring data from the output of the accumulator 3 to the coefficient RAM 5 without passing through the internal data bus. (C) Utilizing the fact that the access time of the coefficient RAM 5 is shorter than the operation time such as multiplication, data writing to the coefficient RAM 5 is executed in the first half of one instruction cycle, and data reading from the coefficient RAM 5 is executed in the latter half. Alternatively, the data is read from the coefficient RAM 5 in the first half of one instruction cycle, and the data is written in the coefficient RAM in the second half. (D) A write address counter 6 and a read address counter 8 of the coefficient RAM 5 are provided and are alternately selected and used.

In this embodiment, these (a), (b),
(C) makes it possible to modify the filter coefficient of the LMS algorithm in one step per tap, and (d) absorbs the address shift when the filter coefficient modification process is pipelined. Is possible.

In FIG. 1, the multiplier 1 is 16 bits × 1.
The 6-bit multiplication is executed in one step and the multiplication result is output in 31 bits, the adder 2 adds the 31-bit two inputs in one step, and the accumulator 3 holds the output of the adder 2 in the 31-bit accumulator. Is. Data RA
M4 and coefficient RAM5 are 256 words × 16 bits of RAM. The data RAM pointer 7 is an 8-bit pointer for designating the address of the data RAM 4, and the coefficient RAM pointers 6 and 8 are 8 for designating the address of the coefficient RAM 5, respectively.
It is a bit pointer.

The data buses 20 and 22 are 16-bit wide data buses, buses 21, 23 and 24 and buses 50, 51 and 5.
Reference numeral 2 is an 8-bit wide data bus, buses 16 to 33 are 16-bit wide data buses, and buses 40 to 43 are 31-bit wide data buses. The multiplexer 9 selectively outputs one of the two inputs of CP6 and 8, and the data latch 11 temporarily holds the input 16-bit data,
The multiplexer 12 selects and outputs one 16-bit data of the two inputs of the buses 20 and 26. The demultiplexer 13 outputs the upper 16 bits of the input 31-bit data to one of the two outputs.

When the selection signal 100 is at high level, the data RA
When M4 is selected and the R / W control signal 101 is at the low level, the data RAM 4 is in the read state and when it is at the high level, the data RA
Set M4 to the write state. The selection signal 102 selects the coefficient RAM 5 at a low level, and the clock signal 103 is a clock signal that determines one step cycle of calculation (multiplication or addition), and is one step cycle from the falling edge of a clock pulse to the falling edge of the next clock pulse. Becomes The clock signal 103 is also used as an R / W control signal for the coefficient RAM 5, and sets the coefficient RAM 5 to a read state at a high level and a write state at a low level. That is, the control signal 10
When 6 is high level, coefficient RAM 5 is in the selected state 1
The writing state is set in the first half of the step cycle, and the reading state is set in the second half. When the control signal 106 is at the low level, the coefficient RAM 5 is in the non-selected state in the first half of the one-step cycle and in the selective read state in the second half.

The data latch 11 latches the read data of the coefficient RAM 5 at the falling edge of the clock signal 103. F
The / R control signal 107 is at a low level during calculation of the predicted value p (k + 1) of the input sample corresponding to the expression (3), and is at a high level during the correction processing of the filter coefficient corresponding to the expression (4). It is a control signal.

The drive control signal 109 indicates whether the output of the demultiplexer 13 is on the bus 33 side in the drive state or in the high impedance state, and becomes high impedance when the drive control signal 109 is low level. The selection signal 110 is a selection signal that selects the data bus 20 as an input of the multiplexer 12 at a low level and selects the bus 26 at a high level. Data latch 1
When the control signal 130 is at the low level, 31 outputs the data on the bus 31 to the bus 32 as it is, and when the control signal 130 is at the high level, it latches and outputs the data on the bus 31 at the rising time of the control signal 130.

The operation of this embodiment will be described below. First, as the initial setting before the filter processing, the initial value of the adaptive filter coefficient is set in the coefficient RAM 5 via the data bus 20. This processing is executed by setting the selection signal 106 to high level, the F / R control signal 107 to high level, the selection signal 110 to low level, and the drive control signal 109 to low level.

In this case, the coefficient RAM 5 is connected to the data bus 20.
Data is written through the coefficient RAM 5
Is output on the bus 31, but since the drive control signal 109 is at the low level, it does not affect the initial setting operation. The above process is executed in advance separately from the adaptive filter process executed every sampling cycle. next,
The processing executed in each sampling cycle will be described.

First, the current input sample value corresponding to s (k) in the equation (1) is written in the data RAM 4. Next, the predicted value p of the input sample corresponding to the above equation (3)
Calculate (k + 1). This calculation process is performed by the selection signal 106.
Is set to a low level, the F / R control signal 107 is set to a low level, and the control signal 130 is set to a low level. In this case, the data of coefficient RMA5 is data bus 3
1, 32, and the data latch 14 to the multiplier 1. On the other hand, the data in the data RAM 4 is also transferred to the data bus 20.
Is input to the multiplier 1 via.

The multiplication result of the multiplier 1 is input to the adder 2 after one step. The multiplexer 10 is the bus 42
Since the data of 1 is output to the bus 43, the above multiplication result is further added to the contents of the accumulator, and the addition result is stored in the accumulator. By repeating the above processing, the predicted value p (k + 1) of the input sample is calculated. Here, since the multiplication and the addition one tap before are performed in the same step, the calculation process of the prediction value p (k + 1) is executed in one step per tap. p
When (k + 1) is obtained, the drive control signal 109 becomes high level, and the predicted value p (k + 1) is output from the accumulator to the data bus 20.

Next, the process for one tap of the correction process of the filter coefficient corresponding to the equation (4) will be described. This processing is executed by setting the selection signal 106 to the high level, the F / R control signal 107 to the high level, the control signal 130 to the high level, the selection signal 110 to the high level, and the drive control signal 109 to the low level.

The processing for one tap is executed in three steps. The processing in each step is as follows: (1) The coefficient ai (k) is transferred from the coefficient RAM 5 to one input of the adder 2 via the bus 31 and the bus 43, and the second equation (4) Multiplication of terms S (k-i) · e (k)
I do. This multiplication converts the data S (k-i) into the data RA.
It is executed by inputting from M4 to one input latch of the multiplier 1 via the data bus 20. Data e
(K) is latched in the data latch 14 in advance. (2) The result S (k−i + 1) · e (k) of the multiplication executed in the same manner as (1) one step before and (1) one step before
Similarly to, the coefficient ai-1 (k) transferred to the adder 2 is added. The addition result is stored in the accumulator 3. (3) New coefficient ai (k +) stored in the accumulator
1) is the next step from the accumulator 3 to the bus 26,
It is written to the coefficient RAM 5 via 27.

Here, the timing of reading the coefficient ai (k) differs from the timing of writing the new coefficient ai (k + 1) by two steps, but the write address input to the coefficient RAM 5 via the bus 52 is two steps before. By setting CP6 and CP8 so as to be the same as the read address of the coefficient RAM 5, the addresses before and after the update can be made the same.

As described above, the coefficient correction process for the same tap requires three steps, but regarding the i-th tap (1)
The process (1), the process (2) for the i−1th tap, and the process (3) for the i−2nd tap are pipelined during the same step.

As described above, the conventional adaptive signal processing apparatus has five steps for processing one tap of the adaptive filter, but the adaptive signal processing apparatus of the present embodiment can execute the processing in two steps per tap. Become.

In the present embodiment, the bus width of the bus, the multiplier,
The bit configuration of the adder or the like, the sampling period, etc. are not limited to the bus width of the data bus, the bit configuration of the multiplier, the adder, etc., the sampling period, etc. described above, and can be realized by other suitable configurations.

As a second embodiment, the clock signal 103
Is inverted by an inverter, and the inverted clock is RA
It can also be connected to M5, the data latch 11, and the like. Therefore, when the control signal 106 is at the high level, the coefficient RAM 5
Becomes the selected state and the read state is made in the first half of one step cycle.
In the latter half, it becomes the writing state. The data latch 11 latches the read data of the coefficient RAM 5 at the rising edge of the inverted clock signal 103.

In this embodiment, the order of reading and writing from and to the coefficient RAM 5 is different from that of the above-described embodiment, but even with such a configuration, the processing for one tap is performed in two steps as in the first embodiment. It is clear that it can be done.

[0037]

As described above, according to the present invention,
In the conventional adaptive signal processing device, processing of 5 steps is required for each tap of the adaptive filter of the LMS algorithm, but one tap can be executed in 2 steps.
Since an actual adaptive filter system is configured with a very large number of taps, it requires a huge amount of hardware. However, by using the adaptive signal processing device of the present invention, processing steps required for each tap are increased. The number is 2 /
It is possible to reduce the number to 5, which makes it possible to significantly reduce the amount of hardware.

For example, when constructing a basic noise canceller in an acoustic space in an automobile, a filter of about 1200 taps is required for 48 kHz sampling, and the conventional adaptive signal processing apparatus shown in FIG. If one step execution time is 100ns, this basic noise
In order to configure the canceller, an adaptive signal processing device 29
It was necessary to make a table.

On the other hand, in the case of the adaptive signal processing device of the present invention, even if the one-step execution time is the same, it is possible to obtain one with 12 units.
A 200-tap noise canceller can be constructed. As described above, the present invention can provide an adaptive signal processing device capable of realizing the processing per tap of the adaptive filter with a very small number of steps, and therefore, the hardware amount can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 2 is a signal flow diagram of adaptive filtering.

FIG. 3 is a block diagram showing a configuration example of an example of a system of a conventional adaptive signal processing device.

[Explanation of Codes] 1 Multiplier 2 Adder 3 Accumulator 4 Data RAM 5 Coefficient RAM 7 Data RAM Pointer 6, 8 Coefficient RAM Pointer 9, 10, 12 Multiplexer 11, 14 Data Latch 13 Demultiplexer 19 NOR Circuit 20 Internal Data Bus 21-33, 40-43, 50-52 Bus 201-213 Multiplication process 220-226 Delay process 230-236 Addition process

Claims (4)

[Claims] 1. A first memory circuit for storing a first input signal sequence, a first counter circuit for setting an address of the first memory circuit, and a filter coefficient for the first input signal sequence. A second memory circuit for setting an initial value,
A first data holding circuit for holding the output of the second memory circuit, an output of the first data holding circuit and the first data holding circuit
Of the memory circuit, an addition circuit for adding the output of the multiplication circuit and the second input signal, a second data holding circuit for holding the output of the addition circuit, A first selection circuit for switching between the output of the second data holding circuit and the output of the second memory circuit for output as the second input signal, and a second setting circuit for setting the address of the second memory circuit. , An adaptive signal processing device comprising: a third counter circuit; and a second selection circuit for switching the outputs of the second and third counter circuits and supplying it as an address of the second memory circuit. 2. The adaptive signal processing device according to claim 1, wherein the first, second, and third counter circuits are circuits that update an address value held at each predetermined time period. 3. The adaptive signal according to claim 1, wherein the second memory circuit operates so as to be in a write state in a first half of a predetermined time period and in a read state in a second half thereof, or vice versa. Processing equipment. 4. The second selection circuit comprises a circuit which selectively outputs the output of the second counter circuit in the first half of the predetermined time period and selectively outputs the output of the third counter circuit in the latter half thereof. Alternatively, the adaptive signal processing device according to item 2.