JPH04160811A - Adaptive signal processing unit - Google Patents

Abstract

PURPOSE:To save the quantity of hardware by selecting whether an output value of a sum latch circuit as a newest filter coefficient is outputted to a 2nd or 3rd storage circuit or a data bus. CONSTITUTION:A selection signal S4 is set to a high level, an F/R control signal FR1 is set to a low level and a latch control signal L1 is set to a high level. In this case, a data of a coefficient RAM 5 is inputted to a multiplier 1 via a data bus 31. On the other hand, a data of a data RAM 4 is inputted to the multiplier 1 is a data bus 20, the result of multiplication is inputted to an adder 2 after one step. A multiplexer 10 outputs data of a bus 42 outputted from an accumulator 3 to a bus 43 and inputted to an adder 2, then the result of multiplication is added to the content of the accumulator 3 and the result of addition is stored further in the accumulator 3. Thus, the calculation processing of a predicted value P(k+1) is executed by one step per tap. Thus, the quantity of hardware is considerably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adaptive signal processing device, and more particularly to an adaptive signal processing device used in an echo canceller of a communication line or the like.

[Conventional technology]

Adaptive signal processing devices were used in echo cancellers and noise cancellers for telephone lines, etc.

An echo canceller using an adaptive signal processing device adaptively estimates the frequency characteristics of the F-propagation path unique to the connected line as a time series impulse response, creates a pseudo echo signal (pseudo echo), and cancels the echo signal. Unlike echo suppressors, echoes can be removed without attenuating the system, allowing for natural conversation.

In addition, a noise canceller using an adaptive signal processing device removes noise from the noise-containing signal and enhances the voice signal when a noise-containing voice signal and a noise-only observation signal are given using two signal input means. This makes it possible.

In conventional adaptive signal processing devices, Widrow-Hof's LMS (L
Adaptive filter processing based on the East-Mean-Square (east-Mean-Square) algorithm has been performed.

First, an overview of this adaptive filter processing will be explained.

The input signal sequence vector for the adaptive filter up to now is 5(k)=[5(k), 5(k-1), 5(k-2),
-, 5(k-N+1)] IT=(1), and the filter coefficient vector is A(k)=[al(k), a2(k), a3(k), -
, aN(k)IT - (2), then the predicted value of the next input sample based on the input signal sequence up to the present 1)(k+
1) is expressed by the following formula.

p(k+1): AT(k)・5(k)
-.(3) Also, the modification formula for the filter coefficient is expressed by the following formula.

A(k+1): A(k)+K(k+1)・e(k)
= (4) where e (k) is an error signal, and the gain is expressed by the following equation in the case of the LMS algorithm.

K(k+1)=S(k)
--(5) Practically, the following equation is used instead of equation (4) in order to reduce the influence of transmission path errors.

A(k+1): W-A(k)+(k+1)-e(k)(
0kuwkul)
-.(6) Here, W is a weighting coefficient.

FIG. 2 shows the signal processing flow of the adaptive filter processing described above.

In FIG. 2, steps 201 to 213 are multiplication processes, steps 220 to 226 are delay processes that delay the input signal by a time corresponding to one sampling period, and step 23
0 to 236 are addition processes, and in the part (C) indicated by a broken line, the same process as in (C) is repeated.

In the case of a noise canceller, the input signal S (k) is an observed signal with only noise, and the predicted value p (k+
1) corresponds to the estimated value of noise, and the miscalculation signal e(k) corresponds to the difference between the speech signal mixed with noise and the estimated value of noise.

Next, the configuration and operation of a conventional adaptive signal processing device that performs the above-mentioned adaptive filter processing will be described.

FIG. 6 is a block diagram showing an example of a conventional adaptive signal processing device.

In FIG. 6, the conventional adaptive signal processing device includes a multiplier 1 that executes 16 bits by 1B bits in one instruction cycle (hereinafter referred to as one step) and outputs the multiplication result in 31 bits; An adder 2 that adds two human forces in one step, a 31-bit accumulator 3 that holds the output of the adder 2, and a data RAM 4.
256 words x 16 bits coefficient RAM5 and data R
A data RAM pointer (hereinafter referred to as DP) 7, which is an 8-bit pointer that specifies the address of AM4, and a coefficient R.
It consists of a coefficient RAM pointer (hereinafter referred to as CP) 8, which is an 8-bit sotopointer that specifies the address of AM5, a multiplexer 9 that selects and outputs one of the two inputs, and an internal data bus 20 with a 16-bit width. Ta.

When the LMS algorithm is executed by the conventional adaptive signal processing device shown in Fig. 3, the predicted value p(k+1
) can be realized by processing one step per tap, but the filter coefficient correction formula (4
) requires four steps of processing per tap.

Details of the processing of each step regarding modification of filter coefficients are as follows.

In the first step, the coefficient ai(k) is loaded from the coefficient RAM 5 to the accumulator 3 via the internal data bus 20, multiplexer 9, and adder 2.

In the second step, the second term of equation (4) is multiplied (5(ki+1)·e(k) in the case of the LMS algorithm). Data 5 (k-i+1) is input from the data RAM 4 to one input latch of the multiplier 1 via the internal data bus 20. The data e(k) can be latched in advance in one input latch of the multiplier, and does not need to be updated every time the data is processed.

In the third step, the first term and the second term of equation (4) are added. The addition result is stored in accumulator 3. In this step, the internal data bus 20 is not driven.

In the fourth step, the new coefficient ai(k+1) is stored from the accumulator 3 into the coefficient RAM 5 via the internal data bus 20.

Therefore, the conventional adaptive signal processing device shown in FIG. 5 requires five steps of processing per tap.

On the other hand, an actual adaptive filter system requires a very large number of taps.

For example, in the case of an echo canceller, considering the transmission delay in Japan's domestic communication network, the impulse response sequence that covers the echo delay amount needs to be about 50 to 60 ms, which is 40 ms.
It was necessary to construct an adaptive filter with a range of 0 to 500 points.

In addition, in the case of sound field control such as in-vehicle audio, an impulse response series of about 25 m5 is required to cover the reflection delay time when considering reflected sound and reverberation sound (higher-order reflected sound) in the acoustic space inside the car. Therefore, it is necessary to configure a filter with about 1200 taps for 48 kHz sampling.

[Problem to be solved by the invention]

The above-described conventional adaptive signal processing apparatus has a drawback in that a large number of steps are required per tap for adaptive filter processing of the LMS algorithm.

Furthermore, since an actual adaptive filter system requires a very large number of taps, there is a drawback that an enormous amount of hardware is required to configure the adaptive filter.

For example, if one step execution time of the conventional adaptive signal processing device shown in FIG. 5 is 100 nS and one sampling period is 0.02 m5, the number of taps that can be executed during one sampling period is 40 taps. Therefore, if the number of taps required for the adaptive filter is 1000, then 2
It was necessary to operate five adaptive signal processing devices in parallel.

[Means to solve the problem]

The adaptive signal processing device of the present invention is based on a minimization mean square value algorithm that corrects filter coefficients at each predetermined sampling period, and combines sample values of input data with the filter coefficients corrected at each period. a multiplier circuit that performs multiplication, an adder circuit that receives the output value of the multiplier circuit, an added value holding circuit that holds the added output value of the adder circuit, and a sample value of the input data for each cycle that is stored. a first storage circuit that alternately stores the latest value of the filter coefficient for each cycle; and one of the output data of the second or third storage circuit. a second selection circuit that switches between the output value of the first selection circuit and the output value of the added value holding circuit and inputs the output value of the added value holding circuit to the adding circuit; and a third selection circuit for switching whether to output the latest value of the filter coefficient to the second or third storage circuit' or to the data bus.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, the adaptive signal processing device of the present invention has the same components as the conventional example described above, and performs multiplication of 16 bits x 16 bits in one instruction cycle (hereinafter referred to as one step). A multiplier 1 that outputs the result in 31 bits, an adder 2 that adds two 31-bit inputs in one step, a 31-bit accumulator 3 that holds the output of the adder 2, a data RAM 4, and 256 words x A 16-bit coefficient RAM5 and a data RAM which is an 8-bit pointer that specifies the address of data RAM4.
A pointer (hereinafter referred to as DP) 7, a coefficient RAM pointer (hereinafter referred to as CP) 8 which is an 8-bit pointer that specifies the address of the coefficient RAM 5, a multiplexer 9 that selects and outputs one of the two, and a 16-bit wide pointer (hereinafter referred to as CP) 8. In addition to the internal data bus 20, it consists of the following:

That is, multiplexer 1 similar to multiplexer 9
0, a data latch 11 that temporarily holds the input 16-bit data, a multiplexer 12 that selects one of the two 16-bit data and outputs it to both outputs, and the upper 16 bits of the input 31-bit data. a demultiplexer 13 that outputs the data to one of two outputs, a selection circuit 15, and buses 21 to 16 which are 16-bit wide data buses.
33, and buses 40-43, which are 31-bit wide data buses.
has been added.

The selection circuit 15 inputs a selection signal S4 and an F/R selection signal FRI, which will be described later, and outputs a selection signal S3 and an R/W control signal RW3.
This is a logic circuit that outputs .

FIG. 4 shows a truth table of the selection circuit 15.

Next, types of signals and their functions in this embodiment will be explained.

The selection signal S1 is a control signal that selects the data RAM 4 at a high level.

The selection signal S2 is a high level control signal for selecting the coefficient RAM5.

The R/W control signal RWI is low level and the data RAM 4
This is a control signal that puts the data RAM 4 in the read state and puts the data RAM 4 in the write state at high level.

The R/W control signal RW2 is a control signal that puts the coefficient RAM 5 in a read state when it is at a low level, and puts the coefficient RAM 5 into a write state when it is at a high level.

The selection signal S3 is a control signal that selects the coefficient RAM 6 at a high level.

The R/W control signal RW3 is a control signal that puts the coefficient RAM 6 in a read state when it is at a low level, and puts the coefficient RAM 6 into a write state when it is at a high level.

The selection signal S4 is a control signal whose level is inverted every sampling period.

The F/R control signal FRI is at a low level while calculating the predicted value 1) (k+1) of the input sample corresponding to the above-mentioned equation (3), and is in the process of correcting the filter coefficients corresponding to the above-mentioned equation (4). is a control signal that becomes high level.

The latch control signal L1 is a control signal that specifies the latch timing of the data latch 11. During the high level, the input data is output as is, the input data is latched at the falling edge, and the latch result is output during the low level period. do.

The drive control signal D1 is a control signal that instructs whether the bus 33 side of the output of the demultiplexer 13 is to be in a drive state or a high impedance state, and becomes high impedance when the drive control signal D1 is at a low level.

The selection signal S5 selects the data bus 20 as the input of the multiplexer 12 when it is at a low level, and selects the data bus 20 as the input of the multiplexer 12 when it is at a high level.
This is a selection signal for selecting. Selected data is on bus 2
7.28.

Next, the operation of this embodiment will be explained based on the above description of the adaptive signal processing operation.

First, as an initial setting before filter processing, initial values of adaptive filter coefficients are set in the coefficient RAM 5 via the data bus 20.

This process is executed by setting the selection signal S4 to a low level, the F/R control signal FRI to a high level, the selection signal S5 to a low level, and the drive control signal D1 to a low level.

In this case, data is written to the coefficient RAM 5 via the data bus 20, and the contents of the coefficient RAM 6 are output onto the bus 31, but since the drive control signal D1 is at a low level, there is no effect on the initial setting operation. do not have.

The above processing is performed in advance, separately from the adaptive filter processing that is performed every sampling period.

Next, a description will be given of the processing executed at each sampling period.

First, the current input sample value corresponding to s (k) in the above-mentioned equation (1) is written into the data RAM 4.

Next, a predicted value p(k+1) of the input sample corresponding to the above-mentioned equation (3) is calculated.

This calculation process is executed by setting the selection signal S4 to high level, the F/R control signal FRI to low level, and the latch control signal L1 to high level.

In this case, data in the coefficient RAM 5 is input to the multiplier 1 via the data bus 31. On the other hand, data in the data RAM 4 is also input to the multiplier 1 via the data bus 20.

The multiplication result is input to adder 2 after one step.

Since the multiplexer 10 outputs the data on the bus 42 output from the accumulator 3 to the bus 43 and inputs it to the adder 2, the above-mentioned multiplication result is further added to the contents of the accumulator 3, and the addition result is further added as follows. It is stored in accumulator 3.

By repeating the above process, the predicted value p(k+1) of the input sample is calculated.

Here, since the multiplication and the addition one tap before are performed in the same step, the calculation process of the predicted value P(k+1) is
It will be executed with one step per tap.

When the predicted value P(k+1) is determined, the drive control signal DI becomes high level, and the predicted value P(k+1) is outputted from the accumulator 3 to the data bus 20.

Next, the processing for one tap in the filter coefficient correction processing corresponding to equation (4) will be explained.

This process is executed by setting the selection signal S4 to high level, the F/R control signal FRI to high level, the latch control signal L1 to low level, the selection signal S5 to high level, and the drive control signal D1 to low level.

Processing for one tap is executed over three steps. The processing in each step is as follows.

In the first step, the coefficient ai(k) is transferred from the coefficient RAM 5 to one input of the adder 2 via the bus 31 and the bus 43, and the second multiplication 5(ki)·e of equation (4) is performed.
Do (k). This multiplication is executed by inputting data 5(k-i) from the data RAM 4 to one large latch of the multiplier 1 via the data bus 20. Note that the data e(k) is latched in the data latch 11 in advance at the beginning of the sampling period.

In the second step, the result of multiplication performed in the same way as in (1) above is 5(k-j+1)・e(k) one step before and transferred to adder 2 in the same way as in (1) above. coefficient a
Addition with i-1(k) is performed.

The addition result is stored in the accumulator 3.

In the third step, the new coefficient ai(k+1) stored in the accumulator 3 is written from the accumulator 3 to the coefficient RAM 6 via the bus 26 in the next step.

Here, the timing to read the coefficient ai(k) and the new coefficient ai
The timing for writing (k+1) differs by two steps, and since there is one CP for two coefficient RAMs, the addresses of the coefficients differ by two addresses before and after the update.

In this way, the coefficient correction processing for the same tap requires three steps, or the processing in the first step for the first tap, the second step for the i-1th tap, and the processing for the l-2nd tap. The processing in the third step regarding taps is performed in a pipeline manner during the same step.

Similar processing is performed in the next sampling period, but the coefficient RAM 5 and the integer RAM 6 are used in reverse.

Selection of coefficient RAM5 and coefficient RAME3 is performed by selection signal S4 and F/R control signal FRI as shown in FIG.

As explained above, in the conventional adaptive signal processing device, processing for one tap of the adaptive filter requires five steps, but in the adaptive signal processing device of this embodiment, processing can be performed in two steps per tap.

The bus width of the bus, the bit configuration of multipliers, adders, etc., sampling period, etc. described in this embodiment are limited to the bus width of the data bus, the bit configuration of multipliers, adders, etc., sampling period, etc. described above. Needless to say, this can be realized by other suitable configurations without any additional configuration.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a system configuration diagram of a second embodiment of the present invention.

In FIG. 4, 8 specifies the address of coefficient RAM 5.
The configuration is the same as that of the first embodiment described above, except for a coefficient RAM pointer (hereinafter referred to as CP) 17, which is a bit pointer, an 8-bit pointer 16 that specifies the address of the coefficient RAM 8, and a bus connected thereto.

Here, since CPs are prepared for each of the two coefficient RAMs, the timing of reading out the coefficient ai(k) and the new coefficient a
Even if the timing of writing t(k+1) differs by two steps, the address of the coefficient can be made the same before and after the update.

It goes without saying that the bit configuration of the pointer described in the second embodiment is not limited to 8 bits, and can be realized by other suitable configurations.

Next, a third embodiment of the present invention will be described.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

In FIG. 5, the configuration is the same as that of the first embodiment described above, except that a shifter 18 and a selection circuit 19 are added to the output side of the coefficient RAM pointer 8 that specifies the address of the coefficient RAM 5.6. .

The shifter 18 shifts the 8-bit output data of the coefficient RAM pointer 8 by two steps for each data process.

The selection circuit 19 is controlled by an R/W control signal RW3 that controls writing and reading of the coefficient RAME3.
The output data of the pointer 8 and the output data of the thick 18 are switched and input to the coefficient RAM 5 or the coefficient RAM 6, respectively.

That is, when the R/W control signal RW3 is at a low level, the output data of the coefficient RAM pointer 8 is input to the coefficient RAM 6, and the output data of the shifter 18 is input to the coefficient RA.
Enter into M5.

Conversely, when the R/W control signal RW3 is at a high level, the output data of the coefficient RAM pointer 8 is input to the coefficient RAM 5, and the output data of the shifter 18 is input to the coefficient RAM 6.
Enter.

As mentioned above, in the filter coefficient correction process, the timing of reading the coefficient ai(k) and the timing of reading the new coefficient ai(k+1
) is different by two steps from the writing timing, but due to the shifter 18 and the selection circuit 19, the write address input to the coefficient RAM 6 becomes the same as the read address of the coefficient RAM 5 two steps before.

Therefore, the difference from the first or second embodiment described above is that the address does not change before and after the update.

Also, instead of the R/W control signal RW3, the coefficient RAM5.
It is clear that even if the selection signal S4 for controlling the multiplexer 9 which switches the output of 6 is used, the same operation will be obtained, and the present invention can of course be applied as long as it does not depart from the gist of the present invention.

〔Effect of the invention〕

As described above, the present invention has the advantage that adaptive filter processing for one tap, which conventionally required five steps, can be executed in two steps, that is, in 215 steps as in the conventional method.

Therefore, there is an effect that the amount of hardware can be significantly reduced.

For example, the conventional adaptive signal processing device shown in FIG. 6 has one step execution time of 100 nS and one sampling period of 0.
．． 02m5. If the number of taps required for the adaptive filter was 1000, it would be necessary to operate 25 adaptive signal processing devices in parallel, but with the adaptive signal processing device of the present invention,
Even if the execution time for one step is the same, there is an effect that it can be reduced to 10 parallel operations.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is a signal flowchart of adaptive filter processing, the third
4 is a block diagram showing the second embodiment of the present invention, FIG. 5 is a block diagram showing the third embodiment of the present invention, and FIG. 6 is a diagram showing the truth table of the selection circuit. FIG. 1 is a block diagram showing an example of a conventional adaptive signal processing device. 1... Multiplier, 2... Adder, 3... Accumulator, 4... Data RAM, 5.6... Coefficient RA
M, 7...Data RAM pointer, 8, 16.17.
...Coefficient RAM pointer, 9, 10.12...Multiplexer, 11...-Data latch, 15.19...
Selection circuit, 18... Shifter, 20... Internal data bus, 21-33. 40-43... Bus.

Claims (1)

[Claims] 1. Based on a minimizing mean square value algorithm that corrects filter coefficients at every predetermined sampling period,
a multiplier circuit that multiplies a sample value of input data by the filter coefficient modified for each cycle; an adder circuit that receives the output value of the multiplier circuit; and an adder that holds the added output value of the adder circuit. a value holding circuit; a first storage circuit that stores sample values of the input data for each cycle; second and third storage circuits that alternately store the latest values of the filter coefficients for each cycle; a first selection circuit that selects one of the output data of the second or third storage circuit; and a first selection circuit that switches the output value of the first selection circuit and the output value of the added value holding circuit and inputs it to the addition circuit. a second selection circuit; and a third selection circuit that switches whether to output the output value of the added value holding circuit to the second or third storage circuit or to the data bus as the latest value of the filter coefficient. An adaptive signal processing device comprising: 2. The adaptive signal processing device according to claim 1, wherein the first, second, and third storage circuits are RAMs whose write/read is controlled by a write/read control signal and addressed by an address pointer. 3. The second memory circuit is controlled to be in a read state when the third memory circuit is in a write state, and the third memory circuit is controlled to be in a read state when the second memory circuit is in a write state. The adaptive signal processing device according to claim 1 or 2, characterized in that: 4. The adaptive signal processing device according to claim 2, wherein the second and third storage circuits have the common address pointer for addressing. 5. The adaptive signal processing device according to claim 2, wherein the second and third storage circuits each have a dedicated address pointer for addressing. 6. The second and third storage circuits include the common address pointer for addressing, a shift circuit that shifts the output data of the address pointer by two steps for each data process, and the output data of the address pointer. 5. The adaptive signal processing device according to claim 4, further comprising a fourth selection circuit that switches and inputs the output data of the shift circuit to the second and third storage circuits, respectively. 7. The adaptive signal processing device according to claim 4, wherein the fourth selection circuit is controlled by a write/read control signal of the second storage circuit. 8. Claim 4, wherein the fourth selection circuit is controlled by a control signal that controls the first selection circuit.
The adaptive signal processing device described.