JPH06112854A - Adaptive signal processing unit - Google Patents

Abstract

PURPOSE:To revise flexibly an algorithm for calculating a filter coefficient and to reduce the cost by improving a processing efficiency of the adaptive signal processing unit comprising a DSP. CONSTITUTION:A processing unit is provided with a DSP 1 implementing adaptive filter processing and RAMs 3, 4 storing filter coefficient data, and a DSP 2 reading the filter coefficient data from the RAMs 3, 4 and applying the adaptive filter processing to them, and the filter coefficient data are subject to correction processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive signal processing apparatus, and more particularly to an adaptive signal processing apparatus used for adaptive filter processing such as echo canceller and noise canceller.

[0002]

2. Description of the Related Art In recent years, digital signal processing devices (DS) have been used as echo cancellers and noise cancellers for telephone lines.
An adaptive signal processing device applying P) has been used. The adaptive signal processing device performs adaptive filter processing based on a least mean square (LMS) algorithm that corrects filter coefficients so as to minimize the mean square value of prediction errors.

The outline of the adaptive filter processing will be described below.

First, the current time T for the adaptive filter
The input signal sequence vector S (k) up to 0 is represented by the following equation.

[0005]

The filter coefficient vector A (k) is expressed by the following equation.

[0007]

The predicted value P (k + 1) of the sample at the next time T1 according to the input signal train until the current time T0 is shown by the following equation.

P (k + 1) = A (k) · S (k) (3) Further, the correction formula A (of the filter coefficient for the sample at time T1 k + 1) is shown by the following equation.

A (k + 1) = A (k) + K (k + 1) .e (k) ... (4) where e (k) is an error signal and the gain K is LMS.
In the case of an algorithm, it is expressed by the following equation.

K (k + 1) = S (k) (5) Practically, in order to reduce the influence of the transmission path error. In addition, the following expression is used as the correction expression A (k + 1) of the filter coefficient.

A (k + 1) = w · A (k) + K (k + 1) · e (k) (0 <w <1) (6) where Where w is a weighting factor.

FIG. 2 shows a signal flow of the adaptive filter processing.

In FIG. 2, the signal flow includes multiplication processes M1 to M10, delay processes D1 to D5 for delaying an input signal by a time corresponding to one sampling period, and addition processes A1 to A5.

In the case of a noise canceller, the input signal S
(K) is the noise-only observation signal and the predicted value of the input sample at the next time T1, and P (k + 1) is the noise estimated value.
The error signal e (k) corresponds to the difference between the voice signal in the noise-containing state and the estimated value of the noise.

An adaptive signal processing device for performing the adaptive filter processing is generally a digital signal processing device (DSP).
Is constructed using.

In the conventional adaptive signal processing apparatus, the processing for realizing the adaptive filter and the processing for correcting the filter coefficient are performed within the same DSP. By using a DSP specialized for normal finite impulse response (FIR) filter processing, the processing for realizing the adaptive filter can be achieved with high efficiency. However, the efficiency of the filter coefficient correction process is not high. The reverse is also true, and it is difficult to realize highly efficient processing by using a general-purpose DSP that is not specialized for any processing. On the other hand, there is a DSP having a specialized hardware configuration dedicated to the adaptive signal processing, but it is expensive and it is difficult to flexibly change the coefficient calculation algorithm.

[0018]

In the conventional adaptive signal processing apparatus described above, the adaptive filter realization processing and the filter coefficient correction processing are performed in the same DSP, so that the general-purpose DSP is highly efficient overall. However, there is a drawback that it is difficult to improve the efficiency of the other process by using the DSP specialized for one of the processes. Also,
DSP with specialized hardware configuration for adaptive signal processing
However, there are drawbacks that it is expensive and it is difficult to flexibly change the coefficient calculation algorithm.

[0019]

An adaptive signal processing apparatus according to the present invention includes a first signal processor for performing adaptive filter processing using coefficient data, and a first signal processor for storing the coefficient data. It comprises a coefficient data storage means for outputting and a second signal processor for modifying the coefficient data and storing the modified coefficient data thus modified in the coefficient data storage means.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the adaptive signal processing apparatus of the present invention.

As shown in FIG. 1, the adaptive signal processing apparatus of the present embodiment includes a DSP 1 for performing adaptive filter realization processing,
A DSP 2 for correcting the filter coefficient, a RAM 3 for storing the filter coefficient, a RAM 4 for storing the corrected filter coefficient, and multiplexers MX1, M for switching the address bus between the DSP 1, 2 and RAMs 3, 4.
Multiplexers MX3, MX4 for switching the data bus between X2 and the DSPs 1, 2 and RAMs 3, 4;
A toggle flip-flop F1 for switching control of the multiplexers MX1 to MX4 controlled by the timing signal FS of the sampling cycle, and inverters I1 and I2 are provided.

Next, the operation of this embodiment will be described.

The signal flow of the adaptive filter processing by the LMS algorithm shown in FIG. 2 is decomposed into a filter realization processing flow of (A) and a filter coefficient correction processing flow of (B) as shown in FIG. be able to.

The filter realization processing flow is FIR filter processing as shown in FIG. 3A, and multiplication processing M11
To M21, delay processing D11 to D15 for delaying the input signal by a time corresponding to one sampling cycle, and addition processing A1
Including 1 and.

The filter coefficient correction processing flow is shown in FIG.
As shown in (B), this is a feedback type process, and the multiplication process M3
1 to M33, delay processing D31 to D33 for delaying the input signal by a time corresponding to one sampling cycle, and addition processing A
31 to A33 are included.

Further, a (n) and b (n) respectively indicate the filter coefficient to be corrected and the correction data necessary for correcting the filter coefficient a (n).

In FIG. 1, first, the DSP 1 is a RAM
The filter coefficient data a (n) is read from 3 and adaptive filter realization processing is performed. Also, the filter coefficient data a
After reading (n), the correction data b (n) is written in the RAM 3. On the other hand, the DSP 2 stores the correction data b in the RAM 4
(N) is read, the correction value of the filter coefficient data a (n) is calculated, and the result is written in the RAM 4. When a series of processing within one sampling period is completed, the multiplexers MX1 to MX4 are switched by the toggle flip-flop F1, the inverters I1 and I2, and the DSPs 1, 2, and R are switched.
The address bus and the data bus are switched between AM3 and AM4. By performing this switching operation in a cycle in which the filter coefficient data needs to be corrected, that is, in the sampling cycle FS, mutual data transfer between the DSPs 1 and 2 is enabled via the RAMs 3 and 4.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made.

For example, instead of switching and using two RAMs respectively storing filter coefficient data and correction data, a 2-port RAM is used so that the access areas of two DSPs do not overlap in synchronization with the coefficient correction cycle. Needless to say, the generation and operation of alternating addresses can be applied without departing from the spirit of the present invention.

[0031]

As described above, the adaptive signal processing apparatus of the present invention includes a first signal processor for performing adaptive filter processing and coefficient data for storing coefficient data and outputting it to the first signal processor. By including the storage means and the second signal processing processor that corrects the coefficient data, the signal processing processor specialized for each processing can be efficiently operated. This has the effect of improving performance.

Further, there is an effect that it is cheaper than a DSP dedicated to adaptive signal processing, and that the coefficient calculation algorithm can be easily changed flexibly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an adaptive signal processing device of the present invention.

FIG. 2 is a signal flow diagram showing a signal flow in adaptive filter processing.

FIG. 3 is a signal flow diagram showing a signal flow in adaptive filter processing of the adaptive signal processing device of the present embodiment.

[Explanation of symbols]

1, 2 DSP 3, 4 RAM F1 toggle flip-flop I1, I2 inverter MX1 to MX4 multiplexer A1 to A5, A11, A31 to A33 addition processing D1 to D5, D11 to D15, D31 to D33 delay processing M1 to M10, M11 to M21, M31 to M33 Multiplication processing

Claims (1)

[Claims] 1. A first signal processor for performing adaptive filter processing using coefficient data, coefficient data storage means for storing the coefficient data and outputting the coefficient data to the first signal processor, and modifying the coefficient data. An adaptive signal processing device, comprising: a second signal processor for processing and storing the corrected coefficient data that has undergone this correction processing in the coefficient data storage means.