JPH0639349Y2 - Error rate measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial application field" The present invention relates to a device for supplying a test signal to a circuit under test and comparing an output signal of the circuit under test with an expected value to measure an error rate. . In particular, it is a relatively simple circuit that enables the error rate to be measured by supplying test signals with different bit rates to the circuit under test.

"Description of Prior Art" FIG. 3 shows a block diagram of a conventional error rate measuring device. This is because the transmitter 12 creates test signals with different bit rates and supplies them to the circuit under test 11, and the output signal of the circuit under test at that time is received by the receiver 13 and compared with the expected value to determine the error rate. The measurement is made.

In the transmitter 12, clock signals having different frequencies are supplied from a plurality of oscillators 15 to the selection circuit 16. And the control circuit 14
One of the signals is selected by the signal supplied from and is supplied to the pattern generation circuit 17. A signal to be supplied to the circuit under test 11 is stored in the memory of the pattern generation circuit 17, and is read every time a clock signal is supplied from the selection circuit 16,
It is supplied to the circuit under test 11 through the buffer circuit 18.

In the receiving section 13, the output signal of the circuit under test 11 is buffered.
Through 19, a plurality of narrow band filters 21 and a comparison circuit
It is supplied to one of the 25 input terminals. The pass frequency of each narrow band filter 21 is set to be equal to the oscillation frequency of each oscillator 15, and the output signals of each are selected by the selection circuit 22.
Is supplied to. The selection circuit 22 selects a signal having the same frequency as the oscillation frequency selected by the selection circuit 16 based on the signal supplied from the control circuit 20, and supplies the selected signal to the pattern generation circuit 23 and the frequency dividing circuit 24. That is, the narrow band filter 21, the selection circuit
By 22, the clock signal supplied from the selection circuit 16 to the pattern generation circuit 17 is reproduced. Pattern generation circuit
The expected value of the output signal of the circuit under test 11 is stored in the memory 23, and is read every time the clock signal is supplied from the selection circuit 22 and supplied to the other input terminal of the comparison circuit 25. . The comparator circuit 25 outputs a theoretical "1" signal when the signals input from the two input terminals are different. The frequency dividing circuit 24 creates a clock signal having a pulse width that is an integral multiple of the clock signal supplied from the selection circuit 22, for example, 100 times, and supplies the clock signal to one input terminal of the AND circuit 26. The output terminal of the comparison circuit 25 is connected to the other input terminal of the AND circuit 26. While the output signal of the frequency divider circuit 24 is logic "1", the comparison circuit 25
The output signal of 1 passes through the AND circuit 26, and the signal of logic “1” is counted by the counting circuit 27. The error rate is calculated from the count value of the counting circuit 27 and displayed on the display circuit 28.

In the above circuit, the number of oscillators 15 is increased and the circuit under test 11
If the bit rate of the test signal supplied to
In accordance with this, the number of narrow band filters 21 has to be increased, and there is a problem that the cost becomes high.

"Means for Solving Problems" The error rate measuring device according to the present invention includes a reference oscillator instead of the clock signal regenerating circuit including a plurality of narrow band filters 21 and a selecting circuit 22 shown in FIG. A circuit composed of a frequency synthesizer for synthesizing an output signal of the circuit under test 11 and a clock signal in phase synchronization from the output signal of the reference oscillator is used. This frequency synthesizer is, for example, a frequency synthesizer, the output terminal of the frequency synthesizer is connected to one input terminal, a phase comparison circuit for controlling the output signal of the frequency synthesizer, and the output terminal is the other input terminal of the phase comparison circuit. Connected to the output terminal of the frequency synthesizer and the selection circuit connected to the output side of the circuit under test. The selection circuit supplies the output signal to the other input terminal of the phase comparison circuit when the output signal of the circuit under test is theoretically "1", and outputs the output signal of the frequency synthesizer to the other input terminal of the phase comparison circuit otherwise. Supply to the input terminal. The output signal of the frequency synthesizer is supplied to the pattern generating circuit and the frequency dividing circuit as a regenerated clock signal. With this configuration, the error rate can be measured by supplying the test signals having different bit rates to the circuit under test with a relatively simple circuit.

[Embodiment] FIG. 1 shows a block diagram of an error rate measuring device which is an embodiment of the present invention. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals.

In the transmitter 29, the output terminal of the reference oscillator 31 is connected to the frequency synthesizer 32. The frequency synthesizer 32, based on the signal supplied from the control circuit 14,
A clock signal having a predetermined frequency is synthesized from the 32 oscillation frequencies and supplied to the pattern generation circuit 17. Each time the clock signal is supplied from the frequency synthesizer 32, the pattern generation circuit 17 sequentially reads the test signals stored in the memory and supplies them to the circuit under test 11 via the buffer circuit 18.

In the receiver 30, the output signal of the circuit under test 11 is buffered.
It is supplied to one input terminal of the comparison circuit 25 and the frequency synthesizer 34 via 19. The frequency synthesizer 34 has a reference oscillator 33
From the circuit under test 11 and the clock signal synchronized in phase with the signal supplied from the circuit under test 11 is synthesized. This clock signal is supplied to the pattern generating circuit 23 and the frequency dividing circuit 24, and the error rate is displayed on the display circuit 28 by the same operation as the circuit shown in FIG.

FIG. 2 shows an embodiment of the frequency synthesizer 34. Reference oscillator
The reference frequency of 33 is supplied to the frequency synthesizer 37.
The input terminal 35 is connected to the output terminal of the buffer circuit 39 shown in FIG. 1, and the output terminal 41 is connected to the input terminals of the pattern generating circuit 23 and the frequency dividing circuit 24. In FIG. 2, the input terminal 35 is connected to one input terminal of the selection circuit 38 and the set terminal S of the flip-flop circuit 36. The other input terminal of the selection circuit 38 is connected to the output terminal of the frequency synthesizer 37, and the output terminal is connected to the reset terminal R of the flip-flop circuit 36. Flip-flop circuit
The output terminal Q of 36 is connected to the control signal input terminal of the selection circuit 38. The selection circuit 38, when the signal of logic “0” is supplied from the output terminal Q of the flip-flop circuit 36,
The signal supplied from the frequency synthesizer 37 is output. When the signal supplied from the input terminal 35 rises to the logic "1", the flip-flop circuit 36 is set and the output terminal Q outputs the signal of the logic "1". At this time, the signal supplied from the input terminal 35 is selected by the selection circuit 38 and output. Then, since the signal of logic "1" is supplied to the reset terminal R of the flip-flop circuit 36, the flip-flop circuit 36 is reset, and the signal of logic "0" is output from the output terminal Q. The output signal of the selection circuit 38 is supplied to one input terminal of the phase comparison circuit 39 in addition to the reset terminal R of the flip-flop circuit 36. The output signal of the frequency synthesizer 37 is supplied to the other input terminal of the phase comparison circuit 29. The phase comparison circuit 39 outputs a signal corresponding to the phase difference between the two input signals and supplies it to the frequency synthesizer 37 through the filter 41. The frequency synthesizer 37, the phase comparison circuit 39, and the filter 40 form a phase lock loop, and the clock signal synchronized with the signal input from the input terminal 35 from the frequency synthesizer 37 is reproduced.

With the above configuration, a test signal can be supplied to the circuit under test while changing the bit rate with a relatively simple circuit, and the error rate can be measured from the output signal of the circuit under test.

In FIG. 1, a counter circuit is used instead of the frequency divider circuit 24 and the AND circuit 26, and the ratio of the number of clock signals output from the pattern generation circuit 34 to the number of clock signals output from the comparison circuit 25 is used. The error rate may be obtained from

[Advantage of Device] As described above, the error rate measuring device according to the present invention receives the test signal from the transmitter which can change the bit rate and supply the test signal to the circuit under test, the reference oscillator, and the output signal of the reference oscillator. A frequency synthesizer that synthesizes a clock signal that is phase-synchronized with the output signal of the test circuit and the expected value of the output signal of the circuit under test are stored, and are sequentially read every time the clock signal is supplied from the frequency synthesizer. And a receiving section including a comparison circuit for comparing the output signal of the circuit under test with the output signal of the pattern generation circuit. With this configuration, the receiving section does not use a narrow band filter for regenerating the clock signal from the output signal of the circuit under test, so that the error rate measuring device can be obtained relatively inexpensively.

[Brief description of drawings]

FIG. 1 is a block diagram of an error rate measuring device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the frequency synthesizer of FIG. 1, and FIG. 3 is a conventional error rate measuring device. It is a block diagram of.

Claims (1)

[Scope of utility model registration request] 1. A transmitter for supplying a test signal to a circuit under test by changing the bit rate, B. a reference oscillator, and a clock signal synchronized with the output signal of the circuit under test from the output signal of the reference oscillator. The frequency synthesizer for synthesizing and the expected value of the output signal of the circuit under test are stored,
A pattern storage circuit that is read every time a clock signal is supplied from the frequency synthesizer, a comparison circuit that compares the output signal of the circuit under test and the output signal of the pattern storage circuit, the output signal of the frequency synthesizer, and the above An error rate measuring instrument comprising: a receiving section comprising means for obtaining and displaying an error rate from an output signal of a comparison circuit;