JPH0588048U - Error detector - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable rapid and accurate processing of a large amount of data including error pulses. [Structure] A 2 ⁿ frequency division counter 11 counts the number of error pulses. When the predetermined time has passed, the MPU 13
The stops the 2 ⁿ dividing counter 11 shifts from the 2 ⁿ dividing counter 11 error pulse information to the shift register 12. Next, the MPU 13 reads the error pulse information from the shift register 12 and outputs 2 ⁿ
The frequency division counter 11 is set and the counting of error pulses is started again. By repeating this operation in the same manner, MP
U13 can always count the number of error pulses in real time.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an error detection device, and more particularly to an error detection device that detects and analyzes an error pulse on the receiving side of a line in wired data transmission.

[0002]

[Prior Art]

 Conventionally, this type of error detecting device is configured as shown in FIG. This error detection device is provided with a 16 frequency division counter 21 for counting the number of errors. The 16-divider counter 21 includes four D-type flip-flops 21 connected in series.₁~ 21_nIt is composed by. Flip-flop 21₁A pulse input terminal 14 is connected to the clock input terminal of the. Flip-flop 21₁The inverted output signal of is supplied to the data input terminal and the flip-flop 21 of the next stage.₂It is designed to be supplied to the clock input terminal of. Similarly, the flip-flop 21 ₂ The inverted output signal of is supplied to the data input terminal and the flip-flop 21 of the next stage.₃It is designed to be supplied to the clock input terminal of. Flip flop 2 1₃The inverted output signal of is supplied to the data input terminal and the flip-flop 21 of the next stage._FourIt is designed to be supplied to the clock input terminal of.

The inverted output signal of the terminal flip-flop 21 ₄ is supplied to the data input terminal and also to one input terminal (set input terminal) of the RS type flip-flop 24 composed of the NAND gates 24 ₁ and 24 _2. It is supposed to be done. The normal output signal of the flip-flop 24 is supplied to the ALM detection circuit. A clock output from the frequency divider 22 is supplied as a reset signal to the reset terminals of the flip-flops 21 _{1 to} 21 _n and the other input terminal (reset terminal) of the flip-flop 24, which constitute the 16-frequency divider counter 21. It is supposed to be done. The frequency dividing circuit 22 divides the frequency of the oscillator 23 to generate a clock.

In this conventional error detecting device, the 16-frequency division counter 21 counts the number of errors in the pulse input to the clock input terminal of the flip-flop 21 ₁ via the pulse input terminal 14. When the 16-frequency division counter 21 is reset by the clock from the frequency-dividing circuit 22 that is oscillated by dividing the oscillation pulse from the oscillator 23, the number of error pulses obtained by the 16-frequency division counter 21 Information is sent to flip-flop 24. The error pulse number information is further sent from the flip-flop 24 to the ALM detection circuit at the output timing of the frequency dividing circuit 22.

[0005]

[Problems to be solved by the device]

 As described above, in the conventional error detection device, the number of 16-frequency division counters 21 for counting the number of error pulses is as small as 4 bits, and it has been impossible to process a large amount of data. Further, as for the reset timing, since the frequency from the oscillator 23 is frequency-divided by the frequency dividing circuit 22 to perform the hardware reset, it is not possible to obtain accurate error pulse number information, and therefore detailed analysis cannot be performed. Moreover, there was a problem that information could not be obtained in real time.

The present invention has been made in view of the above problems, and an object thereof is error detection capable of processing a large amount of data accurately and quickly and obtaining error pulse information in real time. To provide a device.

[0007]

[Means for Solving the Problems]

 An error detecting apparatus according to the present invention comprises a pulse counting means for counting the number of input error pulses, a data storage means for temporarily storing the error pulse information counted by the pulse counting means, and the pulse counting means. The error pulse information counted by the above is transferred to the data storage means at a fixed timing, and the data reading means for reading the error pulse information transferred to the data storage means in real time is provided.

In this error detecting device, when the number of error pulses input by the pulse counting means is counted, this error pulse information is transferred to the data storage means at a fixed timing by the data reading means, and the data storage means is stored. It is read sequentially from the means in real time.

More specifically, the error detecting device of the present invention is composed of n first flip-flops each having an inverting output terminal connected to a data input terminal, and the inverting output terminal of each flip-flop. Is connected to the clock input terminal of the next-stage flip-flop, and the error pulse is supplied to the clock input terminal of the first-stage flip-flop. The 2 ⁿ frequency division counter for counting the number of the supplied error pulses and the An inversion output signal of the first flip-flop, which is connected in series and has n second flip-flops provided corresponding to the first flip-flops, the second flip-flops respectively corresponding to the second flip-flops. in response to a shift register for temporarily storing them, after the 2 ⁿ dividing counter has started counting error pulses, constant Tai Mi A microprocessor unit for supplying the inverted output signal of each first flip-flop as error pulse information to the corresponding second flip-flop of the shift register and then sequentially reading the error pulse information from the second flip-flop. (Hereinafter, referred to as MPU).

In this error detection device, the 2 ⁿ frequency division counter is reset and the 2 ⁿ frequency division counter starts counting the number of error pulses. Then, after a certain period of time, together with the MPU stops the 2 ⁿ dividing counter, the corresponding shift register and an inverted output signal of the first flip-flop each constituting the 2 ⁿ dividing counter as the error pulse information Then, the error pulse information is sequentially read from the second flip-flop. When the reading is completed, MPU resets 2 ⁿ dividing counter again, thereby the 2 ⁿ dividing counter start counting the number of error pulses again. The above operation is similarly repeated so that the MPU can always process the information by counting the error pulse number in real time.

[0011]

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a specific configuration of the error detecting apparatus of this embodiment. This error detection device includes a 2 ⁿ frequency division counter 11 as pulse counting means for counting error pulses from an input pulse, and a shift register as data storage means for receiving error pulse information from the 2 ⁿ frequency division counter 11. 12 and an MPU 13 as a data reading means for reading error pulse information from the shift register 12 in real time.

The 2 ⁿ frequency ^dividing counter 11 is composed of n D-type flip-flops (hereinafter referred to as flip-flops) 11 _{1 to} 11 _n . Each of these flip-flops 1 1 _{1 to} 11 _n has an inverting output terminal connected to a data input terminal, and an inverting output terminal connected to a clock input terminal of the next-stage flip-flop. A pulse input terminal 14 is connected to the clock input terminal of the first-stage flip-flop 11 ₁ , and an error pulse is supplied from this. The flip-flops 11 _{1 to} 11 _n have reset terminals (R).

[0014] The shift register 12, 2 ⁿ partial number of n provided in correspondence to the flip-flops 11 ₁ to 1 1 _n of the division counter 11 D-type flip-flop (hereinafter, referred to as flip-flops) 12 ₁ to 12 _{It is} composed of _n and one D-type flip-flop (hereinafter referred to as flip-flop) 12 _{n + 1} . The normal output terminals of the flip-flops 12 _{1 to} 12 _n are connected to the respective data input terminals of 12 _{2 to} 12 _{n + 1} of the next-stage flip-flop. Each of the flip-flops 12 _{1 to} 12 _n has a set terminal (S) and a reset terminal (R). The flip-flop 12 _{n + 1} has a set terminal (S).

The output terminals of the OR gates 15 ₁ to 15 _n are connected to the reset terminals of the flip-flops 12 _{1 to} 12 _n . The inverted output signals of the corresponding flip-flops 11 _{1 to} 11 _{n in} the 2 ⁿ frequency ^dividing counter 11 are supplied to the respective one input terminals of the OR gates 15 ₁ to 15 _n . A reset signal output from the reset signal output terminal (STB 2) of the MPU 13 is supplied to each of the other input ends of the OR gates 15 ₁ to 15 _n .

[0016] MPU13 also supplies a set signal to each set terminal of the flip-flop 12 ₁ ~12 _{n + 1} from the set signal output terminal (STB 2), each clock of flip-flop 12 ₁ ~12 _{n + 1} A clock is supplied to the terminal from a clock output terminal (CLKOUT). The normal input terminal of the flip-flop 12 _{n + 1 at} the final stage of the shift register 12 is connected to the data input terminal of the MPU 13, and the data (error pulse) is read sequentially from the normal output terminal. ing. The MPU 13 also supplies a reset signal from the reset signal output terminal (STB3) to each reset terminal of the flip-flops 11 _{1 to} 11 _n of the 2 ⁿ frequency ^dividing counter 11, whereby the 2 ⁿ frequency ^dividing counter is supplied. 1 1 is to be reset.

Next, the operation of the error detection device of this embodiment will be described.

First, the MPU 13 outputs a set signal from the set signal output terminal (STB1) before counting the number of error pulses, and sets a series of flip-flops 12 _{1 to} 12 _{n + 1} forming the shift register 12 respectively. Keep it. At this time, the MPU 13 does not output the reset signal from the reset signal output terminal (STB2).

Immediately before attempting to count the number of error pulses, the MPU 13 outputs a reset signal from the reset signal output terminal (STB3) to each of the flip-flops 1 1 _{1 to} 11 _{n of the} 2 ⁿ frequency ^dividing counter 11. Is output and the 2 ⁿ frequency division counter 11 is reset. After that, a pulse is input to the 2 ⁿ frequency ^dividing counter 11 via the pulse input terminal 14 and starts counting the number of error pulses. After a lapse of a predetermined time, the MPU 13 outputs a reset signal from the reset signal output terminal (STB2). As a result, the storage data of each flip-flop 11 _{1 to} 11 _n of the 2 ⁿ frequency ^dividing counter 11 is transferred to the corresponding flip-flop 12 _{1 to} 12 _n of the shift register 12. Immediately thereafter, the MPU 13 outputs a reset signal from the reset signal output terminal (STB3) and resets the 2 ⁿ frequency division counter 11 again. As a result, the 2 ⁿ frequency division counter 11 starts counting the next error pulse.

On the other hand, the MPU 13 outputs a read clock from the clock output terminal (CLKOUT) to each of the flip-flops 12 _{1 to} 12 _n . As a result, the information transferred to the flip-flops 12 _{1 to} 12 _n is read bit by bit into the data input terminal of the MPU 13 via the positive output terminal of the flip-flop 12 _{n + 1} . Upon reading the data of all the flip-flops 12 _{1 to} 12 _n , the MPU 13 outputs a set signal from the set signal output terminal (STB1) to set all the flip-flops 12 _{1 to} 12 _{n + 1} of the shift register 12. To prepare for the next operation.

In the error detection device of this embodiment, the MPU 13 can always count the number of error pulses in real time and process the information by repeating the above-described operation in the same manner.

[0022]

[Effect of the device]

 As described above, according to the error detecting device of the present invention, the error pulse information counted by the pulse counting means is transferred to the data storage means at a fixed timing, and the error pulse information stored in the data storage means is stored in the data storage means. Since the reading means reads in real time, a large amount of data can be processed accurately and quickly.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an error detection device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional error detection device.

[Explanation of symbols]

11 2 ⁿ frequency ^dividing counter 11 _{1 to} 11 _n D-type flip-flop 12 shift register 12 _{1 to} 12 _{n + 1} D-type flip-flop 13 Microprocessor unit (MPU)

Claims (2)

[Scope of utility model registration request] 1. A pulse counting means for counting the number of input error pulses, a data storage means for temporarily storing the error pulse information counted by the pulse counting means, and a pulse counting means for counting the error pulse information. An error detecting apparatus comprising: a data reading unit that transfers error pulse information to the data storage unit at a fixed timing and reads the error pulse information transferred to the data storage unit in real time. 2. An n-th first flip-flop, each of which has an inverting output terminal connected to a data input terminal, and an inverting output terminal of each flip-flop is connected to a clock input terminal of a next-stage flip-flop. And the error pulse is supplied to the clock input terminal of the first-stage flip-flop, and the number of the supplied error pulse is counted 2
^{An n} frequency ^dividing counter and ⁿ second flip-flops connected in series with each other and provided corresponding to the first flip-flops, the second flip-flops respectively corresponding to the first flip-flops. A shift register that receives inverted output signals of the flip-flops and temporarily stores them, and an inverted output of each of the first flip-flops at a fixed timing after the 2 ⁿ frequency division counter starts counting error pulses. An error detection device comprising: a microprocessor unit that transfers a signal as error pulse information to a corresponding second flip-flop of the shift register, and then sequentially reads the error pulse information from the second flip-flop. ..