JPH0335856B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counting circuit, and more particularly to a counting circuit for determining the interval at which a desired number of pulses occur in a clock pulse train.

A conventional counting circuit is a circuit that counts and stores the number of pulses, and the time from when a counting pulse is applied until the counting operation is completed is approximately determined by the performance of the flip-flop circuit used. Therefore, the general usage of a counting circuit is to use the count value, and when using the interval at which a desired number of pulses are generated, for example, when trying to use it in a rotary encoder, it is necessary to use the count value as it is. The drawback was that it was not available.

The present invention eliminates the above drawbacks and provides a counting circuit which can set and output a desired number of clock pulses at intervals.

The counting circuit according to the present invention includes a holding means for holding a counting permission signal, a gate means for transmitting a clock signal in response to the output of the holding means, and a clock signal appearing at the output of the gate means for transmitting the output of the holding means. latching means for latching in synchronization with the signal;
a counter for counting the clock signal appearing at the output of the gate means and generating a signal indicating a predetermined count value; and means for resetting the holding means and the latch means in response to the signal from the counter; It is characterized in that the output of the latch means is used as a counting state determination signal.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The counting circuit of this embodiment receives preset count data 11 and outputs a latch control signal 12.
latch circuit 1 held by and carry signal 21
and the reset signal 14.
and a 1-bit binary counter 4 which is cleared by the output signal 16 of the OR circuit 3 and outputs a count value by detecting the rising edge of the input counting permission signal 17; The output signal 18 of the binary counter 4 is input to the J terminal, the carry signal 21 is input to the K terminal, the falling edge of the clock pulse signal 15 to be counted is detected, and it is determined by the combination of the signals input to the J and K terminals. A falling edge-triggered J-K flip-flop 5 outputs a logical value, an AND circuit 6 takes a logical value between the output signal 19 of the J-K flip-flop 5 and the counted clock pulse signal 15, and a reset signal 14 clears the output signal. , an N-bit binary counter 2 which inputs the output signal 20 of the AND circuit 6 and the output signal 13 of the latch circuit 1, counts up to a preset value, and generates a carry signal 21 when the preset value is reached; It is cleared by the output signal 16 of the circuit 3, and the output signal 19 of the J-K flip-flop 5 is input to the D terminal, and the rising edge of the output signal 20 from the AND circuit 6 is detected to generate a rising signal.・Counter 2
The D flip-flop 7 includes a rising edge trigger type D flip-flop 7 which outputs a single bit information count state determination signal 22 indicating whether or not the count is in progress.

Next, the operation of this embodiment will be explained in the case of positive logic using FIG. In the case of negative logic, just reverse the logic.

FIG. 2 is a waveform diagram of signals appearing in various parts of the embodiment shown in FIG. 1.

First, N bit count value M (N, M are integers,
A preset count data signal 11 corresponding to 1≦N, 0<M≦2 ^N is applied to the latch circuit 1 and is temporarily held by the latch control signal 12. N by the latch data output signal 13 of the latch circuit 3
The preset count data 13 is given to the bit binary counter 2 to set the preset value. Next, N-bit binary counters 2, 1
A reset signal 14 is applied to the bit binary counter 4, JK flip-flop 5, and D flip-flop 7 to reset them (setting them to positive logic "0"). The counted clock pulse signal 15 is applied to a JK flip-flop 5 and an AND circuit 6.

Next, when the counting permission signal 17 is applied to the 1-bit binary counter 4, the output signal 18 of the 1-bit binary counter 4 becomes logic "1", and this output signal 18 is applied to the J of the J-K flip-flop 5. input to the terminal. Since logic "0" is input to the K terminal of the J-K flip-flop 5, the clock pulse signal 1 to be counted is input to the clock pulse signal input terminal CP of the J-K flip-flop 5.
When the falling edge of 5 is applied, the signal 19 which is triggered and output from the output terminal Q of the JK flip-flop 5 becomes logic "1". Since the AND circuit 6 takes the AND of the counted clock pulse signal 15 and the signal 19 from the terminal Q, the AND circuit 6
The output signal 20 is the counted clock pulse signal 15.
The signal has the same waveform as .

When the rising edge signal of the output signal 20 from the AND circuit 6 is applied, the N-bit binary counter 2 starts counting. At the same time, the D flip-flop 7 receives the output signal 19 of the J-K flip-flop 5 and the output signal 20 of the AND circuit 6, detects the rising edge of the signal 20, generates a rising signal (logic "1"), and thereafter outputs the final count value. N until a rising edge of signal 20 corresponding to N is given.
The fact that the bit binary counter 2 is counting is outputted as a count state determination signal 22 of single bit information.

The N-bit binary counter 2 continues counting, and when it receives the rising edge signal of the preset value M from the AND circuit 6, it rises (becomes logic "1") and outputs a carry signal 21 indicating that the count value has reached the preset value. Output as . The carry signal 21 is input to the OR circuit 3, and the output signal 18 of the 1-bit binary counter 4 falls (logic "0").
). Since the carry signal 21 is also input to the K terminal of the JK flip-flop 5, it detects the falling edge of the counted clock pulse signal 15 and outputs a falling signal. That is, a logic "0" signal is output. This signal 19 is given to the AND circuit 6, and the output signal 20 of the AND circuit 6 becomes logic "0", and the N-bit binary counter 2
The supply of clock pulses 15 to be counted is prohibited. This ends the counting state. When counting is to be performed again, a reset signal 14 is applied.
The above operations are repeated.

As explained in detail above, according to the present invention,
The interval between the desired number of clock pulses can be set, and a single bit information can be used to determine whether the clock pulses are being counted until the set number is reached or when the counting has ended. The effect is great because a counting circuit that can be output and displayed is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a waveform diagram of signals appearing in each part of the embodiment shown in FIG. 1. 1... Latch circuit, 2... N-bit binary counter, 3... OR circuit, 4... 1-bit binary counter, 5... J-K flip-flop, 6
...AND circuit, 7...D flip-flop, 11...
Preset count data, 12...Latch control signal, 13...Latch data output signal, 14...
Reset signal, 15...Clock pulse signal to be counted, 17...Counting permission signal, 21...Carry signal, 2
2...Count state determination signal.

Claims (1)

[Claims] 1 holding means for holding the input counting permission signal; gate means for receiving a clock signal and transmitting the clock signal in response to the counting permission signal holding output from the holding means; and the counting permission signal from the holding means. A latch means for latching the signal holding output in synchronization with a clock signal appearing at the output of the gate means, and a counter for counting the clock signal appearing at the output of the gate means and generating a signal indicating that a predetermined count value has been reached. and means for resetting the holding means and the latch means in response to the signal from the counter, the output of the latch means being derived as a counting state determination signal.