SU1725180A2 - Meter of total time of delay - Google Patents

Abstract

The invention relates to a radio metering technique and can be used to measure the frequency characteristics of a group time delay of radio devices. The purpose of the invention is to improve the measurement accuracy. The device contains a discretely tunable generator 1, two-phase generator 2, modulator 3, terminals 4 and 5 of the object under study, switch 6, attenuator 7, amplifier 8, detector 9, ADC 10, phase meter 11, generator 12 pulses, driver 13 pulses, synthesizer 14 clock frequencies, data registers 15 and 16, control registers 17-22, system backbone 23, display unit 24, control panel register 25 and microprocessor unit 26. 2 Cp. f-ly, 5 ill.

Description

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The invention relates to the field of radio measurements, can be used to measure the group delay time (RMS) of radio devices and is an improvement to the invention by the author. No. 1555697.

A known group delay meter is known.

The disadvantages of the known meter are the increased value of one of the components of the random measurement error, determined by the quantization error of the phase meter with the pulse conversion at arbitrary ratios of the quantization frequencies and the signal at its inputs, as well as the presence of the error introduced by the two-phase generator and depends from the specified phase shift.

The aim of the invention is to increase the measurement accuracy.

Figure 1 shows the structural diagram of the meter; figure 2 - diagram of the synthesizer clock frequency; on fig.Z - structural diagram of the phase meter; Fig. 4 is a block diagram of a measuring cycle shaping unit; figure 5 - timing charts of their work (figure 5).

GD meter (figure 1) contains a discrete tunable generator 1 and two-phase generator 2 with a modulator 3 connected to it, which output is connected to input 4 terminal of the object under study, output terminal 5 of which is connected to the first input of switch b, connected to with the second input with the input terminal 4 of the object under study, and the output through an attenuator 7 and amplifier 8 connected in series with the detector 9, to the output of which are connected an analog-to-digital converter (ADC) 10 and a phase meter 11, which is also connected to the generator 12 pulse and the second output of the two-phase generator 2, which through the driver 13 pulses connected to the start input of the ADC 10, the synthesizer 14 clock frequency, the input and output of which are connected respectively to the input of the generator 12 pulses and the clock input of the two-phase generator 2, data registers 15 and 16 connected inputs, respectively, with outputs of ADC 10 and phase meter 11, control registers 17-22, connected by outputs, respectively, with control inputs of discretely tunable generator 1, two-phase generator 2, synthesizer 14 clock frequency switch 6, the attenuator 7 and the phase meter 11, and inputs - with the overall system trunk 23, which are also connected to registers 15 and 16 of the data block 24

the display, the control panel register 25 and the microprocessor unit 26, which are connected to the control panel register 25, the ADC 10 and the phase meter 11 by interrupt request inputs.

The clock frequency synthesizer circuit 14 (FIG. 2) comprises a first frequency divider 27 connected in series, a phase detector 28, a low-pass filter 29 and a tunable oscillator 30, the output of which is connected via a second divider

31 frequency with the second input of the phase detector 28, is the output of the synthesizer.

The block diagram of the phase meter 11c time pulse conversion (fig.Z) contains a series-connected unit

32 converting the phase shift into time intervals whose inputs are signal inputs and quantization input of the phase meter 11, and a time interval to 33 code conversion unit whose output is the output of the phase meter 11, as well as a measuring cycle generation unit 34 connected to them, the external inputs of which are respectively the start and control inputs of the phase meter, and its output is the output of the phase meter measurement end.

The block diagram of the measuring cycle forming unit 34 (FIG. 4) comprises an AND 35, a series-connected element, a counter 36, an RS flip-flop 37, and a D-flip-flop 38, the output of which is connected to the second input of the And 35 element and the output of the block 34 connected to the S-input of the RS-flip-flop 37, the R-input of the D-flip-flop 38 and the initial setup input of the counter 36, whose preset input is the control input of the unit 34.

The operation of the group lag time meter starts with the setting of the test signal parameters, the operation mode and the parameters of the meter, i.e. programming device. The values of the amplitude and frequency of the carrier of the discretely tunable generator 1, the amplitude, frequency and phase shift of the two-phase generator 2, the position of the switch 6 (calibration-measurement mode), the attenuation value of the attenuator 7, the duration of the measuring cycle determined by the number of averaged periods are programmed. the signal of the phase meter 11, to which the values of the programmable parameters of the 14 clock frequency synthesizer are also rigidly connected.

The specified parameters or a part of them are written to the corresponding control registers 17-22 through the common system highway 23 automatically from the microprocessor unit 26 (typical values) or

entered manually by the user through the control panel register 25, the contents of which are read by the microprocessor unit 26 at the interrupt request and rewritten into the corresponding control register 17-22. The values of the input parameters can be simultaneously displayed on the display unit 24.

The meter has two modes of operation — calibration and measurement, determined by the position of switch 6. In calibration mode, an AM test signal from the output of the modulator 3 passes from input terminal 4, the object under test to the switch 6 output, and in measurement mode from the input terminal 4 enters the object under study and from the output terminal 5 to the output of the switch 6.

The sequence of calibration and measurement cycles when the frequency characteristic (TF) of the group stage is measured by the object under study may be different: alternating at each point of the measured frequency group of the GDT or the number of counts of the frequency group of the GHG depending on the stability of the own frequency group of the meter and the required measurement accuracy. In some cases, calibration can be performed periodically at a predetermined time interval. The values of the group delay, obtained in the calibration mode, determine the intrinsic systematic errors of the meter and are subtracted from the measurement results of the frequency group of the phase group of the object under study in the microprocessor unit 26.

Next, the AM signal from the output of the switch 6 passes through the attenuator 7, the amplifier 8, the detector 9 and enters the input of the ADC 10 and the first signal input of the phase meter 11. The attenuation of the attenuator 7 depending on the level of the AM signal at the input of the object under study and its transmission coefficient is set Thus, in order to provide an approximate equality of the signal level at the input of the detector 8 in the calibration and measurement modes, and with a large unevenness of the object's frequency response, also at different frequencies of the measured frequency response group of the object under study. Due to this, the amplitude error of the measurement of the group delay is minimized.

The second signal input of the phase meter 11 receives a signal with a modulation frequency (or twice the modulation frequency in the case of balanced AM and quadratic detection) from the second output of the two-phase generator 2. The calibrated values of the phase shift of this generator are set so that the phase shifts of the input signals of the phase meter 11 calibration and measurement modes are close to 90 °,

ensuring minimum steepness of the main error of the phase meter. At this phase shift, the ADC reads 10 amplitude values of the envelope

the signal from the output of the detector 9 according to the start signals of the ADC 10 from the output of the imaging unit 13 pulses.

Samples of the amplitude of the envelope from the output of the ADC 10 at the signal of the end of the conversion

written to the data register 15, where it is also possible to accumulate these samples (register or operational memory), and by the interrupt request signal (for each or several requests depending on the envelope frequency and the presence of information in the data register 15) the amplitude codes are read from data register 15 in microprocessor unit 26. These samples determine the frequency response of the object under study, and are also used to set attenuation for attenuator 7.

The input calibrated values of the phase shift of the two-phase generator 2 are easily taken into account and subtracted from the measurement results in the microprocessor unit 26. However, in the general case, the two-phase generators also have a basic error depending on the specified phase shift. The specified error

may be commensurate with the basic error of the phase meter 11, which results in a decrease in the accuracy of the measurement of the group delay. .

To improve the measurement accuracy in the device, the measurement technique is changed so that measurements at each point of the emergency response group are performed as a sequence of P measuring cycles, in each of which the input phase shifts of the two-phase generator 2 take on the values: ODFP I DN, where i

 0,1,2Р-1; Other 360 ° / Р.

The measurement result in the i-th cycle, taking into account the basic errors of the two-phase generator and phase meter 11

A.rfm can be represented as follows:

Rizm + RDFP +

where in is the measured phase shift at the inputs of the phase meter 11.

The average measurement results for all cycles, get

i

2, Rizm # “+ --B +

i

2 (D rdFG +)

-F

i 1

Since the input phase shift values are known, the second term can be excluded from the measurement results, the Third term due to the periodicity and uncorrelated values of the basic errors of the two-phase generator 2 and phase meter 11 is a rather small value decreasing with increasing P (averaging effect of the main error .

The quantization of the time intervals proportional to the phase shift of the envelope (and, consequently, the value of the GVZ) at the inputs of the phase meter 11c is pulse-transformed and averaged over the measurement cycle time is carried out by pulses with a quantization frequency f B B from the generator output 12. The quantization error of the phase meter 11 is One of the components of the random error of measurement of the group delay, it very much depends on the ratio of the signal frequencies (envelope) and quantization. With independent quantization (known meter), when the indicated frequencies are in an arbitrary ratio, the quantization error is usually estimated as OHK gq / h7K, where / fKB; K is the number of averaged signal periods. However, with a high frequency stability of the signal and quantization, with some values of the modulation frequency, a sharp increase in the quantization error is possible up to the sfc / 1 / y value corresponding to the integer ratio of the indicated frequencies.

A significant reduction in quantization error can be achieved by maintaining a certain optimal ratio of signal and quantization frequencies that satisfy the condition f KB, where M and K are mutually prime numbers; at the same time, the quantization error takes the minimum value σ 1q / (6 K) in the averaging interval equal to K signal periods.

In the proposed device, the necessary ratio of the signal and quantization frequencies is provided by introducing the synthesizer 14 clock frequency. In this block, the clock frequency f for a two-phase generator 2 is formed (such generators usually provide for the possibility of operating from an external generator). This frequency is obtained by multiplying the quantization frequency of the phase meter by a number equal to the ratio of mutually simple numbers, (K / L). The frequency of the two-phase generator output is generated by dividing the clock frequency by the appropriate number of times.

N so that the ratio of the quantization frequencies and the signal is thus obtained equal to fKB / F (NL) / K. By choosing K not a multiple of the product NL, it is possible to ensure optimal quantization in the phase meter 11 on the number of averaged signal periods K. At, MHz, the quantization error is about –0.045 not, while in the known meter with independent

quantization its value is equal to, 15 not, i.e. more than about 33 times. To achieve the same error with independent quantization, it is necessary to increase the averaging time by a factor of 1000. Besides

In addition, the danger of a sharp increase in quantization error at individual quantization frequencies is not excluded.

The clock synthesizer 14 can be implemented on the basis of active digital frequency synthesis systems with phase synchronization, i.e. PLL systems. The quantization frequency signal from the output of the pulse generator 12 is fed to the input of the first divider 27 with a programmatically variable division factor M, the output of which produces a signal with a frequency of comparison kV / M supplied to the first input of the detector 28. The second input of the phase detector 28 provides the signal output

tunable generator 30, divided by frequency using a frequency divider 31 with a programmable division factor K.

In the steady state, the frequency of the signal at the second input of the phase detector 28 is also equal to FoHve / K. The output signal of the phase detector 28 through the low-pass filter 29 controls the frequency of the tunable oscillator 30 and maintains the frequency ratio tglkv K / M up to phase. The frequency fnr is the clock tV for the two-phase generator 2 and is fed to its clock input.

The division factors of frequency dividers 27 and 31 are set via control register 19. At MHz, fT «100 MHz and kHz receive,. You can use more complex schemes to set large K values.

synthesizer implementation 14 clock frequency.

In the phase meter 11c, a pulse transform (Fig. 3) input signals pass through the conversion unit 32.

phase shift in the time intervals, which are then fed to the block 33 conversion intervals in the code. The codes generated at the output of this block are recorded in data register 16 and at the end of the measuring cycle are read into microprocessor block 26. A feature of phase meter 11 is that the measuring cycle is formed here over a predetermined number of periods of signal K, in which the optimal quantization of time intervals takes place. This is provided by the measuring cycle forming unit 34 (Fig. 4) with a programmable counter 36 of the number of periods of the subtractive type signal. Timing diagrams of the block are shown in figure 5. Counter 35 is preset with a number code K control register 22. On the start signal from the microprocessor unit 26, coming along the common system main 23, a preset (initial setting) of the counter 36, a reset of the D-flip-flop 38 and an installation of the RS-flip-flop 37 are made.

The zero level of the signal from the output of the D flip-flop 38 closes the second input And 36, the first input of which receives signals of the square wave with the frequency of the signal from the meander of the phase-shift block 32 at time intervals. The front of the first time meander D trigger 36 at input C is set to one and the output signal opens AND 35, thereby allowing the number of signal periods to be counted by a counter 36. This signal at the control input simultaneously enables operation of the time interval conversion unit 33 which corresponds to the beginning of the measuring cycle.

After the counter 36 counts (K-1) periods of the signal, at its output a transient pulse is outputted at its output, which will set the RS flip-flop 37 to zero. The signal's meander edge 0 will also trigger the flip-flop 38 and close the element And 35, as well as a block 33 for converting time intervals to a code. This corresponds to the end of the measuring cycle. A drop of type 1/0 from the output of the D-flip-flop 38 is fed to the input of the interrupt request request of the microprocessor unit 26 and the write input of the data register 16. As a result, the total for K signal periods is read into microprocessor unit 26 proportional to the phase delay of the AM signal envelope and, therefore, to the value of the group delay.

In the microprocessor unit 26, using this code and the known value of the quantization frequency, the value of the group delay F ° NЈЈ / (KTKB) is calculated. This measurement and processing algorithm requires a minimum of computational operations to estimate the GDT at any arbitrary modulation frequency, which also contributes to

measurement accuracy. An immediate countdown of the control group can be provided regardless of the modulation frequency.

In known meters, the value of the group delay

calculated through measured value

phase shift in degrees and modulation frequency

in accordance with the algorithm b (360F). This algorithm requires an exact value of the F modulation frequency and measurement (calculation) of the phase shift value φ ° according to the NCJ code value, which in most cases is accompanied by additional errors, there is also no possibility of directly reading the GDT at arbitrary modulation frequencies.

As a block 32 converting the phase shift into time intervals, trigger converters can be used.

Q or overlapping converters. The interval-to-code conversion unit 33 usually contains quantization elements and measurement counters (according to the number of time sequences to be converted

with intervals).

The repetition of measurement cycles is carried out on the Start signal, which is fed automatically from the microprocessor unit 26 as in the measurement of the group delay in one

Q point is the same as in the case of automatic deactivation of the blackboard GHD, when the value of the frequency of the discretely tunable generator 1 changes with a predetermined step. The start can also be performed manually through

5 control panel register 25. If it is necessary to change any parameters of the test signal, operating mode or parameters of the meter, also via the register 25 of the operator control panel, the Q gives the interrupt request signal to the microprocessor unit 26. The individual parameters of the test signal and meter (frequency, amplitude, attenuation of attenuators) may not change only with

5 using a microprocessor unit 26, but also autonomously with the help of the controls of the respective instruments.

All nodes of the proposed meter are implemented on the basis of standard and non-standard measuring means, which are performed on serial digital and analog integrated circuits. As a discretely-loopable oscillator 1 in the frequency range (1-1000) MHz can

5, synthesizers-generators of type 46-71, G4-176 or G4-180 should be used, with the modulator 3 and the attenuator for adjusting the level of the test signal may be part of this generator (except 46- / 1). Two phase generator 2 can be either

standard (for example, F1-4), and specialized. There are also standard code-controlled attenuators 7. Thus, by introducing new elements and connections, the components of the measurement error caused by the basic error of the phase meter 11 and the two-phase generator 2, the random quantization error of the phase meter 11, the calculation error of the measured parameter due to simplified - the steps of the algorithm for calculating the GD. The quantization error in comparison with the known decreases in K or more times, where K is the number of periods of averaging a signal. With this, it is over 33. As a result, the accuracy of the measurement of the group delay is improved.

Claims (3)

1. Group time delay meter on auth.St. No. 1555697, characterized in that, in order to improve the measurement accuracy, a clock frequency synthesizer and two additional control registers are introduced into it, connected by information inputs and recording inputs to a common system backbone, and information outputs, respectively, to an additional control input of a phase meter and control The input of the clock synthesizer, which is connected by a signal input to the output of the pulse generator, and the output to the clock input of a two-phase generator. 2. Pop-1 meter, characterized in that the phase meter contains series-connected conversion unit 0 five 0 five 0 five phase shift in time intervals, the signal inputs of which are the first and second signal inputs of the phase meter, and a time interval to block code, the output of which is the output of the phase meter data, and the combined quantization inputs of both blocks are the phase meter quantization input, as well as the measuring cycle, the first input of which is the start input of the phase meter, also connected to the input of the initial setup of the time interval to code conversion unit, the second input is an additional control A phase meter input, a third input is connected to the output of a phase shift into intervals, and the output is connected to a control input of a time interval to code conversion unit and is the output of the end of the phase meter measurement. 3. Meter in PP.1 and 2, characterized in that the block forming the measuring cycle contains the element And the counter, D-flip-flop and RS-flip-flop, the output of which is connected to the D-input of the O-flip-flop, R-input - with the output of the counter, and the S-input connected to the R-input of the O-flip-flop and the input of the initial installation of the counter is the first input of the block, the input of the preset of the counter is the second input of the forming unit of the measuring cycle, and the first input of the And element connected to the C-input of D- trigger, is the third input of the measuring cycle shaping unit, the output AND means coupled to the counting input of the counter, and its second input - to the output D-flip-flop, which is the output of the unit generating the measuring cycle.