JPH063901B2 - Clock reproduction circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit used in a communication device that communicates with a digital signal, and particularly generates an alarm signal when no signal is input. The present invention relates to a clock recovery circuit having an alarm circuit.

[Prior Art] Conventionally, a clock recovery circuit of a communication device that performs communication by a digital signal has been configured as shown in FIG. That is, a clock component is extracted from the input digital data signal 1 by the differentiating circuit 5, and the phase component 61, the low-pass filter 62, the DC amplifier 63 for amplifying the control signal, and the voltage-controlled oscillator 64 are used as the phase component. When the clock signal 4 is stabilized by the lock loop circuit 6, the data signal is shaped by the flip-flop circuit 8 and then output as the stable data signal 3, and when the digital data signal 1 is not input. The alarm circuit 9 and the gate circuit 7 operate to stop the output of the clock signal and the data signal. Then, the alarm circuit 9 inputs the digital data signal 1 to the input 91 of the monostable multivibrator 93 as shown in FIG.
If there is no input signal for a predetermined time determined by the resistance 95 and the alarm 95, the alarm output 92 becomes "1" level to indicate the alarm state.

[Problems to be Solved by the Invention] In the above-described conventional clock recovery circuit, since the alarm circuit for detecting no input is branched directly from the data signal line, high-speed data whose waveform is easily affected by changes in impedance. It was not preferable to use it for signal transmission. Further, since the alarm circuit uses a monostable multivibrator to set the time constant, the circuit is complicated.

The present invention has been made in view of the above problems, and it is possible to detect a no-input alarm without adversely affecting the waveform of a data signal, and to provide a clock recovery circuit having a simple alarm circuit configuration. For the purpose of provision.

[Means for Solving Problems] A clock recovery circuit of the present invention comprises a differentiating circuit for differentiating an input digital data signal to extract a clock component, and a phase for receiving the clock component and generating a recovered clock signal. A phase-locked loop circuit, wherein the phase-locked loop circuit divides the digital data signal by a voltage-controlled oscillator that generates the reproduction clock signal, and an output signal of the voltage-controlled oscillator and a reset signal of the output of the differentiating circuit. After that, a phase comparator including a first flip-flop circuit and a smoothing circuit, a low-pass filter that removes a predetermined high-frequency component from the smoothed signal output from the phase comparator, and an output from the low-pass filter are amplified. And a DC amplifier for outputting as a control signal of the voltage controlled oscillator In the case where the digital data signal is input and the phase-locked loop circuit is operating stably, the output voltage is offset to 0 volt, and the output voltage is predetermined when the digital data signal is not input. A direct current amplifier that sets a predetermined voltage value as an alarm signal when the voltage value is output, and outputs the regenerated clock signal when the alarm signal is input through a resistor connected to the output of the direct current amplifier. And a second flip-flop circuit that shapes the digital data signal by using the output of the gate circuit as a clock.

[Operation] The clock recovery circuit according to the present invention uses, as an alarm circuit, a DC amplifier that amplifies a DC signal that is a control signal of the voltage controlled oscillator in the phase-locked loop circuit,
A signal branched from the output of the DC amplifier via a resistor is used as an alarm signal.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 is a circuit configuration diagram of a clock recovery circuit of an embodiment, FIG. 2 is a circuit configuration diagram of a phase comparator, and FIG. 3 is a signal waveform diagram of each part of the phase comparator. In these drawings, 1 is a digital data signal, 2 is an alarm signal to be output to the outside, 3 is an output digital signal, and 4 is a reproduced clock signal. Further, 5 is a differentiating circuit for extracting the rising and falling of the input data signal as a narrow pulse including a clock component, and 6 is a phase comparator (PD) 61 by a first flip-flop circuit 614 with a reset function. , A low pass filter 62, a DC amplifier 63, a voltage controlled oscillator (V
CXO) 64 and a phase-locked loop circuit (P
LL), 7 is a gate circuit, 8 is a second flip-flop circuit, and 10 is a branching resistor.

Therefore, one of the input digital data signals 1 is branched to the differentiating circuit 5 for extracting the clock component,
The other is the output digital data signal 3 that is input to the second flip-flop circuit 8 that removes fluctuations and is shaped and stabilized, and is output together with the reproduction clock signal 4 and the alarm signal 2. Then, the signal branched to the differentiating circuit 5 side is extracted by the differentiating circuit 5 as a narrow pulse signal including the rising and falling edges of the signal, and the phase comparator 6 including the first flip-flop circuit 614.
The flip-flop circuit 614 divides the reproduction clock signal 612 from the voltage controlled oscillator 64 into two by using it as the reset signal 611 of 1.

Since the reset signal 611 temporally changes according to the movement of the extracted clock signal, the duty of the pulse of the divided signal 617a changes correspondingly. This divided signal 6
If 17a is smoothed by a resistor 615 and a capacitor 616, a DC signal 613 whose voltage changes according to the movement of the input signal
a is obtained. This DC 613a becomes the output of the phase comparator 61, passes through the low-pass filter 62, and the DC amplifier 6
3 is supplied. The waveform of each part at this time is as shown in FIG.

Here, when the input digital data signal 1 disappears, the reset signal 611 is not output from the differentiating circuit 5, so the phase comparator 61 completely divides the clock signal 612 by two. As a result, the duty of the output pulse from the phase comparator 61 is as high as 50%, and if this is smoothed, the DC voltage is also increased. Frequency division signal 61 in this case
7b and DC signal 613b are also shown in FIG.

The output of the DC amplifier 63 is the phase-locked loop circuit 6
When is stable, the voltage slightly fluctuates around a constant voltage, but this constant voltage is offset to 0 volt. Further, as described above, when the input digital data signal 1 disappears and the DC voltage of the output of the phase comparator 61 rises and the input of the DC amplifier 63 increases, the output of the DC amplifier 63 becomes excessive and the DC For example, the amplification degree of the DC amplifier 63 of the amplifier 63 is set to be equal to the power supply voltage. More specifically, the amplification degree of the DC amplifier 63 is preset to, for example, 100 times, and the output voltage of the DC amplifier 63 is offset to 0V in a state where the phase-locked loop circuit 6 is operating stably. When the signal 1 is not input, the output voltage of the DC amplifier 63 is preset to the power supply voltage of 12V.

Now, there is a digital data signal 1, and the DC amplifier 63 has
For example, a bias DC voltage of 4.5V, a minute fluctuation of 0.01V
When the signal superimposed with is input, the DC component is offset to the output of the DC amplifier 63, and only the minute fluctuation is output. That is, an amplified minute fluctuation amount of 1 V centered on 0 V is output.

On the other hand, assuming that the digital data signal 1 is not input and the input of the DC amplifier 63 is 6V, it is 4.5 when stable.
It becomes 1.5V higher than V, and this should be amplified and the output of the DC amplifier 63 should be 150V.
Since it is limited to V, 12V is output from the DC amplifier 63.

As described above, in the state where the digital data signal 1 is normally input, the DC amplifier 63 controls the control voltage oscillator 64.
When the digital data signal is not input, the preset power supply voltage of 12 V is output, and the phase-locked loop circuit 6 operates while maintaining its function.

On the other hand, the gate circuit 7 uses the “1” level as the power supply voltage,
The "0" level is set to 0 volt, and the gate circuit 7
The signal of the second input is prevented from passing when the first input of is at "1" level. The output of the DC amplifier 63 is connected as the first input via the resistor 10, and the output of the voltage controlled oscillator 64 is connected as the second input.
By doing so, the signal output through the resistor 10 becomes the "1" level when the input digital data signal 1 disappears, so that the alarm signal 2 remains unchanged.
Can be used as At this time, the gate circuit 7
Is closed, it is possible to control output and stop of the data signal and the clock signal.

[Effects of the Invention] As described above, the present invention does not directly use the digital data signal to detect the non-input of the digital data signal, but maintains the configuration of the conventional phase-locked loop circuit and outputs the output of the DC amplifier. Since the DC signal is branched and used by the resistor, it is possible to prevent the input digital data signal from being adversely affected and to prevent the occurrence of instantaneous interruption of the input voltage to the voltage controlled oscillator. Yes, you can increase the reliability. Also, when the output of the DC amplifier has a predetermined voltage value, it is considered as an alarm "Yes", and the output is used as an alarm signal to branch the output to the voltage controlled oscillator with a resistor. The comparator used for is also unnecessary, and the circuit configuration can be very simple, which is economically effective.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention.
FIG. 1 is a circuit configuration diagram of a clock recovery circuit, FIG. 2 is a circuit configuration diagram of a phase comparator, FIG. 3 is a signal waveform diagram of each part of the phase comparator of FIG. 2, and FIGS. The figure shows a circuit configuration diagram of a conventional clock recovery circuit and a circuit configuration diagram of an alarm circuit. 1: Digital data signal, 2: Alarm signal 3: Output digital data signal 4: Reproduced clock signal, 5: Differentiation circuit 6: Phase lock loop circuit 61: Phase comparator, 63: DC amplifier 614: First flip-flop circuit 7: Gate circuit 8: Second flip-flop circuit 10: Resistor

Claims (1)

[Claims] 1. A differential circuit for differentiating an input digital data signal to extract a clock component, and a phase-locked loop circuit for receiving the clock component and generating a reproduced clock signal, the phase-locked loop circuit comprising: A voltage-controlled oscillator that generates the reproduction clock signal, and a first flip-flop circuit and a smoothing circuit that smoothes after dividing the digital data signal by an output signal of the voltage-controlled oscillator and a reset signal of the output of the differentiating circuit. , A low-pass filter that removes a predetermined high-frequency component from the smoothed signal of the output of the phase comparator, and a DC that amplifies the output of the low-pass filter and outputs it as the control signal of the voltage controlled oscillator. In a clock recovery circuit having an amplifier, the digital data signal is input and When the phase-locked loop circuit is operating stably, the output voltage is offset to 0 volt, and when the digital data signal is not input, the output voltage is set to a predetermined voltage value. The DC amplifier that outputs an alarm signal in the case of output, a gate circuit that inhibits the output of the reproduction clock signal when the alarm signal is input through a resistor connected to the output of the DC amplifier, and a gate circuit of the gate circuit. And a second flip-flop circuit that shapes the digital data signal using the output as a clock.