JPH0637632A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To realize a frequency synthesizer in which the high speed of an inter channel frequency switching time can be attained without damaging a characteristic in a normal state, with respect to a frequency synthesizer which is used for a high frequency multiple channel radio equipment or the like. CONSTITUTION:This device is equipped with first and second phase synchronizing circuits 9 and 16, the second phase synchronizing circuit 16 is equipped with more than one frequency-dividers 12 having a fractional frequency-division, and the first phase synchronizing circuit 9 is equipped with a phase matching circuit as necessary. Thus, it is possible to realize the excellent frequency synthesizer in which the high speed of the inter channel frequency switching time can be attained without damaging the characteristic in the normal state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (PLL) type frequency synthesizer used for high-frequency multi-channel radios and the like and characterized by high-speed frequency pull-in.

[0002]

2. Description of the Related Art A frequency synthesizer is an important constituent element of a multi-channel radio and is widely used in various radio equipments and devices. In recent years, wireless communication is shifting from analog to digital, but the time division multiple access (TDMA) method has been adopted as the communication method, and in the frequency synthesizer, the inter-channel pull-in characteristic. Speeding up is an important issue.

A conventional frequency synthesizer will be described below. FIG. 3 shows the configuration of a conventional frequency synthesizer. In FIG. 3, 1 is a voltage-controlled oscillator whose oscillation frequency changes according to the control voltage, 2 is a high-frequency output terminal, 3 is a frequency divider for dividing the output of the voltage-controlled oscillator 1.
Is a reference oscillator that oscillates a reference signal (usually a temperature-compensated crystal oscillator), 5 is a second frequency divider that divides the output of the reference oscillator 4, 6 is the first and second frequency dividers 3, A phase comparator for detecting the output phase of 5 (usually a digital phase / frequency comparator), 7 is a charge pump that converts the output of the phase comparator 6 into a drive signal for the integrator, and 8 is the output of the charge pump 7. Is an integrator (that is, a loop filter) that removes the high frequency component of and returns to the voltage controlled oscillator 1. These form the phase synchronization circuit 9.

The operation of the frequency synthesizer configured as described above will be described below.

First, during phase synchronization, the output frequency (comparison frequency) and phase of the first and second frequency dividers 3 and 5 match, and the output of the charge pump 7 is in a high impedance state. On the other hand, when the channels are switched, the two output frequencies deviate from each other, but the phase comparator 6 performs a frequency correction operation so as to pull the frequency close to the target frequency, and charges and discharges the loop filter 8 via the charge pump 7 (frequency pull-in mode). . Further, the phase comparator 6 performs a phase correction operation so as to pull in the target frequency, and charges and discharges the loop filter 8 via the charge pump 7 (phase pull-in mode).

The above series of operations is faster as the loop gain is higher, that is, the sensitivity of the voltage controlled oscillator 1 is higher, the frequency division number is smaller (the comparison frequency number is higher), or the time constant of the loop filter is smaller.

[0007]

However, in the multi-channel radio, the comparison frequency is uniquely determined by the channel interval and cannot be set freely. Further, if the sensitivity of the voltage controlled oscillator is increased, the S / N and C / N of the voltage controlled oscillator itself are deteriorated. Also, if the time constant of the loop filter is decreased, the noise bandwidth becomes wider and the S / N ratio of the frequency synthesizer increases. There was a problem that / N and C / N deteriorated.

The present invention solves the above-mentioned problems of the prior art, and provides a frequency synthesizer which realizes speeding up of inter-channel pull-in characteristics while maintaining characteristics such as S / N and C / N in a steady state. The purpose is to do.

[0009]

In order to achieve this object, the present invention firstly provides a multi-channel frequency synthesizer with first and second phase synchronization circuits, and secondly.
In the phase-locked loop circuit, a plurality of frequency dividers having a fractional frequency division number are provided, and secondly, a phase matching circuit is provided in the first phase-locked loop circuit.

[0010]

According to the present invention, since the comparison frequency of the second phase-locked loop can be arbitrarily set and the comparison frequency can be set high and the loop gain can be increased by the above configuration, the frequency can be set by the second phase-locked loop at the time of channel switching. By switching to the first phase-locked loop circuit after switching at high speed, it is possible to shorten the inter-channel frequency switching time without degrading the characteristics such as S / N and C / N in the steady state. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention. In FIG. 1, the components numbered 1 to 9 are the same as those in FIG. 1 is different from that of FIG. 3 in that a third frequency divider 11 that divides the output of the voltage controlled oscillator 1 and one or more frequency division numbers that divide the output of the reference oscillator 4 are used. With a fourth frequency divider 12, a fifth frequency divider 13 for dividing the output of the fourth frequency divider 12, and a second phase for detecting output phases of the third and fifth frequency dividers. Loop filter (integrator) that converts the outputs of the comparator 14 and the second phase comparator 14
The second charge pump 15 is used as the drive signal for the drive circuit 8 and the output of the charge pumps 7, 15 that are the inputs of the loop filter (integrator) 8 is provided with a switch 17 for switching based on the phase-locked circuit switching signal 17A. . The voltage-controlled oscillator 1, the first and second frequency dividers 3 and 5, the reference oscillator 4, the first phase comparator 6, the first charge pump 7, and the loop filter 8 enable the first phase synchronization. The circuit 9 is constructed.

Similarly, the voltage controlled oscillator 1, the third, the fourth,
The fifth frequency dividers 11, 12, 13, the reference oscillator 4, the second phase comparator 14, the second charge pump 15, and the loop filter 8 constitute a second phase locked loop circuit 16.

The operation of the frequency synthesizer configured as above will be described. The fourth frequency divider 12 includes two fractional frequency dividers 12a and 12a for easy understanding of the operation.
The operation will be described in the case where the fifth frequency divider 13 is not provided, assuming that it is configured by b.

First, when switching channels, the frequency is switched by the second phase synchronization circuit 16. At this time, since the characteristics of the first phase-locked loop 9 in the steady state are not impaired, the degree of freedom in setting the sensitivity of the voltage controlled oscillator 1 and the time constant of the loop filter 8 is small. However, the setting of the comparison frequency (frequency division number) of the second phase synchronization circuit 16 is arbitrary,
The loop gain can be significantly increased by increasing the comparison frequency. For example, a case where the comparison frequency is about 4.5 MHz will be described. Here, the frequency is 900M
Switching from Hz to 920 MHz, the reference oscillator 4 is 5
The frequency division number of the third frequency divider 11 is set to 200 MHz. The frequency division number (M1) of the fourth frequency divider 12a is set to 11/10,
By setting the frequency division number (M2) of the frequency divider 12b to 100/99, the output frequency (fr1) of the fourth frequency divider 12 is obtained.
Is 4.5 MHz, and the external output is 900 MHz.
Then, by setting M1 to 14/13 and M2 to 108/107, fr1 becomes 4.599987 MHz and the external output obtains 919.99974 MHz. The deviation generated between the set frequency and the external output frequency depends on the number of stages of the fractional frequency divider 12, and the accuracy can be improved by increasing the number of stages.

As described above, the second phase-locked loop 16 can set the loop gain to a significantly high level, and enables high-speed frequency switching, but this changes the capacitance of the loop filter 8 (integrator). This is a function to precharge the potential of the set frequency at high speed.

After that, the first phase-locked loop 9 is switched through the switch 17, but since a slight frequency shift at the time of switching is within the phase pull-in mode range, a phase matching circuit is provided and the phase matching circuit performs phase matching. By performing, it is possible to lock to the set frequency at high speed.

FIG. 2 is a block diagram of a main part of a frequency synthesizer according to an embodiment of the present invention, which is omitted from the structure of FIG. 1 for convenience of explanation.

The components numbered 1 to 9 in FIG. 2 are the same as those in FIG. Reference numeral 20 is a loop switch for switching between the first charge pump 7 and the loop filter 8, and may be shared with the switch 17 shown in FIG. 1 if necessary. Reference numeral 21 is a first gate circuit provided between the voltage controlled oscillator 1 and the first frequency divider 3, and 22 is a second gate circuit provided between the reference oscillator 4 and the second frequency divider 5. The gate circuit, specifically, the first and second gate circuits 21 and 22 can be configured by a logic circuit such as an AND circuit. Reference numeral 23 is an input of the phase synchronization circuit switching signal 17A, the output of the first frequency divider 3 and the output of the phase comparator 6,
The control circuit controls the loop switch 20 and the gate circuits 21 and 22. The loop switch 20, the gate circuits 21 and 22, and the control circuit 23 constitute a phase matching circuit.

The operation of the phase matching circuit configured as described above will be described. When switching from the second phase-locked loop circuit 16 to the first phase-locked loop circuit 9 shown in FIG. 1, the control circuit 23, which receives the output of the phase comparator 6 and the phase-locked loop switch signal 17A, The gate circuits 21 and 22 for controlling the inputs of the frequency divider 3 of 1 and the second frequency divider 5 are controlled (gate) for the time corresponding to the phase error, and the phase comparator 6
The two inputs of are placed in the same phase. In addition, the control circuit 23 creates a loop control signal that changes with a delay of a certain time from the rising of the phase synchronization circuit switching signal 17A. The loop switch 20 is directly controlled by this loop control signal. By these operations, the phase is adjusted at the beginning of the loop switching control so that the pull-in time is short, and then the normal frequency synthesizer mode is set.

As described above, according to the present embodiment, in the multi-channel frequency synthesizer, the first and second phase synchronization circuits 9 and 16 are provided, and the frequency division number of the fraction is provided in the second phase synchronization circuit 16. By providing one or more frequency dividers each having the above, and by providing the phase matching circuit shown in FIG. 2 in the first phase synchronization circuit 9 as necessary, a frequency synthesizer for performing extremely fast frequency switching can be realized.

Needless to say, the frequency division number of the fourth frequency divider 12 is not limited to the above value and may be set arbitrarily. Further, the number of stages of the fourth frequency divider 12 is also arbitrary. Further, it goes without saying that the phase matching circuit is not limited to this embodiment, and may be any function as long as it has a function of matching the phases of the outputs of the first and second frequency dividers at the time of loop switching.

[0023]

As described above, according to the present invention, in the multi-channel frequency synthesizer, the first and second phase synchronization circuits are provided, and the frequency division number of the fraction is provided in the second phase synchronization circuit. By providing one or more frequency dividers and a phase matching circuit in the first phase-locked loop circuit, high-speed channel frequency switching time can be achieved without spoiling characteristics such as S / N and C / N in steady state. It is possible to realize an excellent frequency synthesizer that can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a main part of a frequency synthesizer according to an embodiment of the present invention.

FIG. 3 is a block connection diagram of a conventional frequency synthesizer.

[Explanation of symbols]

 1 Voltage Controlled Oscillator 2 High Frequency Output Terminal 3 First Divider 4 Reference Oscillator 5 Second Divider 6 First Phase Comparator 7 First Charge Pump 8 Loop Filter 9 First Phase Locked Circuit 11th 3 divider 12 4th divider 13 5th divider 14 2nd phase comparator 15 2nd charge pump 16 2nd phase synchronization circuit 17 switch 20 loop switch 21 gate circuit 22 gate circuit 23 Control circuit

Claims (2)

[Claims] 1. A voltage controlled oscillator for changing an oscillation frequency according to a voltage, a first frequency divider for dividing an output of the voltage controlled oscillator, and a second frequency divider for dividing an output of a reference oscillator. , A first phase comparator for comparing the output phases of the first and second frequency dividers and outputting the result, and a first charge pump for converting the output of the first phase comparator A third frequency divider for dividing the output of the voltage controlled oscillator, and a fourth frequency divider for dividing the output of the reference oscillator, the fourth frequency divider having a division number of one or more. A fifth frequency divider for dividing the output of the fourth frequency divider and a second phase comparator for comparing the output phases of the third and fifth frequency dividers and outputting the result. A second charge pump that converts the output of the second phase comparator into a drive signal for an integrator;
A switch that selectively allows only one of the outputs of the second charge pump to pass, and a high-frequency component of one of the outputs of the first and second charge pumps that is input via the switch to remove the voltage. A frequency synthesizer having an integrator that feeds back to a controlled oscillator. 2. A phase matching circuit for matching the output phases of the first frequency divider and the second frequency divider based on the phase comparison result of the first phase comparator. Frequency synthesizer.