JPH05206848A - Pll synthesizer circuit - Google Patents

Abstract

PURPOSE:To provide a PLL synthesizer circuit capable of speeding up lock-up time in the PLL synthesizer circuit without changing the number of communication channels. CONSTITUTION:The device consists of a reference frequency oscillation means 2, a frequency division means 3, a phase comparison means 4 and a voltage control oscillation means (VCO) 7. The frequency division means 3 is composed of a first frequency division means 31 dividing a reference frequency to be outputted by the reference frequency oscillation means 2 and generating a prescribed reference frequency fr and a second frequency division means 32 dividing a comparison signal fp to be compared with the reference frequency fr to be outputted by a voltage control oscillation means 7 and outputting it. A means 11 changing the frequencies of the reference signal fr and the comparison signal fp during a lock-up operation is also provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer circuit, and more particularly to a PLL synthesizer circuit which operates at a high speed so that an output signal frequency always matches a set frequency.

[0002]

2. Description of the Related Art In recent years, with the progress of mobile communication technology and the generalization of digitalization, high-speed tuning has been required. That is, in the mobile communication system, it is desirable to set as many communication channels as possible within a predetermined frequency band. For that purpose, the channel width of each communication channel, that is, the channel step is set to be narrow. There is a need to.

In the current mobile communication,
The step size of each of the communication channels is, for example, 21.
Some are set to 7 KHz. In a mobile communication system, when a frequency is switched from one frequency channel to another frequency channel, it is necessary to immediately switch the frequency.

Further, even if the frequency used is changed during a call for some reason, it is necessary to immediately return to the original frequency. FIG. 4 shows the configuration of a specific example of such a conventional PLL synthesizer circuit. That is, the PLL synthesizer circuit 1 shown in FIG. 4 has a reference frequency oscillating means 2, a frequency dividing means 3, a phase comparing means 4, a charge pumping means 5, a low-pass filter (LPF) 6 and a voltage controlled oscillating means (VCO) 7. And the frequency dividing means 3 is
The first frequency dividing means 31 for generating a predetermined reference frequency fr by dividing the reference frequency output from the reference frequency oscillating means 2 is compared with the reference frequency fr output from the voltage controlled oscillating means 7. And a second frequency dividing means 32 for outputting the comparison signal fp.

Then, the PLL synthesizer circuit 1 is
The phase comparison means 4 compares the phase of the reference frequency fr with the phase of the comparison signal fp, generates a predetermined voltage according to the phase difference, and responds to the voltage change, the voltage controlled oscillation means (VCO). ) 7 outputs a comparison signal having a changed frequency, the phase comparison means 4 compares the phase difference again, and the operation is repeated to change the frequency of the signal output from the voltage controlled oscillation means 7. The fitting operation is performed so as to match the predetermined set frequency.

In the conventional PLL synthesizer circuit, the time until lockup in the PLL synthesizer circuit, that is, the frequency of the output signal of the voltage controlled oscillator 7 deviates from a predetermined reference frequency. There is a comparison frequency input to the phase comparison means 4 as one of the factors that determine the time (hereinafter referred to as the lock-up time) from when the signal is detected to when it returns to the predetermined reference frequency.

That is, there is a tendency that the higher the comparison frequency input to the phase comparison means 4, the shorter the lockup time. Therefore, when the lock-up time of the PLL synthesizer circuit is shortened and the lock-up is performed at high speed, it is preferable that the reference frequency set for each moving body is high.

For example, if the reference frequency set for one moving body is set in units of 100 KHz, the reference frequency set for each moving body is 21.7, as described above.
The lock-up time can be significantly shortened as compared with the one set in KHz units, but on the other hand, setting the reference frequency large makes the channel step width large, and therefore, There arises a problem that the number of channels that can be set in a predetermined usable frequency band decreases.

That is, the result must be contrary to the trend of narrow band multi-channel in the mobile communication system in recent years.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to remedy the drawbacks of the prior art described above and to speed up the lockup time in the PLL synthesizer circuit without changing the number of channels for communication. The present invention provides a PLL synthesizer circuit capable of doing so.

[0011]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, it is composed of a reference frequency oscillating means, a frequency dividing means, a phase comparing means, a voltage control oscillating means,
In the PLL synthesizer circuit, which operates so as to match the phase difference between the reference signal based on the predetermined reference frequency and the comparison signal based on the comparison frequency output from the voltage controlled oscillator, the reference signal and the comparison signal are compared. P is provided with means for changing the frequency of the signal during the lockup operation.
It is an LL synthesizer circuit.

[0012]

Since the PLL synthesizer circuit according to the present invention employs the above-mentioned technical configuration, a plurality of different frequencies are used in the lockup operation process until the lockup is detected. When a reference frequency is prepared and the unlocked state of the PLL synthesizer circuit is detected, that is, when the frequency of the output signal from the voltage controlled oscillation means 7 deviates from the set reference frequency, the phase difference thereof is generated. The frequency of both signals to be compared by the phase comparing means 4 is changed according to the degree of.

Therefore, when the phase difference between the two signals is large, the frequency of both signals to be compared by the phase comparing means 4 is changed to a high frequency to shorten the time required for the adjustment. , When the phase difference between the two becomes small and the lockup state is approached, by changing the frequency to a low frequency, the operation of setting the phase difference to 0 is refined to improve the accuracy of the matching operation. It will improve.

That is, in the PLL synthesizer circuit according to the present invention, when there is a large phase difference between the two to be compared, a high frequency is used to adjust to near the lockup state in a short time. After that, by performing accurate adjustment using a low frequency, it is possible to shorten the lockup time without increasing the channel width set for each normal mobile unit, It is possible to follow the trend of narrow-band multi-channel.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A concrete example of a PLL synthesizer circuit according to the present invention will be described in detail below with reference to the drawings. Figure 1
FIG. 2 is a block diagram showing a specific example of the PLL synthesizer circuit 1 according to the present invention, as well as a diagram for explaining the principle of the PLL synthesizer circuit 1 according to the present invention.

The PLL synthesizer circuit 1 shown in FIG.
Is a reference frequency oscillation means 2, a frequency division means 3, a phase comparison means 4, a charge pump means 5, a low pass filter (LPF).
6 and a voltage controlled oscillating means (VCO) 7, and the frequency dividing means 3 divides the reference frequency output from the reference frequency oscillating means 2 into a predetermined reference frequency fr.
From the first frequency dividing means 31 for generating and the second frequency dividing means 32 for frequency-dividing and outputting the comparison signal fp to be compared with the reference frequency fr output from the voltage controlled oscillator 7. A PLL synthesizer circuit configured to further include means 11 for changing the frequencies of the reference signal fr and the comparison signal fp during a lockup operation.

As the reference frequency oscillating means 2 of the PLL synthesizer circuit 1 in the present invention, any oscillator can be used as long as it is a known oscillator such as a crystal oscillator and can oscillate at a constant frequency. Further, the frequency dividing means 3 in the present invention divides the frequency of the reference signal output from the reference frequency oscillating means 2 by the frequency dividing means 31 and the frequency of the comparison signal output from the voltage controlled oscillating means 7. It is preferable that the frequency dividing means 32 for dividing the frequency is provided separately,
Further, the frequency dividing means need not necessarily have the same frequency dividing function, and the reference frequency fr of the reference signal and the reference frequency fr of the reference signal to be compared with each other by the phase comparing means 4. The reference frequency output from the reference frequency oscillation means 2 and the frequency of the comparison signal output from the voltage controlled oscillation means 7 are divided so that the frequency fp of the comparison signal compared with Any function can be used as long as it has the function of obtaining.

Further, in the present invention, the means 11 for changing the frequencies of the reference signal fr and the comparison signal fp during the lockup operation is the PLL synthesizer circuit 1 in which the reference signal fr and the comparison signal fp are compared. When there is a phase difference between the respective frequencies of the signal fp, a predetermined process is executed in the direction of eliminating the phase difference. The means 11 is, for example, the phase comparison means 4 and the PLL. Lockup detection means 8 for detecting whether or not the synthesizer circuit is in a state close to a lockup state is provided, and frequency switching means 91, 92 are provided between the frequency dividing means 31, 32 and the phase comparison means 4. It may be provided.

In the above specific example of the present invention,
The frequency switching means 91, 92 are preferably configured to be controlled by the output signal of the lockup detecting means 8. The lock-up detection means 8 in the PLL synthesizer circuit 1 according to the present invention includes a reference frequency fr of the reference signal that is compared with each other by the phase comparison means 4 and a comparison signal that is compared with the reference frequency fr of the reference signal. Frequency f
When p is not the same, the phase difference is present in the unlocked state, and the phase difference is equal to or higher than the predetermined level, the predetermined first signal is output and the phase difference is output. Is less than or equal to a predetermined level, that is, when the phase difference between the two approaches and enters a predetermined permissible region, and an accurate adjustment operation is required, a predetermined second signal is output. It is preferably configured.

For example, the first signal may be an "H" level signal and the second signal may be an "L" level signal. The predetermined level of the phase difference in the PLL synthesizer circuit according to the present invention is not particularly limited, but is within a range of, for example, 10 to 20% with respect to the frequency at which the predetermined lockup state is achieved. It is also possible to use the phase difference as a guide.

On the other hand, the frequency switching means 91, 92 have a plurality of switching terminal portions and are connected to the plurality of output terminals of the corresponding frequency dividing means 31, 32, respectively. In the specific example shown in FIG. 1, both frequency dividers are divided into quarter frequency dividing terminals A,
A'and 1/16 frequency dividing terminals B, B'are provided, and the frequency switching means 91, 92 have terminals 93, 94 connected to the output terminals of the frequency divider.

The frequency switching means 91, 92 are
An input terminal section which is connected to the 1/4 frequency dividing terminals A and A'of the frequency dividing means by the first signal of the lockup detecting means 8 and inputs signals having frequencies fr 'and fp', respectively. When 93 is operated, a signal having the frequencies fr 'and fp' is input to the phase comparison means 4. On the other hand, the frequency switching means 91, 92 receives the second signal from the lockup detecting means 8 to divide the frequency dividing means into 1/16 frequency dividing terminals B,
The input terminal portion 94, which is connected to B ′ and inputs the signals having the frequencies fr and fp, respectively, is activated, and the frequency f
A signal having r and fp is input to the phase comparison means 4.

In the present invention, the output from the frequency dividing means is not limited to two places, and signals of different frequencies are taken out from two or more places and compared. Is also good. Then, in the PLL synthesizer circuit 1, when the unlocked state is detected by the lockup detecting means 8 and the phase difference is greater than the predetermined level, the first state of the lockup detecting means 8 is detected. Signal, the frequency switching means 91, 92 are connected to the quarter frequency dividing terminals A, A'of the frequency dividing means, and signals having frequencies fr 'and fp' are fed to the phase comparing means 4. Since it is input, the phase comparison means 4 operates at a frequency higher than the channel frequency, and the phase difference is compared and detected in a large channel step. Therefore, as shown in the area H of FIG. In addition, the lock-up time obtained by the conventional PLL synthesizer circuit (graph J
It is possible to reduce the phase difference at a higher speed and to approach lockup than that of the reference).

After that, when the phase difference between the two becomes less than a predetermined level, the lockup detecting means 8 outputs a second signal, whereby the frequency switching means 91, 92 are switched and the frequency dividing means. 1/16 frequency division terminal B of
Signals connected to B ′ and having frequencies fr and fp, respectively, are input to the phase comparison means 4. Therefore, as shown in the area of the graph H in FIG. 2, the phase difference can be detected and the lock-up operation by the phase difference can be compared by the narrow channel steps to set the correct lock-up state.

The lock-up operation time in the area of the graph H of FIG. 2 is the same as that of the conventional lock-up operation as shown in the graph J of FIG. Since it is shortened to, the lock-up process can be performed at a higher speed than the conventional one as a whole. still,
FIG. 2 is a graph showing the time until the voltage V1 of the voltage controlled oscillator 7 in the unlocked state is changed to the voltage V2 in the locked-up state in the PLL synthesizer circuit, which is a conventional PLL synthesizer. The change time due to the circuit is shown in graph J, and the change time due to the PLL synthesizer circuit according to the present invention is shown in graph H.

FIG. 3 shows an example of the configuration of the switching means 91, 92 used in the PLL synthesizer circuit according to the present invention. That is, in FIG. 3, the frequency divider 3 and the switching means 9 are used.
1 and 92 are provided, and the frequency divider 3
Is composed of, for example, four flip-flops 41 to 44, and divides the frequency of the signal input to the input IN by 1/2.

Therefore, from the output A of the second flip-flop 42 of the frequency divider 3, the frequency of the input signal is 1
A frequency divided by / 4 is output, and a frequency obtained by dividing the frequency of the input signal by 1/16 is output from the output B of the fourth flip-flop 44. On the other hand, in the switching means 91, 92, the NOR gate circuit 50 to which the signal LD from the lockup detecting means 8 and the output A of the second flip-flop 42 of the frequency divider 3 are input, and the NOR gate circuit 50. The AND gate circuit 51 to which the signal LD from the lockup detecting means 8 and the output B of the fourth flip-flop 44 of the frequency divider 3 are input, and further, the output of the NOR gate circuit 50 and the AND gate circuit. The output of the OR gate circuit 52 is connected to the respective input terminals of the phase comparison means 4.

Further, one of the outputs of the voltage controlled oscillator 7 of the PLL synthesizer circuit 1 in FIG. 1 is connected to an appropriate communication circuit.

[0029]

Since the PLL synthesizer circuit according to the present invention has the above-described configuration, it is possible to perform the operation within a fixed time as compared with the conventional PLL synthesizer circuit.
By changing the comparison frequency, and particularly by increasing the comparison frequency, the lock-up time can be shortened and the speed can be increased without changing the number of channels.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of a PLL synthesizer circuit according to the present invention, and is a block diagram showing a configuration of a specific example of a PLL synthesizer circuit according to the present invention.

FIG. 2 is a graph comparing lockup times in a PLL synthesizer circuit according to the present invention and a conventional PLL synthesizer circuit.

FIG. 3 is a block diagram illustrating an example of a configuration of a switching unit used in the PLL synthesizer circuit according to the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of a conventional PLL synthesizer circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... PLL synthesizer circuit 2 ... Reference frequency oscillation means 3, 31, 32 ... Frequency division means 7 ... Voltage control oscillation means 8 ... Lockup detection means 91, 92 ... Switching means 41-44 ... Flip-flops

Claims (4)

[Claims] 1. A reference signal comprising a reference frequency oscillating means, a frequency dividing means, a phase comparing means, and a voltage control oscillating means. In a PLL synthesizer circuit that operates so as to match the phase difference with a comparison signal based on the PLL, means for changing the frequencies of the reference signal and the comparison signal during the lockup operation is provided. Synthesizer circuit. 2. The frequency dividing means divides the reference frequency output from the reference frequency oscillating means, and the frequency dividing means divides the frequency of a comparison signal output from the voltage controlled oscillating means. 2. The PLL synthesizer circuit according to claim 1, wherein and are individually provided. 3. The PLL according to claim 1, wherein the phase comparing means is provided with lockup detecting means for detecting whether or not the PLL synthesizer circuit is in a state close to a lockup state. Synthesizer circuit. 4. A frequency switching means is provided between the frequency dividing means and the phase comparing means, and the frequency switching means is configured to be controlled by an output signal of the lockup detecting means. PL according to claim 1, characterized in that
L synthesizer circuit.