JPH0354917A - Phase locked loop type frequency synthesizer - Google Patents

Abstract

PURPOSE:To reduce a reference frequency level down to a normal mode level by increasing the frequency of a reference signal supplied to a PLL at first to change the output frequency of a VCO and then gradually reducing the reference frequency. CONSTITUTION:The phase locked loop type frequency synthesizer is constituted of a reference signal generator 1, the 1st variable frequency divider 2, a phase comparator 3, a loop filter 4, a voltage controlled oscillator 5, and the 2nd variable frequency divider 6. A frequency dividing ratio control means 7 sets up frequency dividing ratios M, N to small values at the time of switching the frequency to a required value to set up a rapid mode, and while holding an objective frequency value close to the frequency value through one step or more, successively switches the M and N values and finally changes the mode to the normal mode. It is preferable not to set up the time required for each step to a value shorter than the reference frequency of the step, i.e., the period of an output signal from the 1st variable frequency divider 2.

Description

[Detailed Description of the Invention] [Summary] Regarding a phase-locked frequency synthesizer, the purpose of improving the problem of pull-in time in the phase-locked frequency synthesizer is to divide a reference frequency signal by a first frequency division ratio M. a first variable frequency divider that divides the frequency of the output signal of the voltage controlled oscillator by a second frequency division ratio N, and a second variable frequency divider that divides the frequency of the output signal of the voltage controlled oscillator by a second frequency division ratio N; A set M of integers such that frequency division ratio control means for applying I N to the first variable frequency divider and the second variable frequency divider as the first frequency division ratio M and the second frequency division ratio N, respectively; In the phase-locked frequency synthesizer, the frequency division ratio control means, when switching to the desired frequency, starts from a value sufficiently smaller than the M0 and sequentially increases the value through one or more steps to reach M0. The value reached is the first frequency division ratio M
is sequentially applied to the first variable frequency divider, and at the same time, the value at which the frequency at each stage is closest to the desired frequency is applied to the second variable frequency divider.
The structure is such that the frequency dividing ratio N is sequentially applied to the second variable frequency divider.

[Industrial application field]

The present invention relates to a phase-locked frequency synthesizer (PLL synthesizer).

A phase-locked frequency synthesizer is an oscillator that can arbitrarily change the frequency of its output signal according to a given integer value, and is used in radio devices with variable transmitting and receiving frequencies, such as car phones, personal radios, cordless phones, etc. It is widely used as a local oscillator in radio equipment used in mobile communications, or electronic equipment such as electronically tuned radios.

[Conventional technology]

In these fields, as demand increases, the frequency bands used tend to shift to higher frequency bands, and the relative channel bandwidths are becoming increasingly narrower.

FIG. 5 is a diagram showing the basic structure of a well-known phase-locked frequency synthesizer.

In this circuit, when the phase is locked and stabilized, that is, the two signals fr and fp input to the phase comparator 30
When the phases of voltage-controlled oscillator (VCO) 50 match,
The output fout is N times the oscillation frequency of a reference frequency signal generator IO, such as a crystal oscillator, which generates a fixed frequency signal. By giving this N value from another control device, a signal that allows the frequency to be set in predetermined frequency increments can be obtained.

Here, in order to cope with the fact that the frequency band used by electronic devices becomes higher and the relative channel bandwidth becomes narrower as described above, it is necessary to take this N value larger than before. On the other hand, the sensitivity of the phase comparator 30 is KO, VCO 50
Expressing the sensitivity in Kv, the loop gain Ko of the loop composed of the phase comparator 30, loop filter 40, VCO 50, and variable frequency divider 60 is Ko = (Kv-Kn)/N (1) Therefore, the larger the N value, the smaller the loop gain K0.

In other words, if you increase the N value in order to increase the frequency band used and narrow the channel bandwidth, the loop gain will decrease accordingly, and the time to reach phase lock, that is, the pull-in time will become longer. This means that the operating speed of the entire device becomes slower.

This problem is particularly important when applied to MCA (multi-channel access) systems in which a number of users share a common frequency band.

In other words, in the MCA system, M
A channel usage request is sent to the CA control station on a predetermined frequency, and then, when a channel is allocated from the MCA control station, the communication must be started by immediately switching to the allocated frequency. There is also a tendency for the time allowed for this to become stricter, and this trend is particularly noticeable in high-speed digital communications. Therefore, even if a channel is allocated, it is expected that communication will not start in time and communication will not be possible.

As a solution to this problem, the applicant has proposed
No. 1-066011, reference frequency signal generator 1
Another variable frequency divider 20 between 0 and the phase comparator 30
When changing the frequency, the frequency division ratio of the variable frequency divider 60 is sufficiently lowered to increase the loop gain, and at the same time, the frequency divider of the variable frequency divider 20 is also lowered accordingly to quickly change the desired frequency. (high-speed mode), and set the final frequency division ratio when the desired frequency is approached (normal mode).

[Problem to be solved by the invention]

By adopting the above-mentioned structure, a significant improvement in the pull-in time was observed. However, the higher the frequency in high-speed mode is made to shorten the pull-in time, the coarser the frequency increments become, and as a result, the difference between the target frequency in high-speed mode and the final target frequency, that is, the frequency error, increases, and in normal mode A secondary problem has arisen in that the time required to reach phase lock after switching cannot be ignored.

Therefore, an object of the present invention is to further improve the problem of the pull-in time in a phase-locked frequency synthesizer.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle structure of a phase-locked frequency synthesizer according to the present invention.

In the figure, a reference signal generator 1, a first variable frequency divider 2,
phase comparator 3, loop filter 4, voltage controlled oscillator 5,
and the second variable frequency divider 6 are similar to the reference frequency signal generator 10, variable frequency divider 20, phase comparator 30, loop filter 40, VCO 50, and variable frequency divider 60 shown in FIG. It is a structural element with a unique function.

The frequency division ratio control step 7, upon switching to a desired frequency,
Similarly to the above, the frequency division ratios M and N are set small to set the high-speed mode, and then the values of M and N are sequentially switched through l or more steps while maintaining the target frequency close to the desired frequency, and finally the This is to shift to normal mode.

In addition, the time of each stage is based on the reference frequency at that time, that is, the first
It is preferable not to make the period shorter than the period of the output signal of the variable frequency divider 2.

[For production]

The frequency can be quickly switched by gradually reducing the frequency error by gradually approaching the normal mode instead of shifting from the high-speed mode to the normal mode all at once.

〔Example〕

FIG. 2 shows an example in which the present invention is applied to pulse swirl one-way PLL frequency synthesis.

Components that are the same as those in FIG. 5 are given the same reference numerals and their explanations will be omitted.

The variable frequency dividers 62, 64 and the prescaler 66 constitute a well-known pulse swallow type prescaler, and if their frequency division ratios are respectively Nx, NA, and N, then the frequency division ratio N of the entire prescaler is N=NN x Np. +NA (2) is given.

Here, an example will be described in which the frequency is changed to 800.08125 MHz in the 8QQMHz band with a bandwidth of 6.25 k}Iz. In Table 1, the oscillation frequency of the reference frequency signal generator 10 is 8 MHz, and when changing the frequency, the value of fr is initially set to 100 kHz high-speed mode, 64 kHz,
40kHz, 25k}Iz, 12. It represents the numerical values etc. given to each variable frequency divider 20, 62.64 when changing over four stages of 5 kHz and finally setting the normal mode of 6.25 kHz.

Table 1 M N,t NP NAN fr[kHz]80 6
2 128 65 8001 100125 97 1
28 B5 12501 64200 156 128
34 20002 40320 250 128 3
32003 25640 500 128 7 64
007 12.51280 1000 128 13
128013 6.25fr X N [MHz] 800. 1 800. 064 800. 08 800. 075 800. 0875 800. 08125 FIG. 3 is a diagram showing the magnitude of frXN, that is, the target frequency at each setting stage shown in Table 1. The final target of 800 is indicated by the dashed line in the target value of each stage.
．． It is understood that the deviation from 08125 MHz, that is, the frequency error, gradually becomes smaller, and the high-speed mode shifts to the normal mode in stages.

FIG. 4 is a diagram schematically showing the operation of the circuit of FIG. 2 when each frequency division ratio is given stepwise as shown in Table 1 and FIG.

Column (a) shows the frequency division ratio M from the control device 70. N. and N.A.
represents the timing at which is given. As mentioned above, it is preferable that the time interval be shorter than the output signal period of the variable frequency divider 20 at that time.

Column (b) represents each period of the signal fr, that is, the timing at which the output of the phase comparator 30 is updated, and column (C) represents the state of change in the frequency of the output fout of the frequency synthesizer.

At each timing when the division ratio shown in column (a) is given, (b
) column, the timing of updating the output of the phase comparator 30 spreads out, so the loop gain becomes smaller, but the third
As shown in the figure, since the control target value becomes closer to the final value, the pull-in is completed in a relatively short time as shown in column (C).

[Effects of the Invention] As explained above, according to the present invention, the frequency of the reference signal supplied to the PLL loop is increased first to move the VC○ output frequency, and then the reference frequency is gradually lowered. This makes it possible to lower the VC○ output frequency to the reference frequency of the normal mode while suppressing frequency jumps.

By adjusting the VCO output frequency while correcting it to the desired frequency, the frequency switching time can be significantly shortened.

Further, since there is no need for any special circuit for high-speed switching and only a slight change in data is required, effects such as lower operating costs of the device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle structure of the present invention, FIG. 2 is a diagram showing the circuit structure of an embodiment of the present invention, and FIG. 3 is an example of the target frequency at each stage of setting according to the present invention. FIG. 4 is a diagram for explaining the operation of an embodiment of the present invention. FIG. 5 is a diagram showing the basic structure of a phase-locked frequency synthesizer. In the figure, 1.10... reference frequency signal generator, 2. 6.
20, 60, 62. 64...Variable frequency divider, 3
．． 30... Phase comparator, 4.40... Loop filter, 5.50... Voltage controlled oscillator, 66... Brisscaler.

Claims (1)

[Claims] 1. A reference frequency signal generator (1) that is a phase-locked frequency synthesizer and outputs a signal of a predetermined reference frequency.
, a first variable frequency divider (2) that divides the signal of the reference frequency by a first frequency division ratio M and outputs the result, and one input of the first variable frequency divider (2). a phase comparator (3) that receives an output signal and outputs a voltage signal according to the phase difference with the signal input at the other input; and the phase comparator (3)
a loop filter (4) that passes only low frequency components of the output signal of the loop filter (4), and a voltage controlled oscillator (5) that outputs a signal with a frequency corresponding to the output voltage of the loop filter (4) as an output of the frequency synthesizer; The voltage controlled oscillator (5)
a second variable frequency divider (6) that divides the frequency of the output signal by a second frequency division ratio N and supplies the divided signal to the other input of the phase comparator (3); and an output of the frequency synthesizer. The first variable frequency divider (2) and the second frequency divider (2) set the set of integers M_0 and N_0 whose frequency is the desired frequency as the first frequency division ratio M and the second frequency division ratio N, respectively. In the phase synchronized frequency synthesizer, the frequency division ratio control means (7) is configured to apply the frequency division ratio to the variable frequency divider (6), when switching to the desired frequency. Starting from a value sufficiently smaller than M_0, the value is sequentially increased through one or more steps, and the value reaching M_0 is sequentially applied to the first variable frequency divider (2) as the first frequency division ratio M, and at the same time A phase synchronized frequency synthesizer characterized in that a value at which the frequency at each stage is closest to the desired frequency is sequentially applied as a second frequency division ratio N to the second variable frequency divider (6).