JPH0637251A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0637251A
JPH0637251A JP18687192A JP18687192A JPH0637251A JP H0637251 A JPH0637251 A JP H0637251A JP 18687192 A JP18687192 A JP 18687192A JP 18687192 A JP18687192 A JP 18687192A JP H0637251 A JPH0637251 A JP H0637251A
Authority
JP
Japan
Prior art keywords
layer
elements
substrate
semiconductor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18687192A
Other languages
Japanese (ja)
Inventor
Yoshikazu Nakagawa
義和 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP18687192A priority Critical patent/JPH0637251A/en
Publication of JPH0637251A publication Critical patent/JPH0637251A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a semiconductor device of a structure, wherein a chip size is made small and at the same time, the degree of freedom of layout of elements can be improved, and moreover, having superior high-frequency characteristics. CONSTITUTION:Active elements are formed on the surface of a semiconductor substrate 1, a plurality of kinds of passive elements are respectively formed on the active elements via insulating films 5, 8 and 14 in a multilayer and the passive elements 7, 10 and 16 are different from each other in kind in each layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関する。さ
らに詳しくは、キャパシタやインダクタが回路に沢山組
み込まれるマイクロ波集積回路などで、チップサイズを
小さくするとともに素子のレイアウトの自由度を向上さ
せることができる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device such as a microwave integrated circuit in which a large number of capacitors and inductors are incorporated in a circuit, which can reduce the chip size and improve the degree of freedom in element layout.

【0002】[0002]

【従来の技術】主としてマイクロ波帯の信号処理を行な
うMMIC(Monolithic Microwave IC) は、図2に示さ
れるように、GaAsなどの半絶縁性半導体基板に、高
周波増幅器としての電界効果トランジスタ(以下、FE
Tという)や検波用のショットキバリアダイオードなど
の能動素子や抵抗(半導体抵抗)が形成され、基板表面
には絶縁膜を介して伝送線路、キャパシタ、インダクタ
などの回路素子が形成されてモノリシックに集積化した
マイクロ波回路である。このMMICでは前記FET、
ダイオードなどが一平面上に分散して配置されている。
2. Description of the Related Art As shown in FIG. 2, an MMIC (Monolithic Microwave IC) which mainly performs signal processing in a microwave band is formed on a semi-insulating semiconductor substrate such as GaAs on a field effect transistor (hereinafter referred to as a high frequency amplifier). FE
T) and Schottky barrier diode for detection, and resistors (semiconductor resistors) are formed, and circuit elements such as transmission lines, capacitors, and inductors are formed on the surface of the substrate through an insulating film, and monolithically integrated. It is a converted microwave circuit. In this MMIC, the FET,
Diodes and the like are dispersed and arranged on one plane.

【0003】ところで、GaAs基板やSi基板などの
半導体基板に形成する必要があるのは、FET、ダイオ
ードおよび半導体抵抗だけであるが、従来のMMICで
はこれら以外のインダクタやキャパシタなどもFETな
どと配線で接続して回路を形成しなければならないた
め、半導体基板のFETなどが形成されていない表面に
絶縁膜を介して形成されている。
By the way, it is necessary to form only a FET, a diode and a semiconductor resistor on a semiconductor substrate such as a GaAs substrate or a Si substrate, but in the conventional MMIC, other inductors, capacitors and the like are also wired with the FET and the like. Since a circuit must be formed by connecting with each other, it is formed on the surface of the semiconductor substrate on which the FET and the like are not formed, via an insulating film.

【0004】[0004]

【発明が解決しようとする課題】従来のMMICは、こ
のように全回路素子が平面的に形成されているため、チ
ップ面積が大きくなるとともに素子のレイアウトの自由
度が低いという問題がある。また、同一平面上に回路素
子が形成されているため、素子間の接続配線も基板上を
はりめぐらす必要があり、長い配線が形成されることに
なる。マイクロ波帯では配線が少し長くなるだけでもイ
ンダクタンスが増加して特性に悪影響を及ぼしたり、ま
た配線相互間で容量が形成されたり、相互干渉などによ
り特性に影響を及ぼし、配線はできるだけ短かくしなけ
ればならないという問題もある。
In the conventional MMIC, since all the circuit elements are formed in a plane as described above, there is a problem that the chip area becomes large and the degree of freedom of element layout is low. In addition, since the circuit elements are formed on the same plane, the connection wiring between the elements also needs to be laid out on the substrate, and a long wiring is formed. In the microwave band, even if the wiring becomes a little longer, the inductance increases and adversely affects the characteristics.In addition, capacitance is formed between the wirings, and the characteristics are affected by mutual interference, etc., so the wiring should be as short as possible. There is also the problem of having to do so.

【0005】本発明は、叙上の事情に鑑み、チップ面積
を小さくして素子のレイアウトの自由度を向上させるこ
とができると共に動作特性に悪影響を及ぼさないコンパ
クトな回路を形成できる半導体装置を提供することを目
的とする。
In view of the above circumstances, the present invention provides a semiconductor device capable of reducing the chip area to improve the degree of freedom of element layout and forming a compact circuit which does not adversely affect the operating characteristics. The purpose is to do.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板表面に能動素子が形成されており、該半導体
基板表面上に絶縁膜を介して複数種類の受動素子が多層
に形成されており、前記受動素子は各層毎に種類が異な
ることを特徴としている。
The semiconductor device of the present invention comprises:
An active element is formed on the surface of a semiconductor substrate, a plurality of types of passive elements are formed in multiple layers on the surface of the semiconductor substrate through an insulating film, and the passive elements are different in type for each layer. There is.

【0007】[0007]

【作用】本発明によれば、半導体層を必要としな受動素
子を、能動素子が形成された半導体基板表面上に絶縁膜
を介して積層して形成しているため、各素子間の距離が
近く接続配線が短くなる。その結果、とくに高周波で問
題になる接続配線による相互干渉、ノイズの拾得、浮遊
容量、インダクタンスの発生などを防止でき高周波特性
が向上する。
According to the present invention, since the passive element which does not require the semiconductor layer is formed on the surface of the semiconductor substrate on which the active element is formed via the insulating film, the distance between the elements can be reduced. Shorter connection wiring nearby. As a result, it is possible to prevent mutual interference due to connection wiring, noise pickup, stray capacitance, inductance generation, etc., which are particularly problematic at high frequencies, and high frequency characteristics are improved.

【0008】[0008]

【実施例】つぎに添付図面を参照しつつ本発明の半導体
装置を詳細に説明する。図1は本発明の半導体装置の一
実施例の断面説明図である。
The semiconductor device of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional explanatory view of an embodiment of the semiconductor device of the present invention.

【0009】図1において、1はGaAs基板、Si基
板などの半導体基板であり、該基板1の表面側にはFE
T2、ダイオード(図示せず)および半導体抵抗4が形
成され、さらに表面に各電極が形成され、必要な配線2
a、2b、4a、4bが行われている。FET2はSi
基板のばあいには表面に絶縁膜を介してゲート電極が形
成され、その両側に前記半導体層と異なる導電型の不純
物領域を形成して、ソース、ドレイン領域とすることに
より形成されたり、GaAsなどの半絶縁性基板表面に
不純物含有半導体層を形成してその表面にソース、ゲー
ト、ドレインの各電極を形成することなどにより形成す
ることができ、ダイオードはたとえばGaAsなどの半
導体層上にTi/Pt/AuやAlのような金属材料を
直接被膜し、ショットキバリアダイオードを形成した
り、またはpn接合の形成などにより形成することがで
きる。また半導体抵抗4は半絶縁性の半導体基板に濃度
の低い不純物濃度層を形成することにより、所望の抵抗
値の抵抗を形成することができる。
In FIG. 1, reference numeral 1 is a semiconductor substrate such as a GaAs substrate or a Si substrate, and the front side of the substrate 1 is FE.
T2, a diode (not shown) and a semiconductor resistor 4 are formed, each electrode is further formed on the surface, and necessary wiring 2
a, 2b, 4a, 4b are performed. FET2 is Si
In the case of a substrate, a gate electrode is formed on the surface via an insulating film, and an impurity region having a conductivity type different from that of the semiconductor layer is formed on both sides of the gate electrode to form a source / drain region. Can be formed by forming an impurity-containing semiconductor layer on the surface of a semi-insulating substrate such as and forming source, gate, and drain electrodes on the surface, and a diode can be formed on a semiconductor layer such as GaAs by Ti. It can be formed by directly coating a metal material such as / Pt / Au or Al to form a Schottky barrier diode or forming a pn junction. Further, the semiconductor resistor 4 can form a resistor having a desired resistance value by forming an impurity concentration layer having a low concentration on a semi-insulating semiconductor substrate.

【0010】ついで、SiO2 、SiN、SiONなど
からなる第1層間絶縁膜5を熱CVD、プラズマCV
D、スパッタ法などにより基板1の表面に堆積し、えら
れた第1層間絶縁膜5にコンタクト孔を形成する。前記
コンタクト孔内にはコンタクト金属ないしはバイア金属
が埋め込まれて、第1接続配線6を構成している。コン
タクト金属としては電気伝導度の大きなAu、Ag、C
uなどを用いるのが好ましい。前記コンタクト孔は、た
とえばレジストパターン形成後にRIE法などのドライ
エッチング、ウェットエッチングなどのエッチングを行
なうことにより形成される。そして、えられた孔内に蒸
着などによりコンタクト金属を埋め込み、ついでエッチ
ングまたはリフトオフ法などにより孔内以外の金属膜を
除去することにより接続配線を形成することができる。
Next, the first interlayer insulating film 5 made of SiO 2 , SiN, SiON, etc. is subjected to thermal CVD and plasma CV.
D, a sputtering method or the like is deposited on the surface of the substrate 1 to form a contact hole in the obtained first interlayer insulating film 5. A contact metal or a via metal is embedded in the contact hole to form the first connection wiring 6. As the contact metal, Au, Ag, and C having high electric conductivity
It is preferable to use u or the like. The contact hole is formed, for example, by performing dry etching such as RIE or wet etching after forming the resist pattern. Then, a contact metal can be embedded in the obtained hole by vapor deposition or the like, and then a metal film other than the inside of the hole can be removed by etching or a lift-off method to form a connection wiring.

【0011】第1層間絶縁膜5の厚さは、後述する第2
および第3層間絶縁膜同様、本発明においてとくに限定
されないが、基板表面の各電極が完全に被覆され、絶縁
膜の表面がほぼ平担になる厚さで、通常1〜数μmの範
囲である。
The thickness of the first interlayer insulating film 5 is the second
Similarly to the third interlayer insulating film, although not particularly limited in the present invention, the thickness is such that each electrode on the surface of the substrate is completely covered and the surface of the insulating film is substantially flat, and usually in the range of 1 to several μm. .

【0012】抵抗は半導体抵抗以外にニクロムなどの抵
抗材料を被膜したり、ポリシリコンなどを形成して不純
物をドープして、薄膜抵抗として形成することもでき
る。
In addition to the semiconductor resistance, the resistance can be formed as a thin film resistance by coating a resistance material such as nichrome or forming polysilicon or the like and doping impurities.

【0013】つぎに第1層間絶縁膜5上に薄膜抵抗7を
形成する。具体的には、ニクロムまたは、TaNをスパ
ッタ法により厚さが約500 Å、幅が数〜10μmとなるよ
うに堆積することで形成することができる。そしてそれ
ぞれ前記第1層間絶縁膜5および第1接続配線6と同様
にして、第2層間絶縁膜8および第2接続配線9を形成
する。
Next, a thin film resistor 7 is formed on the first interlayer insulating film 5. Specifically, it can be formed by depositing nichrome or TaN so as to have a thickness of about 500 Å and a width of several to 10 μm by a sputtering method. Then, similarly to the first interlayer insulating film 5 and the first connecting wiring 6, respectively, the second interlayer insulating film 8 and the second connecting wiring 9 are formed.

【0014】つぎに第2層間絶縁膜8上にキャパシタ10
を形成する。具体的には、Ti、PtおよびAuの3層
構造の下側電極11を蒸着法またはスパッタ法により形成
し、この下側電極11上にSiNまたはSiO2 を熱CV
D法、プラズマCVD法、スパッタ法などにより約1000
Åの厚さで堆積させて誘電体膜12を形成する。そして、
この誘電体膜12上に前記下側電極11と同様にして上側電
極13を形成する。ついで、それぞれ前記第1層間絶縁膜
5および第1接続配線6と同様にして、第3層間絶縁膜
14および第3接続配線15を形成する。
Next, the capacitor 10 is formed on the second interlayer insulating film 8.
To form. Specifically, the lower electrode 11 having a three-layer structure of Ti, Pt, and Au is formed by a vapor deposition method or a sputtering method, and SiN or SiO 2 is thermally CV-coated on the lower electrode 11.
About 1000 by D method, plasma CVD method, sputtering method, etc.
The dielectric film 12 is formed by depositing it with a thickness of Å. And
An upper electrode 13 is formed on the dielectric film 12 in the same manner as the lower electrode 11. Then, similarly to the first interlayer insulating film 5 and the first connection wiring 6, respectively, a third interlayer insulating film is formed.
14 and the third connection wiring 15 are formed.

【0015】つぎに前記第3層間絶縁膜14上にインダク
タ16を形成する。具体的には、電気伝導度の大きなA
u、AgまたはCuを蒸着法またはスパッタ法により厚
さ数μmになるように堆積してエッチングまたはリフト
オフ法により、インダクタ16を形成する。なお、厚さを
厚くしたいばあいにはメッキ法により形成すればよい。
Next, the inductor 16 is formed on the third interlayer insulating film 14. Specifically, A with high electrical conductivity
u, Ag, or Cu is deposited by evaporation or sputtering to have a thickness of several μm, and the inductor 16 is formed by etching or lift-off. If it is desired to increase the thickness, it may be formed by a plating method.

【0016】このように、第1層にはGaAsやSiな
どの半導体層が作製上必要である素子だけを形成し、第
2層は薄膜抵抗、第3層はキャパシタ、第4層はインダ
クタという具合に階層によって作製する素子を限定す
る。そして各層のあいだは絶縁膜によって分離し、必要
な部分だけコンタクト孔を利用して上下層の素子を接続
している。このように各層ごとに同じ種類の素子を形成
することにより、各層の製造プロセスは共通化でき、製
造が容易になると共に、各層の厚さがほぼ均一になり、
上層の素子形成が容易になる。
As described above, the first layer is formed with only a device required to manufacture a semiconductor layer such as GaAs or Si, the second layer is a thin film resistor, the third layer is a capacitor, and the fourth layer is an inductor. The elements to be manufactured are limited by the layers. The layers are separated from each other by an insulating film, and the upper and lower layers are connected to each other by using contact holes only in necessary portions. By forming the same type of element for each layer in this way, the manufacturing process of each layer can be made common, the manufacturing becomes easy, and the thickness of each layer becomes substantially uniform,
It is easy to form the upper layer element.

【0017】なお、前述した実施例では、第2層に薄膜
抵抗、第3層にキャパシタ、および第4層にインダクタ
をそれぞれ配置しているが、これらの関係は本発明にお
いて限定されるものではない。したがって第2層にたと
えばキャパシタを配置し、第3層に薄膜抵抗を配置して
もよく、要するに層毎に種類の異なる素子を配置すれば
よい。
Although the thin film resistor is arranged in the second layer, the capacitor is arranged in the third layer, and the inductor is arranged in the fourth layer in the above-mentioned embodiment, the relationship between them is not limited in the present invention. Absent. Therefore, for example, a capacitor may be arranged in the second layer and a thin film resistor may be arranged in the third layer, that is, elements of different types may be arranged for each layer.

【0018】以上説明した実施例では、半導体基板とし
てGaAs基板またはSi基板の例で説明したが、それ
以外にInPなどを使用することもできる。また、薄膜
抵抗材料は前述の例のほか、ポリシリコン膜、Ta、M
oなどでも形成でき、半導体抵抗で形成するばあいには
基板内すなわち第1層に形成することになる。さらにイ
ンダクタなどを形成した最上層の表面にも絶縁膜を形成
することができる。
In the embodiment described above, the semiconductor substrate is a GaAs substrate or a Si substrate, but InP or the like may be used instead. In addition to the above-mentioned examples, the thin-film resistance material is a polysilicon film, Ta,
It can also be formed by using o or the like, and when it is formed by a semiconductor resistor, it is formed in the substrate, that is, the first layer. Furthermore, an insulating film can be formed on the surface of the uppermost layer on which the inductor and the like are formed.

【0019】また前述の実施例では各層間の素子の接続
配線を各層の絶縁膜にコンタクト孔を形成して接続する
例で説明したが、各層の一端側に接続配線を導出し、端
部で相互接続して各素子間の配線をすることもできる。
In the above-mentioned embodiment, the connection wiring of the elements between the respective layers has been described as an example in which the contact holes are formed in the insulating films of the respective layers, but the connection wiring is led out to one end side of each layer and is connected at the end portion. It is also possible to make interconnections between the elements by interconnecting them.

【0020】さらに各層の境界面にアルミニウムのよう
な金属膜を形成してアースに接続することにより各層間
の相互干渉やノイズの影響を防止することができる。
Further, by forming a metal film such as aluminum on the boundary surface of each layer and connecting it to the ground, it is possible to prevent mutual interference between the layers and the influence of noise.

【0021】[0021]

【発明の効果】以上説明したとおり、本発明の半導体装
置では半導体基板上に直接形成する必要のある素子だけ
を当該基板表面に形成し、残りのキャパシタやインダク
タなどの受動素子を絶縁膜を介して基板上に多層構造と
なるように形成している。このため、チップサイズを小
さくすることができる。また回路上近接して配置したい
素子を上下に配置できるので、レイアウトを比較的自由
に行なうことができる。
As described above, in the semiconductor device of the present invention, only the elements that need to be formed directly on the semiconductor substrate are formed on the surface of the substrate, and the remaining passive elements such as capacitors and inductors are provided through the insulating film. Are formed on the substrate so as to have a multilayer structure. Therefore, the chip size can be reduced. Further, since the elements desired to be arranged close to each other on the circuit can be arranged vertically, the layout can be relatively freely performed.

【0022】さらに素子を上下に配置しているので、素
子間の距離が非常に小さく、接続配線が短いため、配線
抵抗の増加や余計なインダクタンス、キャパシタが生じ
なくて済み、相互干渉の影響やノイズの少ない高周波特
性の良い半導体装置をうることができる。
Further, since the elements are arranged one above the other, the distance between the elements is very small and the connection wiring is short, so that it is not necessary to increase the wiring resistance, unnecessary inductance and capacitor, and to prevent the influence of mutual interference. It is possible to obtain a semiconductor device with less noise and good high frequency characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の一実施例の断面説明図で
ある。
FIG. 1 is a cross-sectional explanatory view of an embodiment of a semiconductor device of the present invention.

【図2】従来のMMICの説明図である。FIG. 2 is an explanatory diagram of a conventional MMIC.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 FET 4 半導体抵抗 5 第1層間絶縁膜 6 第1接続配線 7 薄膜抵抗 8 第2層間絶縁膜 9 第2接続配線 10 キャパシタ 14 第3層間絶縁膜 15 第3接続配線 16 インダクタ 1 Semiconductor Substrate 2 FET 4 Semiconductor Resistor 5 First Interlayer Insulation Film 6 First Connection Wiring 7 Thin Film Resistor 8 Second Interlayer Insulation Film 9 Second Connection Wiring 10 Capacitor 14 Third Interlayer Insulation Film 15 Third Connection Wiring 16 Inductor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面に能動素子が形成されて
おり、該半導体基板表面上に絶縁膜を介して複数種類の
受動素子が多層に形成されており、前記受動素子は各層
毎に種類が異なることを特徴とする半導体装置。
1. An active element is formed on a surface of a semiconductor substrate, and a plurality of types of passive elements are formed in multiple layers on the surface of the semiconductor substrate with an insulating film interposed therebetween. A semiconductor device characterized by being different.
JP18687192A 1992-07-14 1992-07-14 Semiconductor device Pending JPH0637251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18687192A JPH0637251A (en) 1992-07-14 1992-07-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18687192A JPH0637251A (en) 1992-07-14 1992-07-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0637251A true JPH0637251A (en) 1994-02-10

Family

ID=16196135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18687192A Pending JPH0637251A (en) 1992-07-14 1992-07-14 Semiconductor device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405948A2 (en) * 1989-06-27 1991-01-02 KABUSHIKI KAISHA KOBE SEIKO SHO also known as Kobe Steel Ltd. Electromagnetic agitating method in mold of continuous casting of slab
KR100345516B1 (en) * 2000-09-05 2002-07-24 아남반도체 주식회사 Radio frequency integrated circuit device and manufacturing method thereof
US8273671B2 (en) 2002-05-23 2012-09-25 Schott Ag Glass material for radio-frequency applications

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405948A2 (en) * 1989-06-27 1991-01-02 KABUSHIKI KAISHA KOBE SEIKO SHO also known as Kobe Steel Ltd. Electromagnetic agitating method in mold of continuous casting of slab
KR100345516B1 (en) * 2000-09-05 2002-07-24 아남반도체 주식회사 Radio frequency integrated circuit device and manufacturing method thereof
US8273671B2 (en) 2002-05-23 2012-09-25 Schott Ag Glass material for radio-frequency applications

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