JP3279282B2 - High frequency semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device used at a high frequency, and more particularly to a high-frequency semiconductor device with reduced power loss.

[0002]

2. Description of the Related Art FIG. 2 is a conceptual diagram of a conventional high frequency semiconductor device. The figure shows a 90
1 shows a schematic diagram of a semiconductor device used in a 0 MHz band. This semiconductor device includes MOSFETs 1, 2, 3, 4, 5, wiring 6 connecting the gates of the MOSFETs, wiring 7 connecting the drains of the MOSFETs, a spiral inductor 8, a MOS capacitor 9, and pads 10 and 11 for bonding. Made up of

FIG. 3 shows a MOSFET of the high-frequency semiconductor device shown in FIG.
It is sectional drawing of a part. In the figure, the Si substrate has a resistivity of 2
On a p-type Si layer 12 having a thickness of 0 mΩ · cm and a thickness of 200 μm, a higher-resistance p-type Si layer 13 having a resistivity of 10 Ω · cm and a thickness of 10 μm is provided.
Are laminated. The metal film 14 is formed on the back surface of the Si substrate. The above-described layer structure of the Si substrate is optimized for manufacturing a MOSFET having desired characteristics. The source n portion 15 includes a source metal 16, p +
It is connected to the low-resistance Si layer 12 via the portion 17. The source n portion 15 and the external circuit are connected through the metal film 14 on the back surface of the substrate. Reference numeral 18 denotes a gate, 19 denotes a drain n part, and 20 denotes a drain finger wiring.

FIG. 4 is a sectional view of a portion of a wiring 7 connecting drains of respective MOSFETs in the high-frequency semiconductor device shown in FIG. According to the drawing, this wiring 7 is the same
Since the substrate under the wiring is manufactured on the substrate and the substrate of the MOSFET portion is used as it is, the Si substrate has a resistivity of 20 mΩ similarly to that of the MOSFET portion shown in FIG.
A resistivity of 10 cm on a p-type Si layer 21 having a thickness of 200 μm and a thickness of 200 μm;
A higher resistance p-type Si layer 22 of Ω · cm and a thickness of 10 μm is laminated, and a metal film 23 is formed on the back surface of the Si substrate. An SiO ₂ film 24 having a thickness of 2 μm is laminated on the Si substrate, and a wiring 25 is formed thereon.

FIG. 5 is an equivalent circuit of the parasitic impedance between the wiring 25 and the metal film 23 in the wiring structure shown in FIG. In the figure, a terminal 26 indicates a wiring, and hereinafter, 27 indicates the capacitance of the SiO ₂ film, 28 indicates the resistance of the high-resistance Si layer, 29 indicates the capacitance of the high-resistance Si layer, and 30 indicates the resistance of the low-resistance Si layer. , 31 represents the capacitance of the low-resistance Si layer, and 32 represents the metal film on the back surface of the substrate. The loss of high frequency power due to the parasitic impedance between the wiring 25 and the metal film 23 in FIG. 4 is generated by the resistors 28 and 30 in FIG.

Here, the capacitance 27, 2
Numerical values per unit area of 9, 31, and resistors 28, 30 are obtained. The capacitance 27 is 17 μF / m ² , and the reactance at 900 MHz is 10 μΩ · m ² . Capacity 29 is 10
μF / m ² , and the reactance at 900 MHz is 1.
8 μΩ · m ² . Capacity 31 520nF / m ^2, and the 900
The reactance at MHz is 0.34 μΩ · mm ² . The resistance 28 becomes 1.0 μΩ · m ² . The resistance 30 is 40 nΩ · mm ²
Becomes That is, the reactance of the capacitance 31 and the resistance 30
Has a numerical value of about 1/100 or less as compared with the other circuit elements in FIG. Therefore, in the equivalent circuit of FIG. 5, setting the resistance 30 to 0Ω is a sufficiently accurate approximation.

FIG. 6 is an equivalent circuit obtained by approximation in the equivalent circuit of FIG. In FIG.
Represents a wiring, 34 represents a capacitance of the SiO ₂ film, 35 represents a resistance of the high-resistance Si layer, 36 represents a capacitance of the high-resistance Si layer, and 37 represents a metal film on the back surface of the substrate. The loss of high frequency power due to the parasitic impedance between the wiring 25 and the metal film 23 in FIG. 4 is generated by the resistor 35 in FIG. That is, the wiring 25
Loss of high frequency power due to parasitic impedance between the metal film 23 and the metal film 23 is mainly caused by dielectric loss of the high-resistance Si layer.
Since the value of the resistor 35 is on the order of 1/10 of the reactance of the capacitance of the SiO ₂ film, the loss due to the resistor 35 cannot be ignored. This loss is
This causes performance degradation of the high-frequency semiconductor device. Similarly, the loss due to the dielectric loss of the high-resistance Si layer also occurs in regions such as the spiral inductor 8 and the bonding pads 10 and 11 in FIG.

As a conventional technique for solving such a problem, there is a method of increasing the thickness of the SiO ₂ film 24 in FIG.
Normally, the thickness of the SiO ₂ film 24 is about 2 μm to 5 μm, but by increasing the thickness to 10 μm or more, the capacity 34 of the SiO ₂ film in the simplified equivalent circuit of FIG. Power loss can be reduced. However, using this prior art increases the fabrication cost due to the deposition of a thick SiO ₂ film. In addition, there is a problem that it is difficult to form a through-hole penetrating the thick SiO ₂ film in a portion other than the wiring portion, or it is impossible to form a fine through-hole, which causes a limitation in layout.

As a conventional technique for solving such a problem, a thick dielectric layer is formed by using a dielectric film such as polyimide which can be formed by a spin coating method or the like instead of the SiO ₂ film in FIG. There is a way. In this case, a thick insulating film can be formed more easily than when a thick SiO ₂ film is deposited. However, in order to use this conventional technique, it is necessary to introduce a new dielectric layer forming process.
Manufacturing costs increase. In general, a dielectric film that can be formed by spin coating has a problem of deterioration in reliability due to its hygroscopicity. Furthermore, it becomes difficult to form a through hole penetrating this thick dielectric film in a portion other than the wiring portion, or it is impossible to form a fine through hole,
There are also problems such as restrictions on the layout.

As a conventional technique for solving this problem, there is a technique described in, for example, Japanese Patent Application Laid-Open No. 08-064770. In this prior art, the Si substrate 21 shown in FIG.
By making the resistivity of 22 higher than 2000 Ω · cm,
The values of the parasitic resistances of the capacitors 29 and 31 in the equivalent circuit of FIG. 5 are sufficiently increased to reduce the loss. However, when this conventional technique is used, although the loss of the high-frequency power in the wiring portion is reduced, there is a disadvantage that the Si substrate in the active device portion also has a large resistivity. For example,
In a MOSFET or the like for amplifying a large power, as shown in FIG. 3, a source 15 is connected to a low-resistance Si substrate 12 via a source metal 16 and a p + portion 17, and the low-resistance Si substrate 12 By taking the ground connection from the back surface, the parasitic source inductance is minimized, and the high-frequency characteristics of the MOSFET are improved.

However, in the prior art described in Japanese Patent Application Laid-Open No. 08-064770, such a structure cannot be adopted, so that the characteristics of the active device deteriorate. Depending on the application of the high-frequency semiconductor device, the characteristics of the active device required for the application may be obtained only by using a low-resistance semiconductor substrate as shown in FIG. Japanese Patent Application Laid-Open No. 08-06647 to reduce loss of high frequency power in wiring
It is not possible to use the conventional technique described in Japanese Patent Publication No.

Further, Japanese Patent Application Laid-Open No. 8-293746 discloses that
There is disclosed a technique for expanding the band of a high-frequency power amplifier by attaching a short stub to the output of a high-frequency transistor. In this technique, an insulating film is used as a dielectric of a microstrip line constituting a short-circuit stub, and a metal film on a silicon substrate is used as a ground plane of the microstrip line, thereby improving broadband characteristics. That is, the low-resistance semiconductor layer is configured to function as a ground.

[0013]

As described above,
According to the technology disclosed in Japanese Patent Application Laid-Open No. 08-064770 and the related art that solves the problems of this technology, loss of high-frequency power caused by dielectric loss of a high-resistance semiconductor layer occurs in a passive element such as a wiring, a spiral inductor, and a bonding pad. appear. This becomes a factor of deteriorating the characteristics of the high-frequency semiconductor device. In addition, the high-resistance semiconductor layer that causes this loss is:
It is optimally designed to produce an active device having desired characteristics. Therefore, it is impossible to reduce the loss of the passive element by changing the design of the high-resistance semiconductor layer.
As a conventional technique for reducing the loss of high-frequency power in the semiconductor layer, a method of increasing the thickness of the dielectric film between the wiring and the semiconductor substrate is conceivable. There are problems such as difficulty in forming a through hole penetrating the film.

Further, the technique described in Japanese Patent Application Laid-Open No. 8-293746 is intended to realize a high-frequency power amplifier having a low voltage and a wide band characteristic by using a short stub having a metal-insulator-metal (MIM) structure. Is what it is. Therefore, this technique has a problem that it is not possible to reduce the loss of the wiring section connecting the active element and the input / output pad of the device.

The present invention has been made in view of the above circumstances, and has as its object to provide a high-frequency semiconductor device which suppresses high-frequency power loss generated in passive elements such as wiring, spiral inductors, and bonding pads. Is to provide.

[0016]

According to a first aspect of the present invention, there is provided a high-frequency semiconductor device comprising: an active element formed on a semiconductor substrate; and an active element formed on the semiconductor substrate. In a high-frequency semiconductor device including a metal wiring and a pad provided for connection to the outside, a semiconductor substrate has a high-resistance semiconductor layer laminated on a low-resistance semiconductor layer, and the metal wiring is formed on the semiconductor substrate. The high-resistance semiconductor layer formed on the formed dielectric layer and including the metal wiring is reduced in resistance.

According to a second aspect of the present invention, there is provided a high-frequency semiconductor device comprising: an active element formed on a semiconductor substrate; and metal wires and pads provided for connecting the active element formed on the semiconductor substrate to the outside. In a high-frequency semiconductor device, a semiconductor substrate is formed by stacking a high-resistance semiconductor layer on a low-resistance semiconductor layer, metal wiring is formed on a dielectric layer formed on the semiconductor substrate, and other than active elements. The high-resistance semiconductor layer in the region is characterized in that the resistance is reduced.

According to a third aspect of the present invention, there is provided a high frequency semiconductor device comprising an active element formed on a semiconductor substrate and a passive element formed on the semiconductor substrate. A high-resistance semiconductor layer is stacked on the layer, a part of the passive element is formed on the dielectric layer formed on the semiconductor substrate, and a region including the passive element formed on the dielectric layer The high resistance semiconductor layer is characterized in that the resistance is reduced.

According to a fourth aspect of the present invention, in the high frequency semiconductor device according to any one of the first to third aspects, the semiconductor substrate is a silicon substrate and the active element is a MOSFET. I do. A high-frequency semiconductor device according to a fifth aspect is the high-frequency semiconductor device according to any one of the first to third aspects, wherein the semiconductor substrate is a silicon substrate, and the active element is a bipolar transistor.

According to a sixth aspect of the present invention, in the high frequency semiconductor device according to any one of the second to fifth aspects, the passive element includes at least a spiral inductor, and a metal connecting the spiral inductor and the element. A high-resistance semiconductor layer in a region including a wiring and a pad for connection to the outside is characterized by a low resistance. A high-frequency semiconductor device according to claim 7 is the high-frequency semiconductor device according to any one of claims 2 to 6, wherein the passive element includes at least a MIM capacitor, a metal wiring connecting the MIM capacitor and the element, and A high-resistance semiconductor layer in a region including a pad for connection to the outside is characterized by being reduced in resistance. The high-frequency semiconductor device according to claim 8 is the high-frequency semiconductor device according to any one of claims 2 to 7, wherein the passive element includes at least a stub, a metal wiring connecting the stub and the element, and an external device. The high-resistance semiconductor layer in the region including the connection pad of (1) is characterized in that the resistance is reduced.

According to a ninth aspect of the present invention, in the high-frequency semiconductor device according to any one of the first to eighth aspects, the means for lowering the resistance of the high-resistance semiconductor layer is formed by impurity doping by ion implantation. It is characterized by being. A high-frequency semiconductor device according to claim 10 is the first embodiment.
9. The high-frequency semiconductor device according to claim 8, wherein the means for lowering the resistance of the high-resistance semiconductor layer is impurity doping by a solid-phase diffusion method. The high frequency semiconductor device according to claim 11 is the high frequency semiconductor device according to any one of claims 1 to 8, wherein the means for lowering the resistance of the high resistance semiconductor layer is impurity doping by a vapor phase diffusion method. There is a feature.

A high frequency semiconductor device according to claim 12 is
12. The high-frequency semiconductor device according to claim 1, wherein the resistivity of the low-resistance semiconductor layer is 1 Ω · cm or less, and the resistivity of the high-resistance semiconductor layer is 1 Ω · cm or more.
It is characterized by having a resistivity of not more than 00 Ω · cm and of a region of the high resistance semiconductor layer where the resistance is reduced is 1 Ω · cm or less.

[0023]

Embodiments of the high-frequency semiconductor device according to the present invention will be described below in detail with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS. The first embodiment is a high-frequency semiconductor device to which claims 1, 4, 9, and 12 in the claims are applied. FIG. 7 is a conceptual diagram of the high-frequency semiconductor device according to the first embodiment of the present invention. In the figure, 38, 39, 40, 41 and 42 are unit MOSFETs each having a finger length of 50 μm. Reference numeral 43 denotes a drain bus line for collecting the drains of these unit MOSFETs. Reference numeral 44 denotes a gate bus line for collecting the gates of these unit MOSFETs. 45 and 46 are bonding pads. The source of each unit MOSFET 38 to 42 is
It is connected to the substrate and is connected to the external circuit from the back surface of the substrate.

FIG. 8 is a sectional structural view of the drain bus wiring portion 43 of FIG. The Si substrate has a resistivity of 10 Ω · cm on a p-type Si layer 47 having a resistivity of 20 mΩ · cm and a thickness of 200 μm.
A higher resistance p-type Si layer 48 having a thickness of 10 μm is laminated, and a metal film 49 is formed on the back surface of the Si substrate.
The layer structure of these Si substrates has MOSFETs with desired characteristics.
Has been optimized to produce Si on Si substrate
An O ₂ film 50 is stacked at 2 μm, and a wiring 51 is formed thereon. In the high-resistance p-type Si layer 48, a portion 52 below the wiring is formed as a low-resistance p-type Si layer by ion implantation, and has a resistivity of 100 mΩ · cm.

FIG. 9 is an equivalent circuit of the parasitic impedance between the wiring 51 and the metal film 49 in the wiring structure shown in FIG. 9 is compared with FIG. 8, the terminal 53 indicates the wiring 51, and 54 indicates the capacitance of the SiO ₂ film 50.
Reference numeral 5 denotes the resistance of the high-resistance Si layer 52 whose resistance has been reduced by ion implantation, 56 denotes the capacitance of the high-resistance Si layer 52 whose resistance has been reduced by ion implantation, 57 denotes the resistance of the low-resistance Si layer 47, and 58 denotes the resistance of the low-resistance Si layer 47. 59 is the capacitance of the resistive Si layer 47 and 59 is the metal film 49
Represents each.

Here, the capacitances 54, 5
Numerical values per unit area of 6, 58 and resistors 55, 57 are obtained. The capacitance 54 is 17 μF / m ² , and the reactance at 900 MHz is 10 μΩ · m ² . Capacity 56 is 10
μF / m ² , and the reactance at 900 MHz is 1.
8 μΩ · m ² . Capacity 58 520nF / m ^2, and the 900
The reactance at MHz is 0.34 μΩ · mm ² . The resistance 55 is 10 nΩ · m ² . The resistance 57 is 40 nΩ · mm ² . Accordingly, since the reactance of the capacitors 56 and 58 has an order of 100 times or more the value of the resistors 55 and 57, in the equivalent circuit of FIG. It turns out that this is a good approximation. Further, the resistance values of the resistor 55 and the resistor 57 are
Since the reactance of 4 is on the order of several hundredths, the resistance 5
The loss of high frequency power due to the resistor 5 and the resistor 57 is so small as to be negligible.

The gate bus line 44 and the bonding pads 45 and 46 shown in FIG. 7 also have the same layer structure as the drain bus line 43 as shown in FIG. The loss of the high-frequency power is so small that it can be ignored. In order to lower the resistance of the high-resistance Si layer, it is necessary to add an ion implantation step. However, the increase in the manufacturing cost due to this step is smaller than that of the conventional technique in which a thick dielectric film is deposited. Remarkably small. Also, in some cases, by using a process for forming an active device, the resistance of a high-resistance Si layer under a wiring can be reduced without an additional process.

Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is described in claims 1, 4, 9, and 12.
Is applied to a high-frequency semiconductor device. FIG. 1 is a conceptual diagram of a high-frequency semiconductor device according to a second embodiment of the present invention. This high-frequency semiconductor device is a grounded-source Si power MOSFET used in the 2 GHz band. Gate width 100μ
Twenty m unit MOSFETs 60 are connected in parallel, and the total gate width is 2 mm. The gate fingers of each unit MOSFET are combined by a gate bus line 62 and connected to external circuits from bonding pads 63 and 64. The drain fingers of each unit MOSFET are combined by a drain bus wiring 61 and connected to external circuits from bonding pads 65 and 66. The direction of the gate finger of each unit MOSFET is a direction orthogonal to the gate bus line 62. Each of the above components is manufactured on one Si substrate.

FIG. 10 is a sectional structural view of the MOSFET in the high-frequency semiconductor device shown in FIG. The figure shows the unit MOSF
This is for three ET regions. Si substrate
P-type low-resistance Si layer 6 with a resistivity of 14 mΩ · cm and a thickness of 150 μm
7, p-type high-resistance S having a resistivity of 30 Ω · cm and a thickness of 6.5 μm
The i-layer 68 has a two-layer structure. The resistivity and thickness of these substrates have been optimized to produce Si MOSFETs with the desired properties.

On the back surface of the Si substrate, a metal film 69 is formed for connection with the outside, and an ohmic connection with the Si substrate 67 is established. 70, 71 and 72 are gate fingers, 73 and 74 are drain n portions, and 75, 76 and 77 are source n portions. Reference numerals 78 and 79 are drain fingers formed of aluminum wiring. Reference numerals 80 and 81 denote source fingers formed of aluminum wiring.
6 and 77 serve to connect p + low resistance Si regions 82 and 83 formed in the p-type high resistance Si layer 68 by ion implantation. The resistivity of the p + low resistance Si regions 82 and 83 is
20 mΩ · cm or less. Therefore, the source is connected to the low-resistance Si substrate 67 via the source fingers 80 and 81 and the p + low-resistance Si regions 82 and 83, and is connected from the back surface of the substrate to the ground of the external circuit. Therefore, the ground inductance is extremely small, and the high frequency characteristics of the MOSFET are improved.

FIG. 11 shows the drain bus wiring portion of FIG.
It is sectional drawing. In the figure, the Si substrate is shown in FIG.
Similar to that of the MOSFET part shown, the resistivity is 14 mΩcm, thickness
A 150 μm p-type low-resistance Si layer 84, a resistivity of 30 Ω · cm,
It has a two-layer structure of a p-type high-resistance Si layer 85 having a thickness of 6.5 μm.
The metal film 86 is formed on the back surface. drain
The bus wiring 88 is formed of aluminum wiring, and is
2μm thick SiO between _TwoIt has a structure sandwiching the membrane 87
You. The width of the drain bus wiring 88 is 30 μm. High
Immediately below the drain bus wiring 88 in the resistance Si layer 85
The 89 area, which is low resistance over a width of 50 μm
This is the resulting p-type low-resistance Si layer. This p-type low resistance Si layer 89
The p + low resistance Si regions 82 and 83 of the MOSFET portion shown in FIG.
It is manufactured in the same process as
An ion implantation method is used. The gate shown in FIG.
Each area of the bus wiring 62 and the pads 63, 64, 65, 66
Also for the drain bus wiring region shown in FIG.
Cross-sectional structure.

By realizing the above structure, it is possible to reduce high-frequency power loss in the drain bus line, the gate bus line, and the pad portion. That is, the characteristics of the high-frequency semiconductor device can be improved. In realizing these structures, the p + low-resistance Si region 89 formed in the high-resistance Si layer 85 is formed by using the same process as that for forming the p + low-resistance Si regions 82 and 83 in the MOSFET portion. Since it is formed, there is no additional step, and the problem of an increase in manufacturing cost, which has been a problem with the conventional technology, has been solved.

Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment is a high-frequency semiconductor device to which claims 2, 5, and 11 in claims are applied. FIG. 12 is a conceptual diagram of a high-frequency semiconductor device according to the third embodiment of the present invention. This high-frequency semiconductor device is a common emitter Si power bipolar transistor used in the 1.5 GHz band. Twenty unit bipolar transistors 90 each having an emitter size of 5 μm × 20 μm are connected in parallel. The base fingers of each unit bipolar transistor 90 are combined by a base bus line 92 and connected to external circuits from bonding pads 93 and 94.

The collector fingers of each unit bipolar transistor 90 are collected by a collector bus wiring 91 and connected to external circuits from bonding pads 95 and 96. Each of the above components is manufactured on one Si substrate. The Si substrate has a structure in which a high-resistance n-type Si layer is laminated on a low-resistance p-type low-resistance Si layer. The bipolar transistor 90 uses a high-resistance n-type layer as a collector,
In addition, p-type bases and n-type emitters are being manufactured. The emitter is connected to the low-resistance p-type Si layer via the p + low-resistance Si region formed in the high-resistance n-type layer, and is connected to the ground of the external circuit from the back surface of the substrate. An impurity doping process using a gas phase diffusion method is used in the step of forming the p + low-resistance Si region in the high-resistance n-type Si layer.

In FIG. 12, regions 97, 98, 99, and 10 for forming a bipolar transistor surrounded by a broken line are shown.
In the region other than 0, the high-resistance n-type Si layer is made p-type by a vapor phase diffusion method, and its resistivity is reduced to about the same level as that of the low-resistance p-type Si layer. This p + low resistance Si region is
P + low resistance Si for connecting the emitter to the p-type low resistance Si layer
In the step of forming a region, the regions are collectively manufactured. Thus, the collector bus wiring 91, the base bus wiring 92 and the bonding pad portions 93, 94,
The loss of high frequency power at 95 and 96 can be reduced. That is, the characteristics of the high-frequency semiconductor device can be improved without increasing the manufacturing cost.

Next, a fourth embodiment of the present invention will be described with reference to FIG. The fourth embodiment is a high-frequency semiconductor device to which claims 3, 4, 6, and 10 in the claims are applied. FIG. 13 is a conceptual diagram of a high-frequency semiconductor device according to the fourth embodiment of the present invention. This high-frequency semiconductor device is a 0.9 GHz band amplifier including a source-grounded Si MOSFET 101, a spiral inductor 103, a MOS capacitor 104, an input terminal 105, and an output terminal 102. Spiral inductor 103 and MOS capacitor 104
Constitutes an input 50Ω matching circuit. Each of the above components is manufactured on one Si substrate.

The Si substrate has a structure in which a high-resistance p-type Si layer is laminated on a low-resistance p-type low-resistance Si layer. MOS
The source of the FET 101 is connected to a low-resistance p-type Si layer through a p + low-resistance Si region formed by a solid-phase diffusion method in a high-resistance p-type layer.
Connected to layers. In each region of the spiral inductor 103, the input terminal 105, the output terminal 102, and the wiring connecting each element, the p-type high-resistance Si layer is reduced in p-type resistance by a solid-phase diffusion method. This process of lowering the resistance is performed by the MOSFET 1
01 and a p + low-resistance Si region prepared for connecting the source of No. 01 to the low-resistance p-type Si layer in the same step and at the same time. Thereby, the loss of the high-frequency power of the spiral inductor 103, the input terminal 105, the output terminal 102, and the wiring connecting each element due to the capacitance with respect to the substrate can be reduced, and the characteristics of the high-frequency semiconductor device can be improved without additional steps. Can be done.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. In the fifth embodiment,
This is a high-frequency semiconductor device to which claims 3, 4, and 7 in the claims are applied. FIG. 14 is a conceptual diagram of a high-frequency semiconductor device according to the fifth embodiment of the present invention. This high-frequency semiconductor device has a common-source Si MOSFET 106, D
C-cut MIM capacitor 107, high-frequency input terminal 108, high-frequency output terminal 109, gate bias resistor 110,
A microwave amplifying element including a bias supply terminal 111. Each of the above components is manufactured on one Si substrate. The Si substrate has a structure in which a high-resistance p-type Si layer is stacked on a low-resistance p-type low-resistance Si layer. The source of the MOSFET 106 is connected to the low-resistance p-type Si layer via a p + low-resistance Si region formed in the high-resistance p-type layer.

FIG. 15 is a sectional structural view of the MIM capacitor 107 shown in FIG. 112 is a low-resistance Si layer, 113 is a high-resistance Si layer
Layer 119 is the back metal layer. The MIM capacitor is formed on a 2 μm thick SiO ₂ layer 14 deposited on a Si substrate, and includes a lower electrode 115, an upper electrode 116, and a dielectric film 117.
The dielectric film 117 is made of SiO ₂ , and has an upper electrode 116 and a lower electrode 11.
The thickness of the dielectric film 117 in the region sandwiched by 5 is 50 nm.

In the high-resistance Si layer 113, a region 118 below the MIM capacitor is a p-type low-resistance Si layer whose resistance has been reduced by p-type doping. This low-resistance p-type low-resistance Si layer 118 is formed collectively in the same step as the p + low-resistance Si region for connecting the source of the MOSFET 106 to the p-type low-resistance layer. In addition, other than the MIM capacity 107,
Similarly, the high-resistance Si layer under the wiring connecting each terminal and each element is similarly reduced in resistance. By the above, without additional process
The loss of high frequency power caused by the parasitic capacitance between the lower electrode of the MIM capacitor and the Si substrate is reduced, and the characteristics of the high frequency semiconductor device are improved.

Next, a sixth embodiment of the present invention will be described with reference to FIG. The sixth embodiment is a high-frequency semiconductor device to which claims 3, 4, 6, 7, and 8 in the claims are applied. FIG. 16 is a conceptual diagram of a high-frequency semiconductor device according to the sixth embodiment of the present invention. This high-frequency semiconductor device includes a source-grounded Si MOSFET 120,
Spiral inductors 121, 122, 123, open stubs 124, 125, MIM capacitors 126, 127, bonding pads 128 for high frequency input, bonding pads 129 for high frequency output, metal thin film resistor 130 for gate bias supply, gate bias supply And a bonding pad 132 for supplying a drain bias.

Each of the above components is manufactured on one Si substrate. The Si substrate has a structure in which a high-resistance p-type Si layer is stacked on a low-resistance p-type low-resistance Si layer. The source of the MOSFET 120 is connected to a low-resistance p-type S-type region through a p + low-resistance Si region formed in a high-resistance p-type layer.
Connected to i layer. The spiral inductor 121 and the open stub 124 constitute an input 50Ω matching circuit. The spiral inductor 122 and the open stub 125 constitute an output 50Ω matching circuit. The spiral inductor 123 is connected to the drain bias supply terminal 1
32 is a drain choke inductor provided for separating the drain of the MOSFET 120 from the drain of the MOSFET 120 at a high frequency.

The MIM capacitors 126 and 127 connect the high-frequency input terminal 128 and the high-frequency output terminal 129 to the MOSFET 12
This is a DC cut capacitance for separating DC from zero. MO
Except for the region where the SFET 120 is manufactured, the p-type doping is performed on the high-resistance p-type Si layer in all the regions including the passive element to reduce the resistivity. This doping step is
The P + low-resistance Si region provided for connecting the source 120 to the low-resistance p-type Si layer is collectively manufactured using the same process as that for manufacturing the P + low-resistance Si region. As a result, the loss of high-frequency power of each circuit component other than the MOSFET due to parasitic capacitance with respect to the Si substrate can be reduced without additional steps, and the characteristics of the high-frequency semiconductor device can be improved.

[0044]

As described above, according to the present invention,
Of the high-resistance p-type Si layer, a portion immediately below the gate bus wiring, the bonding pad, and the drain bus wiring is made into a low-resistance p-type Si layer by an ion implantation method or the like. As a result, the loss of high-frequency power due to the dielectric loss of the high-resistance Si layer can be reduced to a negligible level, and the loss of high-frequency power in the drain bus wiring, the gate bus wiring, and the pad portion can be reduced. That is, the band characteristics of the high-frequency semiconductor device can be improved. In order to lower the resistance of the high-resistance Si layer, it is necessary to add an ion implantation step. However, the increase in the manufacturing cost due to this step is smaller than that of the conventional technique in which a thick dielectric film is deposited. Remarkably small. In addition, by using the process for forming the active device, it is possible to reduce the resistance of the high-resistance Si layer under the wiring without any additional process. In other words, in realizing these structures, the p + low-resistance Si region formed in the high-resistance Si layer must be formed using the same process as that for forming the p + low-resistance Si region in the MOSFET section. Therefore, there is no additional step, and the problem of an increase in manufacturing cost, which has been a problem with the conventional technology, is solved.

The high-frequency semiconductor device according to the present invention realizes a reduction in wiring loss by forming a low-resistance p-type Si layer in a wiring portion connecting an active element and an input / output pad of the device. Therefore, it is possible to reduce the loss of the wiring portion which cannot be realized by the configuration of the short stub in which the low-resistance semiconductor layer functions as the ground as disclosed in Japanese Patent Application Laid-Open No. 8-293746.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a high-frequency semiconductor device according to a second embodiment of the present invention.

FIG. 2 is a conceptual diagram of a high-frequency semiconductor device according to a conventional technique.

FIG. 3 is a sectional view of a MOSFET section of the high-frequency semiconductor device of FIG. 2;

FIG. 4 shows each MO in the high-frequency semiconductor device shown in FIG. 2;
FIG. 4 is a cross-sectional view of a portion of a wiring 7 connecting a drain of an SFET.

5 is an equivalent circuit of a parasitic impedance between a wiring 25 and a metal film 21 in the wiring structure shown in FIG.

FIG. 6 is an equivalent circuit obtained by approximation in the equivalent circuit of FIG.

FIG. 7 is a conceptual diagram of the high-frequency semiconductor device according to the first embodiment of the present invention.

8 is a sectional structural view of a drain bus wiring part 43 of FIG. 7;

9 is an equivalent circuit of a parasitic impedance between a wiring 51 and a metal film 49 in the wiring structure shown in FIG.

FIG. 10 shows a MOSF in the high-frequency semiconductor device shown in FIG.
It is sectional drawing of ET.

11 is a sectional structural view of a drain bus wiring portion of FIG.

FIG. 12 is a conceptual diagram of a high-frequency semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a conceptual diagram of a high-frequency semiconductor device according to a fourth embodiment of the present invention.

FIG. 14 is a conceptual diagram of a high-frequency semiconductor device according to a fifth embodiment of the present invention.

15 is a sectional structural view of the MIM capacitor 107 in FIG.

FIG. 16 is a conceptual diagram of a high-frequency semiconductor device according to a sixth embodiment of the present invention.

[Explanation of symbols]

1, 2, 3, 4, 5 ... MOSFET, 6, 7 ... wiring, 8 ... spiral inductor, 9 ... MOS capacitance, 10, 11 ... bonding pad, 12 ... low resistance p-type Si layer, 13 ... high resistance p
Type Si layer, 14: metal film, 15: source n portion, 16: source metal, 17: p + portion, 18: gate, 19: drain
n part, 20: drain finger wiring, 21: low-resistance p-type Si
Layer, 22: high-resistance p-type Si layer, 23: metal film, 24: SiO ₂
Film, 25: wiring, 26: terminal (wiring), 27: capacitance of SiO ₂ film, 28: resistance of high resistance Si layer, 29: capacitance of high resistance Si layer, 30: resistance of low resistance Si layer, 31: Capacitance of low-resistance Si layer, 32: metal film, 33: terminal (wiring), 34: capacitance of SiO ₂ film, 35: resistance of high-resistance Si layer, 36: capacitance of high-resistance Si layer, 37: metal film, 38, 39, 40, 41, 42 ...
Unit MOSFET, 43: drain bus wiring, 44: gate bus wiring, 45, 46: bonding pad, 47: low resistance p-type Si layer, 48: high resistance p-type Si layer, 49: metal film,
50: SiO ₂ film, 51: wiring, 52: low-resistance p-type Si layer, 5
3: terminal (wiring), 54: capacitance of SiO ₂ film, 55: high resistance
Resistance of Si layer, 56: capacity of low-resistance high-resistance Si layer, 5
7: resistance of low-resistance Si layer, 58: capacitance of low-resistance Si layer, 59
... metal film, 60 ... unit MOSFET, 61 ... drain bus wiring, 62 ... gate bus wiring, 63, 64, 65, 66 ...
Bonding pad, 67 ... Si substrate, 68 ... p-type high resistance S
i-layer, 69: metal film, 70, 71, 72: gate finger, 73, 74: drain n portion, 75, 76, 77: source n portion, 78, 79: drain finger, 80, 81
... Source fingers, 82, 83 ... p + low resistance Si region, 84
... p-type low-resistance Si layer, 85 ... p-type high-resistance Si layer, 86 ... metal film, 87 ... SiO ₂ film, 88 ... drain bus lines, 89 ... p
Type low resistance Si layer, 90 unit bipolar transistor, 9
1: collector bus wiring, 92: base bus wiring, 93,
94, 95, 96 ... bonding pad, 97, 98,
99, 100: Group region of unit bipolar transistor, 101: Common source Si MOSFET, 102: Output terminal, 103: Spiral inductor, 104: MOS capacitance, 105: Input terminal, 106: Common source Si MOSFE
T, 107: MIM capacitance, 108: high frequency input terminal, 109
... High frequency output terminal, 110 ... Gate bias resistor, 1
11: bias supply terminal, 112: low resistance Si layer, 113
... High resistance Si layer, 114 ... SiO ₂ layer, 115 ... Lower electrode, 1
16: upper electrode 117: dielectric film 118: p-type low resistance S
i layer, 119: metal layer, 120: common source Si MOSFET,
121, 122, 123 ... spiral inductor, 12
4, 125: open stub, 126, 127: MIM capacitor, 128, 129: bonding pad, 130: metal thin film resistor, 131, 132: bonding pad

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/082 H01L 27/08 102Z 27/088 29/78 301W 29/78 H03F 3/195 (58) Fields surveyed (Int. (Cl. ⁷ , DB name) H01L 21/822 H01L 21/768 H01L 21/8222 H01L 21/8234 H01L 27/04 H01L 27/082 H01L 27/088 H01L 29/78 H03F 3/195

Claims (12)

(57) [Claims] An active element formed on a semiconductor substrate;
In a high-frequency semiconductor device comprising a metal wiring and a pad provided for connection between the active element and the outside formed on the semiconductor substrate, the semiconductor substrate has a high-resistance semiconductor layer on a low-resistance semiconductor layer. Wherein the metal wiring is formed on a dielectric layer formed on the semiconductor substrate, and the high-resistance semiconductor layer in a region including the metal wiring has a reduced resistance. High-frequency semiconductor device. 2. An active element formed on a semiconductor substrate,
In a high-frequency semiconductor device comprising a metal wiring and a pad provided for connection between the active element and the outside formed on the semiconductor substrate, the semiconductor substrate has a high-resistance semiconductor layer on a low-resistance semiconductor layer. Wherein the metal wiring is formed on a dielectric layer formed on the semiconductor substrate, and the high-resistance semiconductor layer in a region other than the active element has a reduced resistance. High-frequency semiconductor device. 3. An active element formed on a semiconductor substrate,
In a high-frequency semiconductor device including a passive element formed on the semiconductor substrate, the semiconductor substrate is formed by stacking a high-resistance semiconductor layer on a low-resistance semiconductor layer; The high-resistance semiconductor layer formed on a dielectric layer formed on a substrate and including a passive element formed on the dielectric layer has a reduced resistance. Semiconductor device. 4. The high-frequency semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon substrate, and said active element is a MOSFET. 5. The high-frequency semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon substrate, and said active element is a bipolar transistor. 6. The high-frequency semiconductor device according to claim 2, wherein the passive element includes at least a spiral inductor, and includes a metal wiring connecting the spiral inductor and the element, and an external device. A high-frequency semiconductor device in which a high-resistance semiconductor layer in a region including a connection pad has low resistance. 7. The high-frequency semiconductor device according to claim 2, wherein the passive element includes at least a MIM capacitor, a metal wiring connecting the MIM capacitor to the element, and an external device. A high-frequency semiconductor device in which a high-resistance semiconductor layer in a region including a connection pad has low resistance. 8. The high-frequency semiconductor device according to claim 2, wherein the passive element includes at least a stub, and a metal wiring connecting the stub and the element and a connection to the outside. Wherein the high-resistance semiconductor layer in the region including the pad is reduced in resistance. 9. The high frequency semiconductor device according to claim 1, wherein the means for lowering the resistance of the high resistance semiconductor layer is impurity doping by ion implantation. High-frequency semiconductor device. 10. The high-frequency semiconductor device according to claim 1, wherein the means for lowering the resistance of the high-resistance semiconductor layer is impurity doping by a solid phase diffusion method. High-frequency semiconductor device. 11. The high-frequency semiconductor device according to claim 1, wherein the means for lowering the resistance of the high-resistance semiconductor layer is impurity doping by a gas phase diffusion method. High-frequency semiconductor device. 12. The high-frequency semiconductor device according to claim 1, wherein the low-resistance semiconductor layer has a resistivity of 1 Ω · cm or less, and the high-resistance semiconductor layer has a resistivity of 1 Ω · cm or less. Is 1Ω · cm or more and 100Ω
· Cm or less, and the resistivity of the region where the resistance is reduced in the high-resistance semiconductor layer is 1Ω · cm or less.