JPH0636582A - Read circuit - Google Patents

Abstract

PURPOSE:To obtain a read circuit having a ROM with a small chip size without failing in high speed read. CONSTITUTION:An inverter 40 is formed by a pM0S transistor Q38 and an nMOS transistor Q39, the source of the pMOS transistor Q38 is connected to the output node 24 of internal generated source 33. Thus, when an input signal Yn is an L, the pMOS transistor Q38 is turned ON, and the nMOS transistor Q39 is turned OFF and then a VBH is outputted. Further, when the input is an H, the pMOS transistor Q38 is turned OFF, and the nMOS transistor Q39 is turned ON and then GND is outputted. Further, the column line GL of a memory matrix 37 is connected to the output of the inverter 40 directly. Thus, two nMOS transistors arranged on the column line necessary usually are unnecessitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit in a read only memory (ROM), and more particularly in an erasable programmable read only memory (EPROM).

[0002]

2. Description of the Related Art Conventionally, as a reading circuit of this type, there is one described in, for example, Japanese Patent Laid-Open Publication No. 1-130398. As described in this publication, the X cell method, which is a memory cell method of ROM, is a 2-bit simultaneous read method.

Specifically, the column lines in the X cell system are connected to the sources of a pair of memory cells selected in the same row, and the drains of the pair of memory cells are adjacent to the column lines. In the X-cell method, since each bit line is connected to two bit lines, by selecting one column line, this pair of memory cells can be selected simultaneously. Therefore, this method requires at least two data buses.

FIG. 2 shows an embodiment of a conventional read circuit in the X cell system. In the figure, in the memory matrix 37 surrounded by the alternate long and short dash line, the column lines GL and the bit lines BL are arranged alternately. Each memory cell MC developed two-dimensionally is arranged between the column line GL and the bit line BL. That is, in the memory cell MC, the source is connected to the column line GL, the drain is connected to the bit line BL, and the gate is connected to any of the row lines X ₀ , X ₁ ... X _n .

Here, the row line X is a decode signal of a row address, and only one line is selected by the row decoder 34. In addition, the selection signals Y ₁ , Y _{2 ,} . ． ．
Is a decoded signal of the column address by the column decoder 35, and is selectively connected to the gate of the MOS transistor Q _G connected between the column lines GL and GND.

The bit lines BL are adjacent to the column lines G.
At least one MOS transistor Q _B whose gate input is Y _n (n = 1, 2, ...) Which is a selection signal for L
Is connected to one of two different data buses DB. At this time, adjacent bit lines BL are always connected to different data buses.

Reference numeral 33 is an internally generated constant voltage source. The nMOS transistor Q ₁₄ of the constant voltage source 33 is connected between the input node 24 of the inverter formed by the nMOS transistor Q ₁₃ whose load is the pMOS transistor Q ₁₂ and V _CC, and the gate of which is the output node 25 of this inverter. Connected to.

In low voltage source 33, node 24 and GN
A resistor R ₁ is connected between D. The connection relationship between the pMOS transistor Q ₁₂ and the nMOS transistors Q ₁₃ and Q _{14 is the same as} the connection relationship between the pMOS transistor Q ₁₇ and the nMOS transistors Q ₁₈ and Q ₂₀ that form the current sense circuit 36.

Therefore, the dimension ratio of the pMOS transistor Q ₁₂ and the nMOS transistor Q ₁₃ is set to pMO.
If the S transistor Q ₁₇ and the nMOS transistor Q ₁₈ have the same dimension ratio, the potential generated at the node 24 is the same as the data bus DB and the bit line potential at the time of reading when the memory cell is OFF in the steady state. The resistor R ₁ is for preventing the potential of the node 24 from rising due to the subthreshold current of the nMOS transistor Q ₁₄ .

The column line GL is pulled up by an internally generated constant voltage source. That is, between the internally generated constant voltage source 33 and its output node 24 and each column line, the output signal bar Y of the inverter 32 which receives the selection signal of the column line GL is input.
₁ , bar Y ₂ , bar Y ₃ ,. ． ． N as the gate input
The MOS transistors Q ₉ , Q ₁₀ , Q ₁₁ ... Are connected.

The bit line BL is also pulled up by the internally generated constant voltage source 33. Internally generated constant voltage source 33
Has resistors R ₂ and R ₃ connected between the output node 26 and each bit line. These resistors R ₂ and R ₃ are B
The internally generated constant voltage is pulled up regardless of whether L is selected or not selected. Therefore, the current that can flow in the resistors R ₂ and R ₃ must be set sufficiently smaller than the current of the memory cell MC.

The read operation is performed in the selected memory cell MC
Is converted into a change in bit line voltage by the current sense circuit 36, and is output as an amplified voltage.

When the selected memory cell MC is OFF, the potential difference between the node 28 and the output node 27 of the inverter formed by the MOS transistors Q ₁₇ and Q ₁₈ is balanced at the threshold value of the nMOS transistor Q ₂₀ . . That is, since the nMOS transistor Q ₂₀ is off,
_Vcc is output to the node 29.

When the selected memory cell MC is ON, the potential of the node 28 is lowered by lowering the potential of the node 28, and the nMOS transistor Q ₂₀ is turned ON. Therefore, at the output node 29, a current (hereinafter referred to as V _SL ) in which the current flowing through the pMOS transistor Q ₁₉ and the series ON resistance of the nMOS transistor Q ₂₀ and the memory cell are balanced appears.

Next, the operation of the data bus system will be described. The memory cell MC1 has a threshold value higher than V _CC and MC ₂ ,
MC _3, MC ₄ is such that is lower than V _CC, the data is assumed has been written.

First, it is assumed that the X ₁ signal and the Y ₃ signal are at the V _CC level and the other X and Y signals are at the GND level. At this time, the bar Y ₁ and bar Y ₂ signals are at the V _CC level, the bar Y ₃
The signal is at the GND level. Unselected column line GL ₂₁ ,
Since the nMOS transistors Q _G5 , Q _B6 , Q _B7 and Q _G8 are OFF and the nMOS transistors Q ₉ and Q ₁₀ are ON, the GL ₂₃ and the bit line BL ₂₂ have the same potential as the node 24 and the node 26.

Since the potentials of the node 24 and the node 26 are the same as the bit line potential (hereinafter V _BH ) at the time of reading the memory cell OFF, as described above, the column lines GL ₂₁ and GL.
The potentials on ₂₃ and bit line BL ₂₂ are pulled up to V _BH .

Next, when the Y ₃ signal becomes the GND level and the Y ₂ signal becomes the V _CC level and the read operation of the memory cell MC ₄ is started, the nMOS transistor Q _G8 is ON and the nMOS transistor Q is turned on in the selected column line GL _{23. 10} changes to the GND potential because the gate input signal bar Y ₂ is turned off by the GND.

In the non-selected column line GL _21, the nMOS transistor Q ₉ is ON and the nMOS transistor Q _G5 is OFF.
_Therefore , the potential V _BH at the time of non-selection is maintained. R
_{Since 2} is very larger than the ON resistance of the memory cell MC _4, the bit lines BL ₂₂ potential at which the current of the current and the memory cell MC ₄ for pouring a current sense circuit 36 flow was equilibrated (hereinafter V _BL ). As a result, the output 29 of the current sense circuit 36 outputs V _SL .

Next, when the X ₀ signal and the Y ₁ signal are at the V _CC level and the other input signals are at the GND level, the column line GL ₂₁ selected at the time of reading the memory cell MC ₁ is nMOS.
Since the transistor Q _G5 is turned on and the nMOS transistor Q ₉ is turned off, the potential shifts to the GND potential. In the non-selected GL _23, the nMOS transistor Q ₁₀ turns on and the nMOS transistor Q _G8 turns off.
3 is electrically connected to the output node 24, and transitions to the potential V _{BH of the} node 24. The bit line BL ₂₂ transitions to the potential of V _BH because the memory cell MC ₁ is not turned on.
As a result, the output 29 of the current sense circuit 36 outputs V _CC .

[0021]

However, in the circuit having the above-mentioned structure, in order to realize high-speed reading in the X cell, several P are required.
A column line extending to F is pulled up to V _BH potential at high speed or G
In order to discharge ND, it is necessary to arrange two nMOS transistors having a large gm for each column line. Therefore, there is a problem that the pattern around the memory cell becomes large and the chip size becomes large.

The present invention eliminates the problem of increasing the chip size due to the nMOS transistors arranged at both ends of each column line in the prior art, and reads the ROM having a small chip size without impairing the high speed reading. The purpose is to provide a circuit.

[0023]

In order to solve the above problems, the present invention provides a memory matrix having an X cell structure, a first selecting means for selecting a row of the matrix, a column line and the column line. A read circuit having a second selection unit that selects an adjacent bit line includes an inverter circuit that outputs a reverse phase of the column decode signal output from the second selection unit, and at least one internally generated constant voltage source. The internally generated low voltage source supplies a predetermined potential to the inverter, and the output of the inverter is directly output to the column line.

[0024]

According to the present invention, in a ROM having an X-cell memory matrix structure, a column line is formed by an inverter which outputs a bit line potential (V _BH ) at the time of non-selection and at the time of reading and outputs a GND level at the time of selection. To drive.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, embodiments of the readout circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a read circuit of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals, and the duplicated description will be omitted here.

That is, in this embodiment, the circuit configuration of the memory matrix 37 surrounded by the alternate long and short dash line is the same as the conventional one shown in FIG. In addition, the current sense circuit 36
-1 and 36-2, row decoder 34, column decoder 3
5. The internally generated constant voltage sources 33-1 and 33-2 are also made of the same constituent elements as in the conventional example.

Inverters 40-1 to 40-2 respectively decode column address decode signals Y ₁ , Y ₂ or Y ₃ . ． ． It is an inverter that outputs a signal YA _A1 , _YA2 or _YA3 having the opposite phase. These inverters 4
0 is formed by a pMOS transistor Q ₃₈ and an nMOS transistor Q _39, and the source of the pMOS transistor Q ₃₈ is connected to the output node 24 of the internally generated power supply 33.

As a result, when the input signal Y _n is L, pM
When the OS transistor Q ₃₈ is turned on and the nMOS transistor Q ₃₉ is turned off, V _BH is output. When the input is H, the pMOS transistor Q ₃₈ turns off and nMO
GND is output when the S transistor Q ₃₉ is turned on.

In this embodiment, the column line GL of the memory matrix 37 is directly connected to the output of the inverter 40. Therefore, in the conventional circuit, the internally generated constant power source 3
3 and column lines, and nMOS transistors Q ₉ , Q ₁₀ , Q ₁₁ arranged between the column lines and GND, and nMOS transistors Q _G5 , Q _G8 . ． ． Is unnecessary.

[0031] Next will be described the operation of the present embodiment, for simplicity of description, the data written state of the memory cells MC ₁ to MC ₄ also selects the same city memory cell MC at the time of operation described in the prior art Do in exactly the same order. Further, it is assumed that the bit line potential when the V _{t of} the memory cell is higher than V _CC is the same V _BH as in the conventional example. Further, it is assumed that the bit line potential when V _{t of the} memory cell MC is lower than V _CC is the same V _BL as in the conventional example.

Here, it is assumed that the signals X ₁ and Y ₃ are at V _CC level and the other input signals are at GND level. At this time, the bars Y _A1 and Y _A2 are at V _BH level, and the bar Y _A3 is GND.
It is a level.

The output signals bar Y _A1 , bar Y _A2 , and bar Y _A3 of the inverters 40-1 to 40-3 are column lines G, respectively.
It is directly connected to L _{21 to} GL ₂₃ . Therefore, the non-selected column line GL and the bit line BL are connected to the node 24 of the internally generated constant voltage source 33-1 and the internally generated constant voltage source 33-2.
Of the node 26.

Since the potentials of the node 24 and the node 26 are the same as the bit line potential when V _{T of the} memory cell MC selected as described above is higher than V _CC , the column line G
The potentials of L and the bit line BL are pulled up to V _BH .

Next, the Y ₃ signal is at the GND level and the Y ₂ signal is at the V level.
_{When the} level becomes _CC and the reading of MC ₄ is started, the selected column line GL ₂₃ changes to the GND potential because the output bar Y _A2 of the inverter 40-2 of Y ₂ input becomes GND.
The non-selected column line GL ₂₁ is connected to the Y ₁ input inverter 40.
Since the output bar Y _{A1 of} -1 does not change, the column line potential V _BH at the time of non-selection is maintained. The selected bit line BL ₂₂ performs the same operation as the conventional circuit, and transits to V _BL . As a result, the output 29 of the current sense circuit 36-1 outputs V _SL .

Next, when the X ₀ signal and the Y ₁ signal are at the V _CC level and the other input signals are at the GND level, and when the operation for reading MC ₁ is started, the selected column line GL ₂₁ is connected to the Y ₁ input inverter 40-. The transition to the GND potential is caused by 1. GL ₂₃ became unselected, and the output of the inverter 40-2 Y ₂ input transitions to V _BH, at the same time a transition from GND to V _BH level. The selected bit line BL ₂₂ is a memory cell MC _1
Does not _{turn on} , the state transits to V _BH level. This causes output node 29 of current sense circuit 36 to transition to V _CC .

FIG. 3 is a waveform diagram of the read operation of FIGS. 1 and 2. As is apparent from FIG. 3, the nMOS transistors arranged at both ends of each column line GL are unnecessary without impairing high-speed reading.

[0038]

As described above in detail, according to the present invention, it is possible to prevent the high-speed reading of data in the X-cell memory array configuration of the prior art from being prevented, and the transistors in the periphery of the memory array per column line, It becomes possible to remove two transistors, which enables high-speed reading and
It can be expected to reduce the chip size.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a read circuit according to the present invention,

FIG. 2 is a circuit diagram of a conventional read circuit,

FIG. 3 is a comparative example of operation waveforms in FIGS. 1 and 3.

[Explanation of symbols]

 33-1, 33-2 internally generated constant voltage source 34 row decoder 35 column decoder 36-1, 36-2 current sense circuit 37 memory matrix 40-1 to 40-3 inverter

Claims (1)

[Claims] 1. A read comprising a memory matrix of X-cell structure, a first selecting means for selecting a row of the matrix, and a second selecting means for selecting a column line and a bit line adjacent to the column line. The circuit further includes an inverter circuit that outputs a reverse phase of the column decode signal output from the second selection unit, and at least one internally generated constant voltage source, and the internally generated low voltage source is predetermined in the inverter. The read circuit is characterized in that the output of the inverter is directly output to the column line while the potential of is supplied.