JPH0581893A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power consumption by making flow no current for detecting a redundant address required at the time of testing, though a redundant address signal is inputted at the time of using it normally regardless of finding the address signal of a block made block redundancy by testing in a semiconductor memory constituted so that plural address are made redundancy as a block, and the address of the block redundancy is detected in an external circuit. CONSTITUTION:An nM0S 29 is connected between the drain of the nM0S 27 required for detecting the raw address of the block made block redundancy and the emitter of an npn transistor 9 to be a constant current source, and the nM0S 29 is turned on at the time of testing and turned off at the time of using it normally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs redundancy with a plurality of addresses as blocks (hereinafter, such a redundancy method is referred to as block redundancy), and an address of a block that has been block redundant is detected by an external circuit. The present invention relates to a semiconductor memory device configured to be able to perform.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device of this type,
There has been proposed one whose main part is shown in FIG.

[0003] In the figure, 1 _0, 1 _n, respectively, from the outside,
These are row address signal input terminals to which row address signals A ₀ and A _{n of} so-called ECL (emitter coupled logic) level are input.

Here, the ECL level means, for example, that the power supply voltage Vcc on the H level side is 0 [V] = GND level,
In a circuit in which the power supply voltage V _EE on the L level side is -5.2 [V], for example, the threshold voltage is -1.3.
[V], H level of -0.9 [V] or higher, -1.7
It is a level where the level below [V] is the L level.

Also, row address signal input terminals 1 ₀ , 1 _n
Of, in particular, a row address signal input terminal 1 _0, in the row address, row address signal input terminals to the row address signal bits included row address signal necessary for selecting the block blocked redundancy is input Is.

On the other hand, the row address signal input terminal 1 _n is a row address to which a row address signal of a bit which does not include a row address signal necessary for selecting a block redundant block is input. Address signal input terminal.

Further, 2 ₀ and 2 _n are connected to the row address signal A through the row address signal input terminals 2 ₀ and 2 _n , respectively.
It is an ECL buffer to which ₀ and A _n are input. Where E
The CL buffers 2 ₀ and 2 _n have the same configuration.

Particularly, in the ECL buffer 2 ₀ , 3 is an npn transistor for inputting the row address signal A ₀ , 4 and 5 are npn transistors forming a differential pair transistor, and 6 is a reference voltage to which the reference voltage Vref is input. It is an input terminal.

Further, 7 is an output npn transistor for outputting a positive phase signal, 8 is an output npn transistor for outputting a negative phase signal, 9 to 12 are npn transistors forming a constant current source, 13 Is a bias voltage input terminal to which the bias voltage VA is input, and 14 to 19 are resistors.

Also, 20 ₀ and 20 _n are respectively ECL
The ECL level outputs from the buffers 2 ₀ and 2 _n are set to TTL.
(Transistor transistor logic) level, that is, a level conversion circuit that sets the H level to 0 [V] and the L level to -5 [V].

Reference numeral 21 is a row address decoder, and 22 _{0 to} 22 _m transfer a signal obtained by decoding a row address signal of a bit which does not include a row address signal necessary for selecting a block redundant block. Is a signal line for.

Further, 23 ₀ to 23 _k are signal lines for transferring a signal obtained by decoding a row address signal of a bit including a row address signal necessary for selecting a block redundant block, and particularly 23 _k Is a signal line for transferring a signal for selecting a block having a block redundancy.

The signal line 23 _k is at H level when a row address signal other than the redundant row address signal is input, and at L level when the redundant row address signal is input.

Further, 24 is a memory cell array section in which a plurality of memory cells selected by a row address and a column address are arranged, and 25 is a memory cell array section 2
Sense amplifier that amplifies the data read from 4
6 is an output terminal.

Further, 27 is an nMOS, 28 is an inverter, and a signal line 23 for transferring a signal for selecting a block redundant block of the row address decoder 21.
_k is connected to the gate of the nMOS 27 via the inverter 28. Therefore, the nMOS 27 is turned on when the redundant row address is input, and is turned off otherwise.

In such a conventional semiconductor memory device,
When a row address signal other than the redundant row address signal is input, the signal line 23 _k that transfers the signal for selecting the block redundant block maintains the H level, so that the nMOS 27 is turned off and the address signal is input. input current I _{iN 0} is inputted through the terminal 1 _0, it will be determined by the current I ₁ flowing through the resistor 14.

On the other hand, when the redundant row address signal is input, the signal line 23 _k for transferring the signal for selecting the block redundant block becomes L level and the nMOS 27 is turned on. , Input current I _IN0
Is determined by the combined current I ₁ + I ₂ of the current I ₁ flowing through the resistor 14 and the current I ₂ flowing through the nMOS 27.

[0018] Thus, during the test, by detecting the current change in the external circuit via the row address signal input terminal 1 _0, a row address signal that is used to perform the block redundancy, i.e., blocked redundant The row address of the existing block can be known.

[0019]

However, in such a conventional semiconductor memory device, even when it is normally used, when the redundant address signal is input, the resistance 14
In addition to the current I ₁ flowing in the nMOS 27, the current I ₂ also flows in the nMOS 27, and the power consumption increases accordingly. Such a problem similarly exists when the column address side is made redundant.

In view of such a point, the present invention makes it possible to know the address signal of the block in which the block has been made redundant by the test, but in the normal use, even if the redundant address signal is input, the test is performed. An object of the present invention is to provide a semiconductor memory device in which a current for detecting a redundant address, which is sometimes required, does not flow and power consumption can be reduced.

[0021]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention is a semiconductor memory device in which a plurality of addresses selected by a predetermined partial bit of an address signal composed of a plurality of bits are used as a block for redundancy. The first switch means is turned on when an address signal is input and is turned off when an address signal other than the redundant address signal is input, and is turned on during a test and turned off during a normal use. A current path formed of a series circuit with the second switch means is directly or indirectly connected to a part or all of the address signal input terminal to which the address signal of the predetermined partial bit is input. Is.

[0022]

In the present invention, when an address signal other than the redundant address signal is input during the test, the second switch means is turned on, but the first switch means is turned off. Also, no current flows in the current path formed by the second switch means.

On the other hand, when the redundant address is input, the first and second switch means are turned on, so that no current flows in the current path formed by these first and second switch means. Flowing.

Therefore, by detecting this change in current, it is possible to know the address signal used for performing the block redundancy, that is, the row address of the block having the block redundancy.

In addition, during normal use, the second switch means is turned off. Therefore, regardless of whether or not the redundant address signal has been input, the current path formed by the first and second switch means has no current. Does not flow.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. In this embodiment, nM is provided between the drain of the nMOS 27 and the emitter of the npn transistor 9.
The OS 29 is provided, the drain thereof is connected to the emitter of the npn transistor 9, and the source thereof is the nMOS 27.
Connected to the source.

In addition to the ECL buffer 2 _n , the address signal input terminal 1 _n to which a row address signal of a bit that does not include a row address signal necessary for selecting a block-redundant block is input is a TTL buffer. Thirty
The negative phase output terminal 31 of the TTL buffer 30 is connected to the gate of the nMOS 29.

Here, the TTL buffer 30 has a threshold voltage of -2.5 [V], for example, and -2.0.
[V] or higher is determined as H level, and −3.0 [V] or lower is determined as L level.

Therefore, when the ECL level address signal A _n is input, this signal is determined to be the H level regardless of the H level and the L level of the ECL level, and the negative phase output terminal of the TTL buffer 30. 31 for L
The level is output and the nMOS 29 is turned off.

Further, it is −3.0 [V] or less, for example, −5.
When 2 [V] is input, this voltage is determined to be L level, H level is output to the negative phase output terminal 31 of the TTL buffer 30, and the nMOS 29 is turned on.

In this embodiment, for example, the power supply voltage of the ECL circuit, -5.2 [V], is applied to the address signal input terminal 1 _n during the test. As a result, the output of the negative phase output terminal 31 of the TTL buffer 30 is set to the H level, and the nMOS 29 is turned on.

The row address signal bits included row address signal necessary for selecting the block redundancy blocks are input to the address signal input terminal 1 ₀ ... in this state.

When a row address signal other than the row address signal necessary for selecting a block-redundant block is input here, a signal for selecting a block-redundant block in the row address decoder 24. Since the signal line 23 _k for transmitting the signal maintains the H level,
OS27 is turned off, the input current I _{IN 0} inputted through the address signal input terminal 1 _0, will be determined by the current I ₁ flowing through the resistor 14.

On the other hand, when the row address signal necessary for selecting the block-redundant block is input, the signal line 23 _k for transferring the signal for selecting the block-redundant block is L Level, nMO
Since S27 is turned on, the input current I _IN0 is
The current I ₁ flowing through the 4, will be determined by the resultant current I ₁ + I ₂ and the current I ₂ flowing through the NMOS 27.

[0036] Therefore, by detecting the current change in the external circuit via the row address signal input terminal 1 _0, which by that address signal is used to perform the conventional semiconductor memory device as well as block redundancy, i.e., It is possible to know the row address of a block which is block redundant.

Further, in normal use, the row address signal input terminals 1 _n, ECL level of the row address signal A _n
However, since the row address signal A _n is determined to be the H level regardless of the H level and the L level at the ECL level, the TTL buffer 30 outputs to the negative phase output terminal 31 of the TTL buffer 30. The L level is output and the nMOS 29 is turned off.

Therefore, the row address signal necessary for selecting the block-redundant block is input, the signal line 23 _k for transferring the signal for selecting the block-redundant block becomes L level, and the nMOS 27 is turned on. Even in the case of the above, no current flows in the current path including the nMOS 27.

As described above, according to the present embodiment, the row address of the block-redundant block can be known by the test, but in the normal use,
Even if the redundant address signal is input, the nMOS 27
Since it is possible to prevent current from flowing in the current path including, it is possible to reduce power consumption.

In the above embodiment, the case where the row address side is made redundant has been described, but the present invention is
It can be naturally applied to the case where the column address side is made redundant.

[0041]

According to the present invention, although the address signal of the block having the block redundancy can be known by the test, even if the redundant address signal is input in the normal use, the address signal of the block is not used in the test. It is possible to prevent the required current for redundant address detection from flowing and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of an example of a conventional semiconductor memory device.

[Explanation of symbols]

1 ₀ , 1 _n row address signal input terminal 2 ₀ , 2 _n ECL buffer

Claims (1)

[Claims] 1. A semiconductor memory device for performing redundancy with a plurality of addresses selected by a predetermined partial bit of an address signal composed of a plurality of bits as a block, which is turned on when a redundant address signal is input. , A series circuit of first switch means that is turned off when an address signal other than the redundant address signal is input, and second switch means that is turned on during a test and turned off during normal use A semiconductor memory device, wherein a current path is directly or indirectly connected to a part or all of an address signal input terminal to which the address signal of the predetermined partial bit is input.