JP3288760B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for use in a NAND type read-only memory (ROM).

[0002]

Conventionally, the NOR type ROM, provided with a dummy bit line and the dummy cell in the cell array, a method of canceling from occurring shaking is used to supply potential V _cc and V _ss ground potential the bit lines by the noise Had been. FIG. 3 is a schematic configuration diagram of a conventional semiconductor memory device in which such a noise measure is taken. As shown in FIG. 3, the gates of the memory cells C1 to C3 are connected to the word lines WL1 to WL.
L3, and the drain for reading is connected to the bit line BL. And the bit line BL is
It is connected to the bit line bias circuit BB through the column selectors CS1 and CS2. On the other hand, the word lines WL1 to WL3 are also connected to gates of dummy cells DC1 to DC3 arranged symmetrically with the memory cells C1 to Cn. The drains of the dummy cells DC1 to DC3 are connected to the dummy bit line DBL. Dummy bit lines DBL are connected to transfer gates DS1, DS2.
Is connected to a dummy bit line bias circuit DBB. The bit line bias circuit BB generates an input voltage V _SA and inputs it to the differential amplifier SA. On the other hand, the dummy bit line bias circuit DBB
Generates a reference voltage V _REF and inputs it to a differential amplifier SA. The differential amplifier SA compares and senses the reference voltage V _REF and the input voltage V _SA and outputs an output D _out .

The bit line bias circuit BB is
It is connected to the bit line BL through the column selectors CS1 to CSn. The dummy bit line bias circuit DBB is connected to the dummy bit line DBL through transfer gates DS1 and DS2. Each of the bias circuits BB and DBB has a configuration illustrated in the circuit configuration diagram of FIG.
An input voltage V _SA and a reference voltage V _REF are supplied. On the other hand, the differential amplifier SA has a configuration illustrated in FIG. 7, performs a sensing operation on the input voltage V _SA and the reference voltage V _REF , and outputs an output D _out .

In the above configuration, for example, it is assumed that the memory cell C1 is selected by the word line WL1. The state of the memory cell C1 is output to the bit line BL. At the same time, the dummy cell DC1 connected to the word line WL1 is also selected, and the reference level appears on the dummy bit line DBL. The bit line BL is connected to a bit line bias circuit BB through column selectors CS1 to CSn. Similarly, the dummy bit line DB
L passes through transfer gates DS1 and DS2,
It is connected to a dummy bit line bias circuit DBB.
The size of each of the load transistors of the bit line bias circuit BB and the dummy bit line bias circuit DBB is substantially intermediate between when the reference voltage V _REF is high and when the differential amplifier SA input V _SA is high L and low. Level is set. And
Whether the threshold value of the transistor of the memory cell C1 is the normal level (= 1 V) or high (= 7 V) is amplified by the differential amplifier SA, and whether the storage data of the cell C1 is "1" or "0" is sensed. I have. Generally, the dummy cell DC
The threshold of one transistor is in the normal level range. However, by V _cc and V _ss of the noise, the bit line BL
Suppose the potential fluctuates. In this case, the dummy bit line D
The potential of BL fluctuates similarly. Therefore, two inputs to the differential amplifier SA, that is, the input voltage V _SA and the reference voltage V _REF also fluctuate. As a result, the noises cancel each other _out, and the effect of the noise does not appear on the output Dout.

[0005] On the other hand, the configuration of the dummy cells of the NAND type ROM is different from that of the NOR type ROM. That is, in the NAND type ROM, the memory cell is configured by connecting an enhancement type transistor and a depletion type transistor in series. For this reason, when the memory cell (transistor) is on, especially when the selected transistor is a depletion transistor, the cell potential varies depending on the number of depletion transistors connected in series. In the method using the differential amplifier SA, it is necessary to be able to sense even when the cell current is minimized. Similarly, the dummy cell must have the minimum cell current.

FIG. 4 is a schematic configuration diagram showing another example of such a conventional semiconductor memory device. Dummy cells DC1 to DCn provided in relation to memory cells C1 to Cn include a depletion type transistor having a gate threshold value of 0 V,
It is configured in series with a transistor having a gate threshold value of _Vcc . The memory cells C1 to Cn are connected in series to a NAND select gate NC whose gate is connected to a NAND select line NSL, and are connected to the bit line BL via the NAND select gate NC.

In such a configuration, the word line WL
The states of the memory cells C1 to Cn selected by 1 to WLn are stored in the bit line B through the NAND select gate NC selected by the NAND select line NSL.
L, and further input to the bit line bias circuit BB via the column selectors CS1 to CSn. On the other hand, the dummy bit lines DBL connected to the dummy cells DC1 to DCn are connected to the transfer gates DS1, DS1.
2 is connected to a dummy bit line bias circuit DBB. And a bit line bias circuit B
The input voltage V _SA from B and the reference voltage V _REF from the dummy bit line bias circuit DBB are sensed by the differential amplifier SA and output as an output D _out .

[0008]

Even in the above configuration, a combination that minimizes the cell current is required. This is the case where there is one depletion type transistor and its gate potential is still 0V.

Now, suppose that dummy cells DC1 to DCn are configured in a cell array. For example, the memory cell C
2 and the memory cells C3 and C4 are selected, the corresponding dummy cells DC1 to D4 are selected.
Cn must always be a series connection of one depletion-type transistor having a gate of 0 V and an enhancement-type transistor having a gate of _Vcc . However, this is not possible as a practical matter.

Therefore, the NAND type ROM cannot have a configuration in which dummy cells are provided in a cell array as shown in FIG. For this reason, it is not possible to cancel a sufficient effect of shaking of V _cc and V _ss of noise due to the bit line BL. Then, as shown in the output waveform diagram of FIG.
Exits the influence of fluctuation of the bit line BL according to V _cc and V _ss of the noise to the differential amplifier SA input, the influence is little on the reference voltage V _REF. Therefore, in the worst case, the state of the output D _out is inverted.

[0011] The present invention has been made in view of the above,
Its purpose is, V _cc and V _ss level is varied based on the noise in the NAND ROM, even if occurring shaking to the potential of the bit line, enabling stable reading of the memory to cancel this effectively Is to do.

An apparatus according to the present invention comprises a NAND type memory cell group in which the gate of each memory cell is connected to each select line;
Configured and arranged in the same array as the memory cell group,
A gate of each of the select lines has a first dummy cell group of a NAND type having a plurality of enhancement-type transistors connected in common with a gate of each of the memory cells, and an array of each of the memory cell groups in a separate place. A second dummy cell group having a plurality of transistors, each having a fixed gate potential, and a bit line bias circuit connected to a bit line of the memory cell group;
A dummy bit line bias circuit connected to a dummy bit line connected to the first dummy cell group and the second dummy cell group; an output of the bit line bias circuit and a reference voltage from the dummy bit line bias circuit stage; And an arithmetic circuit for comparing and outputting a comparison result.

[0013]

The data from the NAND type memory cell group is applied to the bit line bias circuit. The bias circuit applies a signal corresponding to input data to one input terminal of the arithmetic circuit. A signal from the NAND type first dummy cell group and a signal from the second dummy cell group are both input to the dummy bit line bias circuit. The dummy bit line bias circuit supplies a reference voltage corresponding to two input signals,
It is applied to the other input terminal of the arithmetic circuit. The arithmetic circuit is 2
Output an output based on one input.

Thus, the gate of each memory cell of the NAND type memory cell group and the gate of each dummy cell of the NAND type first dummy cell group are commonly connected to each select line, and the memory cell group and the dummy memory cell group Are arranged in the same array and a second dummy cell group for setting a DC reference potential is provided, so that fluctuations in the power supply potential and the ground potential due to noise are common to the two cell groups. Appears and is eventually offset.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to one embodiment of the present invention. As shown in FIG. 1, a series circuit of dummy cells DC1 to DCn is connected to a dummy bit line bias circuit DBB via transfer gates DS1 and DS2. Further, a NAND array comprising enhancement type transistors is provided in the cell array.
Dummy cells DC1a to DCna each composed of a mold cell are provided. These cells DC1a to DCna are connected to a dummy bit line DB via a NAND select gate DNC connected to a NAND select line NSL.
L. The dummy bit line DBL is connected to a dummy bit line bias circuit DBB through transfer gates DS1a and DS2a.
The dummy cells DC1a to DCna are the memory cells C
1 to Cn and common word lines WL1 to WL
Ln.

In the configuration described above, the memory cells C1 to C1 selected by the word lines WL1 to WLn are used.
The state of Cn is transmitted to the bit line BL through the NAND select gate NC. Furthermore, the state of the cell is
The signal is applied to the bit line bias circuit BB through the column selectors CS1 to CSn. On the other hand, the dummy cell DC1
To DCn are connected to the dummy bit line bias circuit DBB through the dummy cells DC1 to DCn.
At the same time, the state of the dummy bit line DBL is also supplied to the dummy bit line bias circuit DBB through the dummy cells DC1a to DCna. Dummy cells DC1a-D
Cna is connected to the common word lines WL1 to WLn with the memory cells C1 to Cn. Therefore, the dummy cells DC1a to DC1a selected by the word lines WL1 to WLn are
The state of DCna is given to the dummy bit line DBL through the NAND select gate DNC.

[0018] Now, the noise shook the bit line BL occurred in the V _cc and V _ss. Selected dummy cell DC
1a to DCna are provided in the cell array. Therefore, so that sway in accordance with the swinging state even of V _cc and V _ss of those cells. The fluctuation of the state of the dummy cells DC1 to DCn is transmitted through the NAND select gate DNC.
The signal is transmitted to the dummy bit line DBL. This allows
The dummy bit line DBL swings similarly. As a result, the reference voltage V _REF supplied from the dummy bit line bias circuit DBB to the differential amplifier SA also fluctuates. Therefore, as shown in the waveform diagram of FIG.
Even V _cc or even swing the input voltage V _SA obtained through a bit line bias circuit BB from the bit line BL for shaking the V _ss, the dummy bit line bias circuit D
The reference voltage V _REF output from BB fluctuates similarly. For this reason, noise is canceled from the output D _out from the differential amplifier SA.

As described above, even in a case where a dummy cell cannot be provided in a memory cell array as in a NAND ROM, a dummy cell connected to a NAND cell composed of an enhancement transistor is provided in the cell array. by providing, since so as to transmit the variations in V _cc and V _ss to the dummy bit line bias circuit DBB, it is possible to configure the noise resistance of the excellent ROM.

In the above embodiment, the dummy cells DC1 to DCn are provided separately from the dummy bit line DBL. However, the dummy cells DC1 to DCn are connected to the reference voltage V
Since only the DC level of _REF is set, the dummy cells DC1 to DCn may be directly connected to the dummy bit line DBL.

Further, in the above embodiment, the NAND type RO
Circuits applicable to M in general have been illustrated. However, according to the present invention, if the memory cell is a NAND type, the mask RO
The present invention is applicable to any of M, EPROM, and EEPROM.

[0022]

As described above, according to the present invention, even when the potential of the read bit line from the memory cell fluctuates due to the noise of Vcc or Vss, the same fluctuation occurs in the potential of the dummy bit line. As a result, the input of the differential amplifier and the reference voltage for sensing the same have the same fluctuation, so that noise is canceled and a signal free from noise is obtained at the output.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is an output waveform diagram in FIG.

FIG. 3 is a schematic configuration diagram illustrating an example of a conventional semiconductor memory device.

FIG. 4 is a schematic configuration diagram showing another example of a conventional semiconductor memory device.

5 is an output waveform diagram in the configuration of FIG.

FIG. 6 is a circuit configuration diagram showing an example of a configuration of a bit line bias circuit and a dummy bit line bias circuit.

FIG. 7 is a circuit configuration diagram showing an example of the configuration of a differential amplifier.

[Explanation of symbols]

 BB Bit line bias circuit SA Differential amplifier DBB Dummy bit line bias circuit BL Bit line DBL Dummy bit line C1 to Cn Memory cell DC1 to DCn Dummy cell DC1a to DCna Dummy cell WL1 to WLn Word line NSL Nand select line NC Nand select gate DNC NAND select gate CS1 to CSn column selector DS1 transfer gate DS2 transfer gate DS1a transfer gate DS2a transfer gate

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Takizawa 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Microelectronics In-house (72) Inventor Shigefumi Ishiguro 25, Ekimae-Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Address 1 In-house Toshiba Microelectronics Corporation (56) References JP-A-63-225998 (JP, A) JP-A-3-263693 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) G11C 16/06

Claims (2)

(57) [Claims] A NAND type memory cell group in which a gate of each memory cell is connected to each select line; and a NAND type memory cell group configured and arranged in the same array as the memory cell group.
A gate of each of the select lines has a first dummy cell group of a NAND type having a plurality of enhancement-type transistors connected in common with a gate of each of the memory cells, and an array of each of the memory cell groups in a separate place. Arranged
Multiple transistors with fixed gate potentials
A dummy cell connected to a dummy bit line connected to the first dummy cell group and the second dummy cell group; a bit line bias circuit connected to a bit line of the memory cell group; A line bias circuit, comparing the output of the bit line bias circuit with a reference voltage from the dummy bit line bias circuit stage,
A semiconductor memory device, comprising: an arithmetic circuit that outputs a comparison result. 2. The second dummy cell group according to claim 1, wherein a gate of the second dummy cell group is grounded.
Depletion type transistor
Is fixed to the selection potential of the selection line.
And a transistor of the same type.
Item 2. The semiconductor memory device according to item 1.