JPH06150681A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To lower a power source voltage by starting a H or L level by connecting sources to low or high power source potentials and connecting drains to either an inversion or non-inversion bit lines in the case when the memory cores of a ROM are N or P MOS transisters. CONSTITUTION:When a word line 122 or 123 goes to a H level to be selected, N MOS transisters (Tr) 110 or 111 goes to ON and the power source potential VSS of a source is transmitted to the non-inversion or inversion bit line 130 or 131. Furthere, when a word line 120 or 121 goes to a L level and is selected, P MOS Tr 112 or 113 goes to ON, high power source potential VVDD of a source is also transmitted to the inversion or non-inversion bit line 133 or 132. The potential of the conversion bit line 130 is outputted by inverters 160 to 162, the potential of the non-inversion bit line 132 is outputted by inverters 163, 164, 166. In such a manner, the power source voltage is lowered to the higher threshold value among P and N MOS Tr s.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory circuit (hereinafter referred to as "ROM") formed on a basic cell column of a CMOS master slice type semiconductor integrated circuit device (hereinafter referred to as "gate array"). Is.

[0002]

2. Description of the Related Art In a gate array, basic constituent cells (hereinafter, referred to as "basic cells") each having an NMOS transistor and a PMOS transistor are arranged, and a logic circuit is formed by connecting these cells in a step after a wiring step. Constitute. Even when a ROM is formed by using a plurality of basic cells, each transistor is connected in the steps after the wiring step.

As shown in FIG. 2, the ROM is roughly divided into an address decoder 1, a memory core 2, a sense amplifier 3 and an output buffer 4.

FIG. 3 shows an example of a conventional circuit.

Transistor 10 constituting the memory core,
..., 13 (10, 11: NMOS transistor, 12,
13: PMOS transistor) is a transistor of a basic cell, the source of each is a high power supply potential (hereinafter,
Data is stored by connecting to “VDD” or “H level”) or a low power supply potential (hereinafter referred to as “VSS” or “L level”). The gates of the memory core transistors 10, ..., 13 are word lines 20, respectively.
, 26, and the respective drains thereof are connected to the bit lines 30, 31. Since there are two types of memory core transistors, NMOS and PMOS, the word line and bit line are provided with two types, one for NMOS and one for PMOS.

Now, suppose that an address decoder is used for NMO.
It is assumed that the S word line 22 is selected. In order to bring the memory core transistor 10 connected to this word line into a conductive state, the potential of the word line 22 is set to the H level. As a result, a potential difference is generated between the gate and the source of the transistor 10, the transistor 10 becomes conductive, and VSS connected to the source is transmitted to the bit line 30. The potential of the bit line 30 is buffered by the inverters 60 and 61, and the L level is output. In addition, 40 is a pull-up control PMOS transistor, 42
Is a pull-up resistor. Similarly, the PMOS word lines 20 and 21 are selected when they become L level, and PM
The OS transistors 12 and 13 are turned on, and the source potential of each is transmitted to the bit line 31. The potential of the bit line 31 is buffered by the inverters 62 and 63,
Is output. Reference numeral 41 is a pull-down control NMOS transistor, and 43 is a pull-down resistor.

[0007]

However, when VDD is connected to the source like the NMOS memory core transistor 11 in FIG. 3, even if the word line 23 is selected and becomes H level, the gate / source is There is no potential difference between them. The transistor 11 becomes conductive due to the potential difference between the gate and the drain, and transmits the source potential to the bit line. However, when the potential of the bit line 30 rises and the potential difference with the gate becomes smaller than the threshold voltage of the transistor 11,
The transistor 11 is cut off and becomes non-conductive. That is, the potential of the bit line 30 does not rise any more. The potential of the bit line 30 at this time is: potential of the bit line 30 = high power supply potential−threshold voltage of the transistor 11. When this potential is received by the CMOS inverter 60 assuming that the potential is sufficiently higher than the threshold voltage of the NMOS transistor, the transistor 50 becomes conductive. But,
There is a potential difference corresponding to the threshold voltage of the transistor 11 between the gate and the source of the transistor 51. If this potential difference is higher than the threshold voltage of the transistor 51,
The transistor 51 also becomes conductive, and a through current flows through the inverter 60. To prevent this, the potential of the bit line 30 is raised to VDD by the pull-up circuit (pull-up control transistor 40, pull-up resistor 42). The pull-up circuit is an inverter 60
Bit line 3 conducts only when the output of
When 0 becomes L level, the output of the inverter 60 becomes H level and the pull-up circuit becomes non-conductive. However, when operating with the power supply voltage lowered, the previous H level of the bit line 30 approaches the threshold voltage of the transistor 50, the transistor 50 does not become completely conductive, and the output of the inverter 60 has an intermediate potential. Is output.
In this state, the transistor 40 of the pull-up circuit does not conduct, and a normal value is not output. The same result is obtained when the source of the PMOS transistor is connected to VSS, and it is difficult to operate at a low power supply voltage whose power supply voltage is equal to or less than the sum of the threshold voltage of the NMOS transistor and the threshold voltage of the PMOS transistor. .

[0008]

To solve the above problems, the bit line is always kept at a stable high power supply potential or low power supply potential. That is, when the memory core transistor is an NMOS, the source is set to a low power supply potential and the PM
In the case of OS, the source is connected to the high power supply potential. Then, two kinds of bit lines, a non-inverted bit line and an inverted bit line, are prepared, and by selecting which bit line the drain of the memory core transistor is connected to,
It is determined whether to store the L level or the H level. The two types of bit lines are connected to respective inverters, and the respective inverters drive the bit lines connected to their inputs. When the drain of the memory core transistor is connected to the non-inverted bit line, the source potential of that transistor is output, and when the drain of the memory core transistor is connected to the inverted bit line, the source potential of that transistor is output. Invert and output.

[0009]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a block diagram of an embodiment of the present invention.

Transistor 11 forming a memory core
Reference numerals 0 and 111 are NMOS transistors, each source is connected to the low power supply potential (VSS), and each gate is connected to each word line 122, 123. The drain of the transistor 110 is connected to the non-inverting bit line 130, and when the word line 122 becomes H level and is selected, the transistor 110 becomes conductive due to the potential difference between the gate and the source, and the low power supply potential is applied to the bit line. 1
Tell 30 On the other hand, the drain of the transistor 111 is connected to the inverted bit line 131 and the word line 123.
Becomes H level and is selected, the transistor 111
Becomes conductive due to the potential difference between the gate and source,
The low power supply potential is transmitted to the inverted bit line 131. The two kinds of bit lines 130 and 131 are respectively connected to the inverters 161 and 160 which function as sense amplifiers, and the outputs of the respective inverters mutually drive the bit lines connected to the input of the other inverter. ing. The inverter 162 is for output, is connected to the output of the inverter 161, and outputs the potential of the non-inverting bit line 130.

Next, the PMOS transistor portion will be described. A transistor 112 forming a memory core,
Reference numeral 113 is a P-channel MOS transistor, each source is connected to the high power supply potential (VDD), and the gate is connected to each word line 120, 121.
The drain of the transistor 112 is connected to the inversion bit line 133, and when the word line 120 becomes L level and is selected, the transistor 112 becomes conductive due to the potential difference between the gate and the source, and the high power supply potential is inverted. Reach line 133. On the other hand, the drain of the transistor 113 is connected to the non-inverted bit line 132, and when the word line 121 becomes L level and is selected, the transistor 113 becomes conductive due to the potential difference between the gate and the source, and the high power supply potential is applied. Transfer to non-inverted bit line 132.
The two types of bit lines 132 and 133 are connected to the inverters 164 and 163, respectively, which serve as sense amplifiers, and the outputs of the respective inverters mutually drive the bit lines connected to the input of the other inverter. ing. The inverter 166 is for the inverter output, is connected to the output of the inverter 164, and is connected to the non-inverted bit line 13
The potential of 2 is output.

The operation will be described below.

It is now assumed that the word line 122 is selected and becomes H level. Since the other word lines are in the non-selected state, the word line 123 is set to the L level and the word lines 120 and 121 connected to the PMOS transistors are set to the H level. The transistor 110 becomes conductive due to the potential difference between the gate and the source, and transmits the low power supply potential connected to the source to the non-inverting bit line 130. At this time, the non-inverting bit line 130 is driven to either the high power supply potential or the low power supply potential by the inverter 160, but even if it is driven to the high power supply potential, the non-inverting bit line 130 is driven by the transistor 110.
Inverter 160 so that the potential of
The drive capability on the high power supply potential side of the transistor is lower than that of the transistor 110. At this point, a through current temporarily flows, but when the L level is transmitted to the bit line 130, the inverted bit line 131 is driven to the H level by the inverter 161, and the inverter 160 outputs the L level. As a result, the path of the through current is cut off. Bit line 130 is L
The bit line 131 is fixed to the H level, and the inverter 162 outputs the L level.

Next, it is assumed that the word line 123 is selected and becomes H level. The transistor 111 becomes conductive due to the potential difference between the gate and the source, and transmits the low power supply potential connected to the source to the inversion bit line 131. The bit line 131 is also driven to either the high power supply potential or the low power supply potential by the inverter 161, but even if it is driven to the high power supply potential, the potential of the bit line 131 is set to the L level by the transistor 111. For this reason, the drive capability of the inverter 161 on the high power supply potential side is lower than that of the transistor 111. By the same operation as described above, the bit line 130 is set to the H level,
The bit line 131 is fixed to the L level, and the inverter 162
Will output an H level.

Next, it is assumed that the word line 120 is selected and becomes L level. The transistor 112 has a gate
Due to the potential difference between the sources, it becomes conductive, and the high power supply potential connected to the source is transmitted to the inversion bit line 133.
At this time, the inverted bit line 133 is driven to either the high power supply potential or the low power supply potential by the inverter 164, but even if it is driven to the low power supply potential, the inverted bit line 133 is driven by the transistor 112.
Inverter 164 so that the potential of
Of the low power supply potential side is lower than that of the transistor 112. By the same operation, the bit line 132 is set to L level, the bit line 133 is set to H level, and the inverter 166 outputs L level.

Finally, it is assumed that the word line 121 is selected and becomes L level. The transistor 113 has a gate
Due to the potential difference between the sources, it becomes conductive, and the high power supply potential connected to the source is transmitted to the non-inverting bit line 132. The bit line 132 is also driven to either the high power supply potential or the low power supply potential by the inverter 163, but even if it is driven to the low power supply potential, the potential of the bit line 132 is set to the H level by the transistor 113. For this reason, the drive capability of the inverter 163 on the low power supply potential side is lower than that of the transistor 113.
By the same operation, this time, the bit line 132 is set to the H level, the bit line 133 is set to the L level, and the inverter 1
66 outputs H level.

[0018]

As described in detail above, according to the present invention, there is always a predetermined potential difference between the gate and the source of the selected memory core transistor, and the bit line is sure to have a high power supply potential or a low potential. Power supply potential is transmitted. As a result, a PMOS transistor or an NM forming a sense amplifier (inverter) connected to each bit line.
A potential exceeding the threshold voltage is applied between the source and the gate of any one of the OS transistors, and each transistor is surely turned on. The amplitude of the bit line varies from a low power supply potential to a high power supply potential, and the amplitude potential difference may be higher than the threshold voltage of each of the PMOS transistor and the NMOS transistor. That is, it is possible to reduce the power supply voltage to the higher threshold voltage of either the PMOS transistor or the NMOS transistor.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a read-only memory.

FIG. 3 is a circuit configuration diagram showing a conventional configuration example.

[Explanation of symbols]

110,111 NMOS memory core transistor 112,113 PMOS memory core transistor 120,121 PMOS word line 122,123 NMOS word line 130,131 NMOS bit line 132,133 PMOS bit line 160,161,163,164 Sense Inverter for amplifier 162,166 Inverter

Claims (1)

[Claims] 1. In a read-only memory circuit formed on a basic cell column of a CMOS master slice type semiconductor integrated circuit device, an L level is used when a transistor forming a memory core is NMOS, and an H level is used when it is PMOS. A semiconductor integrated device characterized in that it is decided to store an H level or an L level by connecting to each source and connecting the drain side to either an inverting output bit line or a non-inverting output bit line. Circuit device.