JPH11260064A - Sense amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sense amplifier which requires a low power consumption and is capable of performing a readout operation at a high speed. SOLUTION: A sense amplifier 1 is composed of an isolation circuit 10, a current supply circuit 20, a sense circuit 30 and a latch circuit 40 which are configured by cross-coupling inputs and outputs of two CMOS inverters 31, 32. The sense amplifier 1 is isolated from a data line pair DL, *DL except when data is to be read out from a memory cell. At the time of the data readout from the memory cell, the sense amplifier 1 supplies current from its current supply circuit 20 to the sense circuit 30 so as to raise the sensing speed of the sense circuit 30, and latches the sensing result by the latch circuit 40 to be output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier used in a semiconductor memory such as an SRAM (static RAM), and more particularly to a differential sense amplifier suitable for speeding up data reading from a semiconductor memory cell. About.

[0002]

2. Description of the Related Art Conventionally, as a differential sense amplifier used in a semiconductor memory such as an SRAM, a current mirror type sense amplifier constituted by a MOSFET or the like is mainly used. Since the current mirror type sense amplifier consumes a large amount of direct current (DC) due to its characteristics, a latch type sense amplifier which consumes a small amount of DC current is often used as the differential type sense amplifier. ing.
As such a latch type sense amplifier, for example, a differential type sense amplifier disclosed in Japanese Patent Application Laid-Open No. 8-77780 is known. FIG. 5 shows a configuration of a differential (latch type) sense amplifier described in the publication.

In FIG. 5, a portion surrounded by a broken line constitutes a sense amplifier, and data read from a memory cell by the sense amplifier is performed as follows. At the time of reading, first, the bit line pair BL, * BL (* indicates logical inversion) is precharged to the power supply voltage VDD. Next, the word line to which the memory cell to be read is connected is selected. At this time, since all the Y-selects are still off, no DC current flows through the sense amplifier. At this time, the read data line pair RL, * RL
Are pulled down to the ground level by an n-channel MOS transistor (hereinafter referred to as an nMOS transistor) 56. When a certain potential difference occurs between the bit line pair BL and * BL, the switch nMOS transistor 57 of the sense amplifier is turned on and the pull-down nMOS transistor 56 is turned off. At this time, when only one Y select is turned on, one of the read data line pair RL and * RL becomes a logic high (H) level according to the potential difference between the bit line pair BL and * BL, and the read ends. When the sensing is completed, the current of the sense amplifier is automatically cut off due to the characteristics of the CMOS inverter 55.

[0004]

In the above-described conventional sense amplifier, the CMOS inverter 55 is used.
P-channel MOS transistor (hereinafter referred to as pM
The OS transistor 55a is connected to the memory cell via the pMOS transistor 54 constituting Y select. Therefore, the source of the logic H level voltage of the sense amplifier is only the memory cell. In addition, the logic H level voltage is lower than the power supply voltage VDD. For this reason, the reading speed of the sense amplifier is naturally limited, which is also a factor of prolonging the SRAM access time.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a sense amplifier which consumes less power and enables a higher-speed read operation. .

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a semiconductor memory device is provided between a pair of signal lines connected to a memory cell of a semiconductor memory. A gist of the present invention is to provide a sense amplifier for amplifying a potential difference and including a current supply unit for supplying a current to a sense unit during sensing.

According to a second aspect of the present invention, in the sense amplifier according to the first aspect, the sensing section amplifies signals on the same pair of signal lines based on a potential difference between the pair of signal lines. The gist is that the current supply means supplies a current to the sensing unit when the sensing unit starts sensing.

According to a third aspect of the present invention, in the sense amplifier according to the first or second aspect, each of the sense units includes a p-channel field-effect transistor and an n-channel field-effect transistor. A signal from the pair of signal lines is input to the source side of the field effect transistor, and its input and output are connected to a pair of inverters that are cross-coupled, and are connected between the pair of inverters and ground and turned on during sensing. n
A channel field-effect transistor, and a pair of pull-down n-channel field-effect transistors connected to each output terminal of the same pair of inverters and setting the potential of the output terminal to a predetermined level before starting sensing. The gist is that the supply means includes four p-channel field-effect transistors which are in front of the sensing unit and supply current to the pair of signal lines when the sensing unit starts sensing. .

According to a fourth aspect of the present invention, when the sense section is inactive, the sense section and the current supply means are separated from the memory cell. The gist of the present invention is to further include a separating unit and a latch circuit for latching an output of the sense unit when the sense unit is active.

According to a fifth aspect of the present invention, there is provided a sense amplifier provided between a pair of signal lines connected to a memory cell of a semiconductor memory and amplifying a potential difference between the signal lines, wherein each of the sense amplifiers includes a p-channel amplifier. A pair of CMOS inverters that input a signal from the pair of signal lines to a source side of a MOS transistor and that input and output are cross-coupled;
An n-channel MOS transistor connected between the pair of CMOS inverters and the ground and turned on at the time of sensing, and connected to each output terminal of the same pair of CMOS inverters to set the potential of the output terminal to a predetermined level before the start of sensing. A sense unit having a pair of pull-down nMOS transistors, and four p-channel MOS transistors, which are in front of the sense unit and supply current to the pair of signal lines when the sense unit starts sensing. A current supply unit having a transistor, a separation unit for separating the sense unit and the current supply unit from the memory cell when the sense unit is inactive, and an output of the sense unit when the sense unit is active. And a latch circuit for latching.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which a sense amplifier of the present invention is applied to a static RAM will be described below in detail with reference to FIGS.

FIG. 2 schematically shows a configuration of a portion related to reading data from a memory cell in a static RAM. In FIG. 2, memory cell MC
Are arranged in a matrix, and each of the memory cells MC is connected between a pair of bit lines BL and * BL (* indicates logical inversion) and is connected to one word line WL.
A precharge / equalize circuit PE1 for connecting the same bit line pair BL, * BL to the same potential when not sensing is connected between one ends of the bit line pair BL, * BL. On the other hand, the other end of the bit line pair BL, * BL is
As shown in FIG.
1 and QS2 are connected to a pair of data lines DL and * DL. This data line pair DL, * DL has a predetermined number,
For example, eight pairs of the bit lines BL and * BL are connected,
Similarly, between the pair of data lines DL and * DL, as in the case of the pair of bit lines BL and * BL, a precharge circuit for setting the same potential of the pair of data lines DL and * DL to the same potential during the non-sense period.
The equalizing circuit PE2 is connected. The sense amplifier 1 is connected to the data line pair DL, * DL.

In such a configuration, the connection from the predetermined memory cell MC to the data lines DL and * DL is performed by selecting a predetermined word line WL by a row decoder (not shown) and by connecting a column decoder (not shown). When a predetermined column selection line SEL is selected, the column selection transistors QS1, QS
2 is turned on, a specific bit line pair BL, * B
This is performed by connecting only L to the data lines DL, * DL.

Next, the configuration of the sense amplifier 1 will be described with reference to FIG. As shown in FIG. 1, the sense amplifier 1 includes a separation circuit 10, a current supply circuit 20, a sense circuit 30, a latch circuit 40, and the like.

The isolation circuit 10 is formed by connecting the gates of a pair of nMOS transistors 11 and 12 to each other. As shown in FIG. 1, a control circuit for controlling the activation of the sense amplifier 1 is provided at the gate. Signal EN is input. The drains of the transistors 11 and 12 are connected to the data lines DL and * DL, respectively, and the sources of the transistors 11 and 12 are connected to the current supply circuit 20. Then, the separation signal 10 causes the control signal E
When N is at a logic low (L) level, the sense amplifier 1 is electrically separated from the data lines DL and * DL.

The current supply circuit 20 has four p
MOS transistors 21, 22, 23, and 24. At the start of sensing, the power supply voltage VDD
A current is supplied to the sense line * SL via 1 and 23, and also to the sense line SL via the transistors 22 and 24. The supply is controlled by a pMOS as shown in FIG.
This is performed by a control signal * EN applied to the gates of the transistors 23 and 24. The source outputs of the transistors 23 and 24 are connected to the sense line pair SL, *
The reason for crossing SL is to adjust sense logic. That is, the pMOS transistor 2
According to the characteristics of the gate voltage and the source / drain current of the gate lines 1 and 22, the lower gate voltage (the lower voltage of the pair of sense lines SL and * SL) is turned on first, at which time the power supply voltage VDD This is to supply voltage and current to the sense line on the logical H level side.

The sense circuit 30 includes two CMOSs.
The inputs and outputs of the inverters 31 and 32 are cross-coupled, and the output terminals SA of the inverters 31 and 32 are connected.
O, * SAO to pull-down nMOS transistor 35,
36 are connected. The control signal * EN is applied to the gates of the pull-down nMOS transistors 35 and 36. When the control signal * EN is at the logic H level, the output terminals SAO and * SAO of the inverters 31 and 32
For example, it is equalized to a ground (GND) level.
The source terminals of the pMOS transistors 31a and 32a of the inverters 31 and 32 are connected to the sense line pairs SL and *, respectively.
SL (data line pair DL, * DL), the source terminals of the nMOS transistors 31b, 32b of the inverters 31, 32 are commonly connected, and a switch nMOS transistor 37 is connected to the common connection point. . The control signal EN is applied to the gate of the switch nMOS transistor 37, and when the control signal EN is at the logical H level, the sense circuit 30 (sense amplifier 1) is activated, and the sensing and latching operation of the memory data is started. You.

The data from the sense circuit 30 is sent to the latch circuit 40 from the output terminals SAO and * SAO, and the sense data is latched. As shown in FIG. 1, the latch circuit 40 is a well-known latch circuit composed of two inverter circuits 41 and 42 and two NAND circuits 43 and 44.

Next, the operation of the sense amplifier 1 having the above configuration will be described with reference to a time chart shown in FIG.
Note that, at the time before the time shown in FIG.
L, * BL and the data line pair DL, * DL are precharged to a logic H level by the precharge / equalize circuits PE1, PE2, respectively (FIG. 3).
(B), FIG. 3 (d)). Also, as shown in FIG. 3 (h), the output terminals SAO and * SAO of the sense circuit are equalized to the ground level. Further, it is assumed that the addressing of the memory cell MC from which data is to be read has already been completed.

At time t0 shown in FIG. 3, a word line selection pulse WL and a bit line pair selection pulse SEL for designating a memory cell MC from which data is to be read start rising almost simultaneously, and a predetermined word line WL and It is assumed that bit line pair BL, * BL is selected (FIG.
(A), FIG. 3 (c)). Note that these selection pulses are
Each is generated based on a row address signal and a column address signal (not shown). Then, as shown in FIG. 3B, the bit line pair BL, * B precharged to the logic H level
One of L gradually changes toward the logical L level. Then, as shown in FIG. 3D, in response to the change of the bit line pair BL, * BL, the data line pair DL, * BL
Similarly, one of the DLs slowly changes toward the logic L level.

Next, at time t1 shown in FIG. 3, the control signal EN starts rising and the control signal *
When EN starts to fall, the sense amplifier 1 shown in FIG. 1 is activated. That is, in FIG. 1, the pair of nMOS transistors 11 and 12 of the separation circuit 10 are turned on, and the data line pair DL and * DL and the sense line pair SL and * SL are coupled. Further, the pull-down nMOS transistors 35 and 36 of the sense circuit 30 are turned off.
Then, since the switch nMOS transistor 37 of the circuit 30 is turned “on”, the sense circuit 30 starts the sensing operation.

By the way, the sense amplifier 1 of this embodiment
As described above, since the current supply circuit 20 is provided on the input side of the sense circuit 30, the sensing speed of the sense circuit 30 can be increased. That is, when the control signal * EN falls, the pMOS transistors 23 and 24 of the current supply circuit 20 shown in FIG.
A current corresponding to the gate voltages of the pMOS transistors 21 and 22 of the circuit 20 is applied to the sense circuit 3 via the transistors 23 and 24 by the applied power supply voltage VDD.
0 is supplied. Specifically, the sense line pair SL, * SL
Of the power supply voltage VD
D is applied. The sense line pair S at that time
L, * SL and the sense output SAO, * of the sense circuit 30
The voltage change of the SAO is shown in FIGS. 3 (g) and 3 (h). In FIG. 3G, Vthp is a pMOS
It shows the threshold voltage of the transistor. In FIG. 3H, Vthn shows the threshold voltage of the nMOS transistor. 3 (h) shows the case where the current supply circuit 20 is not provided in the sense amplifier 1. As shown in FIG. 3 (h), when the current supply circuit 20 is provided, the output terminals SAO, * are output.
The SAO voltage changes faster. This is because, as described above, the current is supplied from the power supply voltage VDD to the sense circuit 30 by the current supply circuit 20, and the sense output terminals SAO, * S
AO, that is, the pMOS transistor 31 shown in FIG.
This is because it is possible to charge the drain end of any one of the drain terminals a and 32a to the logic H level more quickly. Note that FIG.
In (h), Vthn indicates a threshold voltage of the nMOS transistor.

Next, the sense output of the sense circuit 30 is input to the latch circuit 40 shown in FIG. 1 and is latched by the latch circuit 40 until the next memory data read operation.
Read data Dout, * Dout are output from sense amplifier output terminals 45a, 45b. FIG. 3I shows the transition of the read data Dout, * Dout.
Note that the broken line in FIG. 3I shows the case where the current supply circuit 20 is not provided, and the arrows in FIG. 3I show the control signals EN and * E.
The time from when the sense amplifier 1 is activated by N to when the read data Dout, * Dout is read out,
That is, it indicates the delay time τd. As shown in FIG. 3I, the delay time τd is shorter than the delay time τd0 when the current supply circuit 20 is not provided because the sense time is reduced by the current supply circuit 20 as described above. FIG. 4 shows the relationship between the delay times τd and τd0 and the bit line potential difference ΔV. As shown in FIG. 4, the delay time τd is greatly improved at a bit line potential difference ΔV equal to or greater than a predetermined value, as compared with the case where the current supply circuit 20 is not provided.

The effects obtained by the above-described embodiment will be described below. (1) According to the present embodiment, the sensing speed of the sense circuit 30 is increased, and the delay time τd from when the sense amplifier 1 is activated to when the read data Dout, * Dout is read is greatly improved. That is, according to the present sense amplifier 1, when reading data from the static RAM, the current supply circuit 20 and the sense circuit 30 are provided, so that the power consumption is low and the access speed can be increased.

(2) According to the present embodiment, since the latch circuit 40 is provided at the subsequent stage of the sense circuit 30, the output terminals SAO, * S of the sense circuit 30 are in the standby state.
AO can be pulled down and equalized to the ground level to prepare for the next operation. Further, the logic H level (logic L level) period and the like of the control signals EN and * EN shown in FIGS. 3E and 3F can be appropriately set.

This embodiment can be embodied with the following modifications. In the present embodiment, the current supply circuit 20 is
, Four pMOS transistors 21,
Although the example constituted by 22, 23, and 24 was shown, it is not limited to this. For example, the current supply circuit 20 may be configured by two nMOS transistors or the like.

In the present embodiment, the sense circuit 3
0 are paired with CMOS inverters 31 and 32
However, the present invention is not limited to this. For example, the inverter may be an MNOS (Metal Nitride Oxide S).
It may be constituted by a field-effect transistor having another structure such as semiconductor. Similarly, the transistors constituting the current supply circuit 20 may be constituted by MNOS or the like.

In this embodiment, an example in which the sense amplifier 1 is applied to a static RAM has been described. However, the present invention is not limited to this.
It may be applied to the M data read circuit.

In addition, technical ideas other than the claims that can be grasped from the embodiment will be described below together with their effects. (1) The semiconductor memory cell is a memory cell constituting a static RAM.
The sense amplifier according to any one of the above.

According to this configuration, the data read operation of the static RAM is further speeded up.

[0031]

According to the first aspect of the present invention, at the time of sensing, current is supplied from the current supply means to the sense section.
It is possible to increase the sensing speed of the sense section.

According to the second aspect of the present invention, at the time of sensing,
The sense unit has low power consumption and can suitably increase its sensing speed. According to the third aspect of the present invention, the current supply unit and the sensing unit can be suitably configured.

According to the fourth aspect of the present invention, the power consumption of the sense amplifier can be further reduced, and the control of the sense unit can be suitably performed. According to the fifth aspect of the present invention, it is possible to suitably configure a sense amplifier which consumes less power and enables a higher-speed read operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a sense amplifier according to the present invention.

FIG. 2 is a configuration diagram illustrating a configuration related to reading of a memory cell;

FIG. 3 is a time chart showing an operation example of the sense amplifier of the embodiment.

FIG. 4 is a diagram showing a relationship between a delay time and a bit potential difference.

FIG. 5 is a circuit diagram showing a conventional sense amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Sense amplifier 10 ... Separation circuit 20 ... Current supply circuit 21,22,23,24 ... PMOS transistor 30 ... Sense circuit 31,32 ... CMOS inverter 35,36 ... Pull down nMOS transistor 37 ... Switch nMOS transistor 40 ... Latch circuit

Claims (5)

[Claims] 1. A sense amplifier provided between a pair of signal lines connected to a memory cell of a semiconductor memory and amplifying a potential difference between the signal lines. A sense amplifier comprising means. 2. The sense amplifier according to claim 1, wherein said sense section amplifies signals on the same pair of signal lines based on a potential difference between said pair of signal lines, and said current supply means includes a same current supply means. A sense amplifier for supplying a current to the unit at the start of sensing. 3. The sense section includes a p-channel field-effect transistor and an n-channel field-effect transistor, and inputs signals from the pair of signal lines to a source side of the p-channel field-effect transistor. A pair of inverters whose inputs and outputs are cross-coupled, an n-channel field-effect transistor connected between the pair of inverters and the ground and turned on at the time of sensing, and connected to each output terminal of the same pair of inverters A pair of pull-down n-channel field-effect transistors for setting the potential of the output terminal to a predetermined level before the start of sensing; And four p-channel field effect transistors for supplying current to the pair of signal lines. 3. The sense amplifier according to claim 1, wherein: 4. The sense amplifier according to claim 2, wherein said sense section and said current supply section are separated from said memory cell when said sense section is inactive, and said isolation section when said sense section is active. And a latch circuit for latching an output of the sense unit. 5. A sense amplifier which is provided between a pair of signal lines connected to a memory cell of a semiconductor memory and amplifies a potential difference between the signal lines. A pair of CMOS inverters that receive signals from signal lines and whose inputs and outputs are cross-coupled, and an n-channel MOS transistor that is connected between the pair of CMOS inverters and the ground and is turned on at the time of sensing. A pair of pull-down n-channel MOS transistors connected to the respective output terminals of the CMOS inverter and setting the potential of the output terminals to a predetermined level before the start of sensing; At the start of sensing of the same sense section, there are four p-channel MOS transistors for supplying current to the pair of signal lines. Current supply means, separation means for separating the sense section and the current supply means from the memory cell when the sense section is inactive, and a latch circuit for latching the output of the sense section when the sense section is active And a sense amplifier comprising: