JP2551346B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a static RAM manufactured by a CMOS process.

[0002]

2. Description of the Related Art A static memory has been devised which uses a current mode sense amplifier for fixing a constant voltage on a bit line and sensing a current flowing through the bit line. Conventionally, this type of current mode sense amplifier is disclosed in, for example, "1991.
April, I EE Journal of the
Solead State Circuit, Volume 26, Issue 4 "
(IEEE JOURNAL OF SOLID ST
ATE CIRCUITS, VOLUME 26, NU
As shown in MBER 4), it is used for the purpose of high-speed sensing and facilitation of timing design.

FIG. 2 is a circuit diagram showing an example of a conventional current mode sense amplifier. The current source 101 and the capacitance 1 in FIG.
02 and the resistor 103 are equivalent circuits of the memory cell. Transistors M1-M4 are CMOS latches. Transistors M5 and M6 are biased in the linear region, clamping the bit line to V _REF . The outputs V _{OUT +} and V _OUT- swing between VDD and V _REF , so V
_REF must be lower than the threshold current.

[0004] This sense amplifier has precharge and sense
Memory access that operates in two phases of signal amplification
To start, turn on transistor M9
Supply current to the pump. Transistors M7 and M8 are pre
It is on during charging and the bit line and output node
Keep equipotential. Transistor M at the end of precharge
7 and M8 turned off, transistors M1-M4 high gay
It works as a positive feedback amplifier. Transistors M1 and M2
The difference in current flowing through the
It is amplified at high speed by the positive feedback of the switch.

[0005]

In this conventional current mode sense amplifier, the bit line voltage is V _REF (GND˜1 /).
Since it is as low as 3 VDA), the noise margin of the memory cell is small. Further, there is a risk of malfunction due to offset voltage due to process variations, which is not practical.

[0006]

The gist of the means for solving the problems is that the precharge circuit (20) composed of the PMOS (8) and the PMOS (9) and the NMOS (1), N.
MOS (2), NMOS (5), NMOS (6) and N
MOS (7) and PMOS (3) and PMOS (4)
Composed of a sense amplifier (22), a memory cell array (21) composed of a plurality of memory cells (10), one NOR gate (13) and two CMOS inverters (1
CMOS inverter (11)
Input is connected to the common gate of PMOS (4) and NMOS (2), and further, PMOS (3) and NMOS (1)
Connected to the common drain of the CMOS inverter (1
The output of 1) is connected to the read data line (15), and C
The input of the MOS inverter (12) is connected to the common gate of the PMOS (3) and the NMOS (1),
Connected to the common drain of (4) and NMOS (2),
The output of the CMOS inverter (12) is connected to the inverted read data line (19), the source of the PMOS (3) is connected to the bit line (17 _), and the source of the PMOS (4) is connected to the bit line (18 ₎ . The common source of the NMOS (1) and the NMOS (2) is connected to the drain of the NMOS (5), and the source of the NMOS (5) is grounded.
The gate of the OS (5) is connected to the read control signal line (16), the drain of the NMOS (6) is connected to the input of the CMOS inverter (11), and the drain of the NMOS (7) is the input of the CMOS inverter (12). Connected to N
The common sources of the MOS (6) and the NMOS (7) are grounded, the common sources of the PMOS (8) and the PMOS (9) are connected to a power source, and the common gates of the PMOS (8) and the PMOS (9) are write control signals. Connected to wire (14),
The memory cell (10) is a PMOS (8) and a PMOS
Connected to the drain of (9), the drain of PMOS (8) is connected to the source of PMOS (3),
The drain of (9) is connected to the source of PMOS (4), the output of NOR gate (13) is connected to the common gate of NMOS (6) and NMOS (7), and the two inputs of NOR gate (13) are The semiconductor memory device is characterized by being connected to a write control signal line (14) and a read control signal line (16), respectively.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a static type memory according to an embodiment of the present invention. In FIG. 1, the static memory is
It comprises a precharge circuit 20, a memory cell array 21, a sense amplifier 22, a write control signal line 14, and a read control signal line 16.

The precharge circuit 20 includes PMOSs 8 and 9
The bit line and the inverted bit line are charged up to the power supply voltage by. The PMOSs 8 and 9 are controlled by a write control signal line (WriteEnable) 14 and fix the bit line and the inverted bit line to the power supply voltage after the write operation is completed. Since the noise margin has a relationship with the precharge voltage as shown in FIG. 3, a sufficient noise margin is obtained by this, and when the decoding is completed, the read control signal line (ReadEnable) 16 is set high.
And start the sense.

Before the start of sensing, the NOR gate 13 causes N
The MOS6, 7 are on and the output of the sense amplifier is lo
It has been pulled to the w level. This makes the PMOS
It is possible to prevent malfunction when L and V _t of 3, 4 and NMOSs 1, 2 vary.

When the NMOS 5 is turned on and the NMOSs 6 and 7 are turned off, a potential difference occurs in the output of the sense amplifier due to the current difference between the bit line 17 and the inverted bit line 18, and this potential difference is amplified at high speed by positive feedback.

[0011]

As described above, according to the present invention, a high noise margin can be obtained by precharging the bit line and the inverted bit line to the power supply voltage. Further, by setting the output of the sense amplifier to the ground level before the start of sensing, it is possible to prevent malfunction due to process variations.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a conventional current mode sense amplifier.

FIG. 3 is a diagram showing a precharge voltage dependency of a noise margin (at a power supply voltage of 3.3V).

[Explanation of symbols]

 1, 2, 5, 6, 7 NMOSFET 3, 4, 8, 8, 9 PMOSFET 10 Memory cell 11, 12 Inverter 13 NOR gate 14 Write control signal line 15 Read data line 16 Read control signal line 17 Bit line 18 Inverted bit Line 19 Inverted read data line 20 Precharge circuit 21 Memory cell array 22 Sense amplifier 101 Current source 102 Capacitance 103 Resistance 104 Bit line 105 Inverted bit line M1, M2, M5, M6 NMOSFET M3, M4, M9 PMOSFET

Claims (2)

(57) [Claims] 1. A precharge circuit (20) comprising a PMOS (8) and a PMOS (9), and NMOS (1), N.
MOS (2), NMOS (5), NMOS (6) and N
MOS (7) and PMOS (3) and PMOS (4)
And a memory cell array (21) including a plurality of memory cells (10), one NOR gate (13), and two CMOS inverters (11, 12), The input of the CMOS inverter (11) is connected to the common gate of the PMOS (4) and the NMOS (2), and the PMO
It is connected to the common drain of S (3) and NMOS (1), the output of the CMOS inverter (11) is connected to the read data line (15), and the input of the CMOS inverter (12) is PMOS (3) and NMOS (1). ) Connected to the common gate of
Connected to the common drain of S (4) and NMOS (2), the output of CMOS inverter (12) is connected to the inverted read data line (19), and the source of PMOS (3) is connected to the bit line (17). The source of the PMOS (4) is connected to the bit line (18), and the common source of the NMOS (1) and the NMOS (2) is NM.
The drain of OS (5) is connected, the source of NMOS (5) is grounded, and the gate of NMOS (5) is a read control signal line (16)
The drain of the NMOS (6) is connected to the CMOS inverter (1
1), the drain of the NMOS (7) is connected to the CMOS inverter (1)
Connected to the input of 2), the common sources of NMOS (6) and NMOS (7) are grounded, the common sources of PMOS (8) and PMOS (9) are connected to the power supply, and PMOS (8) and PMOS (9) ) Is connected to the write control signal line (14), and the memory cell (10) is connected to the PMOS (8) and the PMOS (8).
Connected to the drain of (9), the drain of PMOS (8) is connected to the source of PMOS (3), the drain of PMOS (9) is connected to the source of PMOS (4), and the output of NOR gate (13) Is NMOS (6) and NM
A semiconductor memory device characterized in that it is connected to a common gate of an OS (7), and two inputs of a NOR gate (13) are connected to a write control signal line (14) and a read control signal line (16), respectively. . 2. Before the start of sensing, the NOR gate (13) turns on the NMOS (6) and the NMOS (7),
2. The semiconductor memory device according to claim 1, wherein the read data line (15) and the inverted read data line (19) are kept at a low level.