JPH10199256A - Signal change detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal change detecting circuit which is useful as an address transition detecting circuit which can independently set the optimum values of the widths of a rising edge detecting signal and a falling edge detecting signal of a pulse signal. SOLUTION: A first delay circuit 11 for producing a first delay pulse signal N1 obtained by delaying the rising edge of an address pulse signal AD and a second delay circuit 12 for producing a second delay pulse N3 obtained by delaying the falling edge of the address pulse signal AD are provided in combination. The delay circuits 11, 12 adjust amount of delay with given DC biases VCR, VCF. The first delay pulse signal N1 and address pulse signal AD are input to a first EOR gate 13 to obtain the rising edge detecting signal N2. The second delay pulse signal N3 and address pulse signal AD are input to a second EOR gate 14 to obtain the falling edge detecting signal N4. These detecting signals N2, N4 are combined with an OR gate 15 to obtain an ATD (Address Transition Detecting Circuit) signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal change detection circuit for detecting a pulse signal edge to generate a rise detection signal and a fall detection signal, and more particularly to a signal change detection circuit useful as an address transition detection circuit of a semiconductor memory. It relates to a detection circuit.

[0002]

2. Description of the Related Art Conventionally, there has been known a technique of detecting a transition of a fetched address in a semiconductor memory such as a static RAM and performing a high-speed access operation using the transition detection signal as a timing reference signal.
FIG. 13 shows a schematic configuration of such a semiconductor memory. An external address pulse signal AD is applied to an address buffer 1
31, and is supplied to the memory cell array 133 after being decoded by the decoder 132. The read / write circuit 13 for the selected memory cell
4 reads or writes data. Address pulse signal A taken into address buffer 131
D is an address transition detection circuit (Addr
ESS Transition Detector (hereinafter, referred to as ATD circuit) 135 to detect an edge of the address signal AD, and to perform an address transition detection signal (hereinafter, ATD signal).
Is made. The ATD signal is used as it is as an internal clock signal, or is sent to a clock generation circuit 136 to generate various internal clock signals, and data read / write timing is controlled by these clock signals.

ATD circuit 135 typically includes a delay circuit 141 and an exclusive OR gate 14 as shown in FIG.
2. As shown in FIG. 15, the address pulse signal A is delayed by delaying the address pulse signal AD and exclusive ORing the delayed signal and the original signal.
D rise and fall detection signals are obtained. These detection signals are normally supplied to the NMOS transistor 14 with the PMOS transistor 143 as a load, as shown in FIG.
4 and passed through the inverter 145, A
A TD signal is obtained.

Since the ATD signal serves as a reference for the operation timing of the internal circuit as described above, the pulse width and timing of the ATD signal must be adjusted with high precision in order to ensure high-speed performance of the semiconductor memory. is necessary. However, in the conventional configuration as shown in FIG.
1, the pulse width of the ATD signal ATD1 at the rise and the pulse width of the ATD signal ATD2 at the fall shown in FIG.
Also, variations in the rise delay characteristics affect the fall delay characteristics, which cause variations in the internal circuit operation.

More specifically, as a technique for increasing the speed, there is a data line equalizing operation performed based on an ATD signal. As shown in FIG. 16, a pair of data lines DB1 and DB2 to which a number of memory cells are connected are connected to load NMOS transistors Q1 and Q2.
2 to the power supply VDD. Data line DB
An equalizing NMOS transistor Q3 is provided between 1 and DB2, and is turned on by an equalizing signal EQ prior to selecting a word line.

That is, as shown in FIG.
Prior to timing t3 at which the selected memory cell is switched by WL1 and WL2, equalization signal EQ is output at timing t1.
Rise, and before the timing t2 when the equalize signal EQ is "H", the data lines DB1 and DB2, one of which is "H" and the other is "L", are short-circuited, and both power lines VDD and
(Or VDD / 2). As a result of this equalizing, the data lines DB that have become “H” and “L”
1 and DB2 are set to “L” according to the cell data,
High-speed access becomes possible as compared to the case where the swing is made full to “H”. If the timing and width of the equalization signal EQ vary, there is a problem that equalization is insufficient or a high-speed access operation is hindered.

[0007]

As described above, the width and timing of the equalizing signal EQ are important for high-speed operation. Therefore, the width and timing of the ATD signal that is the basis of the equalizing signal EQ are important. FIG.
In the conventional ATD circuit shown in (1), the width and timing of the ATD1 signal at the time of rising and the ATD2 signal at the time of falling cannot be controlled independently. In particular, the variation in the width of the ATD1 signal at the time of falling cannot be controlled. Affects width directly. In order to realize a stable high-speed operation of the static RAM, it is desired that the width of the ATD signal at the time of rising and falling can be independently set to the optimum state without being affected by manufacturing variations.

The present invention has been made in view of the above circumstances, and has a signal change useful as an address transition detection circuit in which the widths of a rising detection signal and a falling detection signal of a pulse signal can be independently and optimally set. It is intended to provide a detection circuit.

[0009]

According to the present invention, there is provided a signal change detection circuit for detecting an edge of a pulse signal to generate a rising detection signal and a falling detection signal, wherein the rising of the pulse signal is performed for a first set time. Delayed first
A first delay circuit for generating a delayed pulse signal, a pulse width corresponding to the first set time at a rising edge of the pulse signal by detecting an overlapping state of the first delayed pulse signal and the pulse signal A first logic gate for generating a rising detection signal, a second delay circuit for obtaining a second delay pulse signal obtained by delaying the falling of the pulse signal by a second set time, and the second delay A pulse signal and a second logic gate that detects an overlapping state of the pulse signal and generates a falling detection signal corresponding to the second set time at a falling edge of the pulse signal. I have.

Preferably, in the present invention, the first delay circuit includes a first inverter having a first current-limiting element whose conductance is controlled by a first DC bias, and the first inverter And a second inverter for inverting the output of the second inverter is connected in series with n stages (n is a positive integer), and the second delay circuit has a conductance on the power supply side by a second DC bias. Is controlled by a third inverter having a second current limiting element interposed therebetween and a fourth inverter for inverting the output of the third inverter, and the falling delay element is provided in m stages (m is a positive delay element). (Integer) connected in series, and the first and second logic gates are each constituted by an exclusive OR gate.

In a preferred embodiment of the present invention, the first current limiting element is a first NMOS transistor, and as means for applying the first DC bias, a constant voltage is applied to the gate of the first NMOS transistor. A first constant voltage circuit including a diode-connected second NMOS transistor for providing the second current limiting element, wherein the second current limiting element is a first PMOS transistor;
The first PMO
A second PMOS transistor including a diode-connected second PMOS transistor for applying a constant voltage to the gate of the S transistor;
It has a constant voltage circuit.

The signal change detection circuit according to the present invention further comprises:
The pulse signal is applied to an address transition detection circuit of a semiconductor memory as an address pulse signal.

According to the present invention, the first delay circuit for delaying the rise of the pulse signal and the second delay circuit for delaying the fall are separately provided, and the rise detection signal and the fall detection signal are obtained from each. It is composed.
Therefore, variations in the rise detection signal do not affect the fall detection signal, and the rise detection signal and the fall detection signal can be used as they are, or can be combined and used as a stable timing reference signal. In particular, if the first delay circuit and the second delay circuit are provided with a current limiting element capable of controlling the conductance by a DC bias so that the delay amount can be controlled, respectively, the rise detection signal and the fall detection signal can be controlled. The pulse width can be set independently and optimally.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an ATD circuit according to one embodiment of the present invention. A first delay circuit 11 that generates a first delay pulse signal N1 that delays the rise of an address pulse signal AD taken from outside, and a second delay pulse N3 that similarly delays the fall of the address pulse signal AD And a second delay circuit 12 for generating the same. The first delay circuit 11 is supplied with a first DC bias VCR to control the rising delay amount. Similarly, the second delay circuit 12 is supplied with a second DC bias VCF to control the amount of delay in falling. The details will be described later.

As a first logic gate for detecting a state of overlap between the first delay pulse signal N1 and the address pulse signal AD and generating a rising detection signal N2 at a rising edge of the address pulse signal AD, a first exclusive logic is used. Sum (EO
R) A gate 13 is provided, similarly detects the overlapping state of the second delay pulse signal N3 and the address pulse signal AD and generates a falling detection signal N4 at the falling edge of the address pulse signal AD. As the gate, the second
EOR gate 14 is provided. The detection signals N2 and N4 obtained from the EOR gates 13 and 14 are combined by the OR gate 15 to obtain an ATD signal.

As shown in FIG. 2, first delay circuit 11 generally has n stages, and in the case shown in FIG.
1 to RD3 are connected in series. The rising delay element RD1 has a PMOS transistor QN21 as a first current limiting element whose conductance is controlled by a first DC bias VCR on the ground side.
A first CMOS inverter I11a comprising an S transistor QP11 and an NMOS transistor QN11, and a second CMOS inverter I11a for inverting the output of the first CMOS inverter I11a.
MOS inverter I11b. It is assumed that the NMOS transistor QN21 has a sufficiently large ratio L / W of the channel length L and the channel width W as compared with other switching transistors, and therefore has a large on-resistance. Other delay elements RD2 and RD3 are similarly configured.

As shown in FIG. 4, the second delay circuit 12 generally has m stages, and in the case shown in FIG.
1 to FD4 are connected in series. The falling delay element FD1 has a PMOS transistor QP31 as a second current limiting element whose conductance is controlled by a second DC bias VCF on the power supply side.
A third CMOS inverter 21a comprising an S transistor QP21 and an NMOS transistor QN31;
Fourth CM for inverting the output of MOS inverter I21a
OS inverter I21b. The PMOS transistor QP31 is different from other switching transistors in that
It is assumed that L / W is sufficiently large and therefore the on-resistance is large. The same applies to the other delay elements FD2 to FD4.

The operation of the ATD circuit thus configured will be described below. First, focusing on one rising delay element RD1 of the first delay circuit 11, a current limiting NMOS transistor QN21 is inserted on the ground side of the first-stage CMOS inverter I11a. This NMOS transistor Q
N21 is lower than driver NMOS transistor QN11.
/ W is set large and a predetermined DC bias VCR is applied to the gate. Thereby, the driver NMO
When the S-transistor QN11 turns on, the load discharge is limited and a predetermined delay occurs. On the other hand, assuming that the PMOS transistor QP11 has a sufficient drive capability, the output N11 of the first-stage CMOS inverter I11a has a gentle fall as shown in FIG. 3, and the output N12 of the second-stage CMOS inverter I11b has an address pulse. This is a signal obtained by delaying only the rise of the signal AD by τ1.

The rise is similarly delayed in the remaining rise delay elements RD2 and RD3. Therefore, as shown in FIG. 6, the first delay circuit 11 has a delay of n × τ1 as the first set time as shown in FIG. Thus, one delayed pulse signal N1 is obtained. Then, a rising detection signal N2 having a pulse width of n × τ1 as shown in FIG. 6 is obtained by an exclusive OR of the first delay pulse signal N1 and the address pulse signal AD.

Next, focusing on the falling delay element FD1 of the second delay circuit 12, the current limiting PMOS on the power supply side is used.
The transistor QP31 is a driver PMOS transistor Q
L / W is set larger than P21, and a predetermined DC bias VCF is applied to the gate. This allows
A predetermined delay occurs in load charging when driver PMOS transistor QP21 is turned on. Assuming that the NMOS transistor QN31 has a sufficient driving capability, the output N21a of the first-stage CMOS inverter I21a has a gentle rising as shown in FIG. 5, and the output N32 of the second-stage CMOS inverter I21b has the address pulse signal AD. Is a signal obtained by delaying only the falling edge of.

The falling is similarly delayed in the remaining delay elements FD2 to FD4. Therefore, as shown in FIG. 6, the second delay circuit 12 sets m × τ2 as the second delay time.
A second delayed pulse signal N3 having a falling delay of By the exclusive OR of the second delay pulse signal N3 and the address pulse signal AD, as shown in FIG.
A falling detection signal N4 having a pulse width of m × τ2 is obtained.

Actually, in the first delay circuit 11 and the second delay circuit 12, there are slight falling delay and rising delay, respectively, and therefore, as shown in FIG. P2 occurs. However, when the rising detection signal N2 and the falling detection signal N4 are combined by the OR gate 15, these signals are absorbed by the final ATD signal, so that they have no adverse effect.

As described above, according to this embodiment, the ATD signal is generated by delaying the rise and fall of the address pulse signal AD by independent circuit paths provided together, so that the ATD obtained at the rise of the address pulse signal AD The width of the ATD signal obtained at the falling edge of the signal and the address pulse signal is independently and optimally set, and variations in the pulse widths do not affect each other.

In the above embodiment, in order to obtain an ATD signal having a substantially constant width even if there are variations in the manufacturing conditions, the DC biases VCR and VCF are set so as to cancel out the effects of the variations in the manufacturing conditions. It is desirable that the variable control be performed automatically. An embodiment having a DC bias circuit having such an automatic adjustment function will be described below.

FIG. 7 shows the configuration of one rising delay element RD used in the first delay circuit 11 described above. As a first DC bias circuit for applying a bias VCR to the gate of an NMOS transistor QN2 (corresponding to QN21, QN22 and QN23 shown in FIG. 2) as a current limiting element, a diode-connected NMOS transistor QN4 as a constant voltage element A first constant voltage circuit 16 combining resistors R1 and R2 is used. The NMOS transistor QN4 is
It is assumed that they are formed at positions close to each other under the same process conditions as the NMOS transistor QN2.

With such a configuration, for example, the threshold value V of the NMOS transistor QN2 may vary depending on the variation in manufacturing conditions.
It is assumed that the direction fluctuates in a direction in which thn becomes higher, that is, a direction in which channel conductance becomes smaller. At this time, the threshold value of the NMOS transistor QN4 of the constant voltage circuit 16 also increases, and the NMOS transistor QN4 fluctuates in a direction to increase the constant voltage output. That is, the DC bias VCR increases, and the NMOS transistor Q
It works to increase the conductance of N2. From the above,
The influence of the variation in the manufacturing conditions is offset, and a certain rise delay characteristic can be obtained.

FIG. 8 shows the configuration of one falling delay element FD used in the second delay circuit 12 whose bias is automatically adjusted in the same manner. As a second DC bias circuit for applying a bias VCF to the gate of the current limiting PMOS transistor QP3 (corresponding to QP31, QP32 and QP33 in FIG. 4), a diode-connected PMOS transistor QP4 is used as a constant voltage element, and resistors R3 and R4 are used. The second combining
Is used. It is assumed that the PMOS transistor QP4 is formed at a position close to each other under the same process conditions as the PMOS transistor QP3.

In this case, due to variations in the manufacturing conditions, P
Assuming that the threshold voltage | Vthp | of the MOS transistor QP3 changes in the direction of increasing, that is, in the direction of decreasing the channel conductance, the threshold value of the PMOS transistor QP4 of the constant voltage circuit 17 also increases and the constant voltage output decreases. Fluctuating in the direction. That is, the DC bias VCF decreases, and the conductance of the PMOS transistor QP3 increases. Therefore, the influence of the variation in the manufacturing conditions is canceled, and a certain fall delay characteristic can be obtained.

FIG. 9 shows an example in which the first delay circuit 11 shown in FIG. 2 is modified.
A single current limiting NMOS transistor QN2 is provided. Similarly, FIG.
Is a modified example of the delay circuit 12 in which a single current limiting PMOS transistor QP3 is provided for a plurality of falling delay elements FD. Even if such a delay circuit configuration is used, the same operation as in the previous embodiment can be performed.

FIG. 11 shows an ATD circuit according to another embodiment, and FIG. 12 is an operation timing chart thereof. In contrast to FIG. 1, in this embodiment, the first delay circuit 11 adds an inverter I3 to a plurality of rising delay elements RD similar to the embodiment of FIG. 1 and inverts the phase as shown in FIG. First
Is obtained. Then, the rising detection signal N2 whose polarity is inverted from that of the previous embodiment is obtained by the NAND gate 16 which receives the delay pulse signal N1 and the address pulse signal AD as inputs.

The second delay circuit 12 comprises a plurality of falling delay elements FD, as in the embodiment of FIG.
The delay pulse signal N3 and the address pulse signal AD obtained by the second delay circuit 12 are input to E.
By using the NOR gate 14, a falling detection signal N4 whose polarity is inverted from that of the previous embodiment is obtained. If these detection signals N2 and N4 are combined and taken out by CMOS inverter I4 as shown in FIG. 11, ATD similar to that of the previous embodiment can be obtained.
A signal is obtained.

According to this embodiment, the first delay circuit 11
On the side, only the rising delay is detected, and at the time of falling, the whisker-like pulse as shown in FIG. 6 is not generated. Therefore, it is effective when the rising detection signal N2 is used alone as an internal clock or used alone as a reference timing signal of the internal clock.

The present invention is not limited to the above embodiment. For example, in the embodiment, the case where the present invention is applied to an ATD circuit of a semiconductor memory has been described. be able to.

[0034]

As described above, according to the present invention, the first delay circuit for delaying the rise of the pulse signal and the second delay circuit for delaying the fall are separately provided, and the rise detection signal is provided from each. The first delay circuit and the second delay circuit are provided with DC bias means for controlling the amount of delay, respectively, so that the widths of the rise detection signal and the fall detection signal are reduced. Since the optimum setting can be made independently, the rise detection signal and the fall detection signal can be used as stable timing reference signals without variation in the rise detection signal affecting the fall detection signal.

[Brief description of the drawings]

FIG. 1 shows a configuration of an ATD circuit according to an embodiment of the present invention.

FIG. 2 shows a configuration of a first delay circuit of the embodiment.

FIG. 3 is a diagram for explaining an operation of a delay element of the first delay circuit.

FIG. 4 shows a configuration of a second delay circuit of the embodiment.

FIG. 5 is a diagram for explaining an operation of a delay element of a second delay circuit.

FIG. 6 is a diagram for explaining the operation of the ATD circuit of the embodiment.

FIG. 7 shows a configuration of a rise delay element of another embodiment.

FIG. 8 shows a configuration of a fall delay element of another embodiment.

FIG. 9 shows a configuration of a first delay circuit of another embodiment.

FIG. 10 shows a configuration of a second delay circuit according to another embodiment.

FIG. 11 shows a configuration of an ATD circuit of another embodiment.

FIG. 12 is a diagram for explaining the operation of the embodiment.

FIG. 13 shows a schematic configuration of a static RAM having an ATD circuit.

FIG. 14 shows a configuration of a conventional ATD circuit.

FIG. 15 is a diagram illustrating the operation of a conventional ATD circuit.

FIG. 16 shows a configuration of a data line equalizing circuit of a static RAM.

FIG. 17 is a diagram illustrating an operation of data line equalization.

[Explanation of symbols]

11 ... first delay circuit, 12 ... second delay circuit, 13 ...
First EOR gate, 14... Second EOR gate, 15
... OR gate, RD1 to RD3 ... Rise delay element, F
D1 to FD4 fall delay elements, VCR, VCF DC bias, I11a, I12a, I13a first CMOS inverter, I11b, I12b, I13b second CMOS inverter, I21a, I22a, I23a, I24a third CM
OS inverters, I21b, I22b, I23b, I24b ... fourth CMOS inverters, QN21, QN22, QN23 ... current limiting NMOS transistors, QP31, QP32, QP3
3 ... PMOS transistor for current limiting, 16 ... first constant voltage circuit, 17 ... second constant voltage circuit.

Claims (4)

[Claims] 1. A signal change detection circuit for detecting an edge of a pulse signal to generate a rise detection signal and a fall detection signal, wherein a first delay pulse in which the rise of the pulse signal is delayed by a first set time A first delay circuit for generating a signal, detecting an overlapping state of the first delayed pulse signal and the pulse signal, and detecting a rising edge of a pulse width corresponding to the first set time at a rising edge of the pulse signal A first logic gate for generating a signal, a second delay circuit for obtaining a second delay pulse signal obtained by delaying a fall of the pulse signal by a second set time, and a second delay pulse signal. A second logic circuit for detecting an overlapping state of the pulse signals and generating a falling detection signal having a pulse width corresponding to the second set time at a falling edge of the pulse signal; Signal change detection circuit comprising: the bets, the. 2. The first delay circuit according to claim 1, wherein the first delay circuit includes a first current limiting element whose conductance is controlled by a first direct current bias on a ground side, and a first inverter having a first current limiting element interposed therebetween. A rising delay element consisting of a second inverter for inverting the output is connected in series with n stages (n is a positive integer), and the second delay circuit has a conductance on the power supply side due to a second DC bias. A falling delay element composed of a third inverter having a controlled second current limiting element interposed and a fourth inverter for inverting the output of the third inverter is provided in m stages (m is a positive integer) 2. The signal change detection circuit according to claim 1, wherein the first and second logic gates are each configured by an exclusive OR gate. 3. The device according to claim 1, wherein the first current limiting element is a first NM.
An OS transistor, wherein the means for applying the first DC bias includes a diode-connected second element for applying a constant voltage to the gate of the first NMOS transistor;
A first constant voltage circuit including a first NMOS transistor, the second current limiting element is a first PMOS transistor, and
3. The signal change detection circuit according to claim 2, further comprising a second constant voltage circuit including a diode-connected second PMOS transistor for applying a constant voltage to the gate of the PMOS transistor. 4. The semiconductor device according to claim 1, wherein said pulse signal is an address pulse signal of a semiconductor memory.
The signal change detection circuit according to any one of the above.