JPH04278295A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve sensing sensibility by alleviating a short-channel effect of a transistor, reducing an irregularity in a threshold voltage and reducing an irregularity in sensing sensitivity. CONSTITUTION:A well potential controller 3 for controlling a well potential Vw of first, second transistors Q11, Q12 for constituting a flip-flop type sense amplifier 1 is provided. The potential Vw is a potential V1 when a drive control signal SAN is between an intermediate potential (Vm) and the potential V1, and a power source potential Vss between the potential V1 and the potential Vss.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory equipped with a flip-flop type sense amplifier circuit that amplifies the potential difference between a pair of digit lines at a predetermined timing.

0002

2. Description of the Related Art Conventionally, this type of semiconductor memory has been provided with N-type first and second transistors Q11 and Q forming a first flip-flop circuit, as shown in FIG.
12 and P-type first and second transistors Q21 and Q22 forming a second flip-flop circuit, and drive control signals SAN and SAP supplied between the sources of these transistors are activated from an inactive level. digit lines DL1 and D become active when the level changes to
It includes a sense amplifier circuit 1b that amplifies the potential difference between L2 and P-type and N-type transistors Q1 and Q2, and a control signal S.
When E1 and SE2 change from the inactivation level to the activation level, the first and second The configuration includes a drive control circuit 2 that generates drive control signals SAN and SAP that change to activation levels of power supply potentials Vss and Vdd, respectively.

Furthermore, a first power supply potential Vss is applied to the wells (back gates) of the first and second N-type transistors Q11 and Q12, and the first and second power supply potentials Vss of the first and second P-type transistors Q21 and Q22 are applied. A second power supply potential Vdd was applied to the well (back gate).

After the data from the memory cell is read and a signal with a small potential difference appears between the digit lines DL1 and DL2, the drive control signals SAN and SAP change to the activation level power supply potentials Vss and Vdd, Sense amplifier circuit 1b is activated.

At this time, N-type transistors Q11 and Q
12, these transistors Q11, Q1
2 threshold voltages Vt are Vt(Q11) and Vt(Q
12), the deterioration in sense sensitivity due to variations in threshold voltage Vt corresponds to |Vt(Q12)−Vt(Q12)|. Similarly, the deterioration in sensitivity due to variations in threshold voltage Vt of P-type transistors Q21 and Q22 is |Vt(Q
21)-Vt(Q22)|

On the other hand, as integration progresses, the pitch of the digit lines becomes smaller, and as a result, the gate length of the transistor constituting the flip-flop becomes extremely short, resulting in a significant drop in threshold voltage Vt due to the short channel effect.

FIG. 6 shows the relationship between the absolute value of the threshold voltage Vt and the gate length of a typical transistor. As the gate length becomes shorter, the slope of the threshold voltage Vt with respect to the gate length increases, so the variation in the threshold voltage Vt with respect to the variation in the gate length increases, and |Vt(Q11)-Vt(Q12)|,
The value of |Vt(Q21)−Vt(Q22)| increases, and the sense sensitivity deteriorates.

[0008] Furthermore, the short channel effect becomes more significant as the well potential is higher in P-type transistors and as the well potential is lower in N-type transistors.
Although it is desirable that the potential difference between the well and the source be as small as possible, each transistor Q11 of the sense amplifier circuit 1b,
Since the source potentials of Q12, Q21, and Q22 change during the sensing period, in order to prevent forward current from flowing through the PN junction of each transistor, the P-type transistors Q21 and Q2 must be
The potential of the wells of N-type transistors Q21 and Q22 is fixed at the highest potential applied to the common source, that is, the power supply potential Vdd, and the potential of the wells of N-type transistors Q21 and Q22 is fixed to the lowest potential applied to the common source, that is, the power supply potential. Fixing it to Vss was the method of setting the well potential that gave the best sense sensitivity.

For example, the precharge potential is set to 2.5V, the drive control signal SAP is set from the inactivation level of 2.5V to 5V, and the drive control signal SAN is set to the inactivation level of 2.5V.
．． If the voltage is to be changed from 5V to 0V, the potential of the wells of transistors Q11 and Q12 must be set to 0V, and the potential of the wells of transistors Q21 and Q22 must be set to 5V. Now, set the threshold voltage of all transistors to 0.7.
V, the common source at the starting point of the sense amplifier circuit 1b is P-type transistors Q21 and Q22 (2
．． 5+0.7)V, or 3.2V, and (2.5-0.7)V, or 1.8V, for N-type transistors Q11 and Q12, and the potential difference between the source and well is 1.8V in both cases. It could not be lower than this.

0010

Problem to be Solved by the Invention In this conventional semiconductor memory, the transistor Q constituting the sense amplifier circuit 1b
Since the wells of 11, Q12, Q21, and Q22 are fixed to the power supply potential Vdd for P-type transistors and to the power supply potential Vss for N-type transistors, the difference in potential between the well and the source is kept below a certain value. Therefore, each transistor must be used at an operating point where the short channel effect is strong, which increases the variation in sense sensitivity and makes it difficult to improve the sense sensitivity.

[0011]

[Means for Solving the Problems] A semiconductor memory according to the present invention includes first and second transistors, which are activated when a drive control signal reaches an activation level to reduce the potential difference between the first and second digit lines. a flip-flop type sense amplifier circuit for amplification; a drive control circuit for generating the drive control signal that changes from an inactivation level to an activation level when the control signal becomes an activation level; When the drive control signal changes from the inactivation level to the activation level, the drive control signal changes from a first level between the inactivation level and the activation level of the drive control signal to the well of the transistor. The well potential control circuit applies a well potential that changes to an activation level.

0012

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory shown in FIG. Intermediate potential between Vss and Vdd (
Vm) to the first potential V1 between this intermediate potential (Vm) and the power supply potential Vss, the first potential V
1. A well potential control circuit 3 is provided which applies a well potential Vw which becomes the power supply potential Vss when it is between the first potential V1 and the power supply potential Vss to the wells of the transistors Q11 and Q12.

Next, the operation of this embodiment will be explained.

FIG. 2 is a waveform diagram of various signals for explaining the operation of this embodiment.

When the control signals SE1 and SE2 are at the inactivation level of the power supply potentials Vdd (5V) and Vss (0V), respectively, the drive control signals SAN and SAP are at the intermediate potential Vm (2V).
．． 5V), the sense amplifier circuit 1 is in an inactive state, and the digit lines DL1 and DL2 are precharged to an intermediate potential Vm.

The potential V1 (1.5V) is supplied to the inverting input terminal (-) of the differential amplifier 31, and the non-inverting input terminal (
+) is supplied with a drive control signal SAN.

When the potential of the drive control signal SAN is higher than the potential V1, a high potential is output to the output terminal of the differential amplifier 31, the transistor Q3 is turned on, the transistor Q4 is turned off, and the well potential Vw is is equal to the potential V1.

When the control signals SE1 and SE2 reach the activation level of the power supply potentials Vss and Vdd, respectively, the drive control signal SAN approaches the power supply potential Vss, and the drive control signal SA
P approaches the power supply potential Vdd. That is, at the beginning of the operation of the sense amplifier circuit 1 (early stage of activation), the well potential Vw of the N-type transistors Q11 and Q12 is V1 (1.5V).
Therefore, the potential is set higher than the ground potential.

When the sensing operation progresses and the drive control signal SAN becomes a potential lower than the potential V1, the transistor Q3 is turned off, the transistor Q4 is turned on, and the well potential Vw becomes the power supply potential Vss, that is, the ground potential.

Therefore, the potential difference between the sources and wells of the transistors Q11 and Q12 is reduced, the short channel effect is alleviated, and variations in threshold voltage can be reduced even when the gate length is short.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, a P-type transistor Q21
, Q22 are controlled.

The well potential control circuit 3a of this embodiment is as follows:
Drive control signal SAP is input to the inverting input terminal (-), and power supply potential Vdd (5V) and intermediate potential Vw are input to the non-inverting input terminal (+).
(2.5V), an inverter IV that inverts the output of this differential amplifier 31, and an inverter IV that inputs the output of the differential amplifier 31 to its gate. A P-type transistor Q5 whose source is supplied with a potential V2 and outputs a well potential Vwa from its drain, whose gate receives the output of an inverter IV, whose source is connected to the drain of the transistor Q5, and whose drain receives a drive control signal SA.
The configuration includes a P-type transistor Q6 that inputs P.

FIG. 4 is a waveform diagram of various signals for explaining the operation of this embodiment.

The basic operation and effects of this embodiment are as follows.
Since this is the same as the embodiment, the description thereof will be omitted.

In these embodiments, the well potential of either the N-type transistor or the P-type transistor is controlled while the other is fixed. The well potentials of both transistors may be controlled together.

[0029]

As described above, the present invention has a configuration in which a well potential control circuit is provided to control the potentials of the wells of the first and second transistors of a flip-flop type sense amplifier circuit. Since the potential difference between the source and well of the first and second transistors can be reduced, the short channel effect of the transistor can be alleviated, and therefore, even if the gate length of the transistor is shortened, variations in threshold voltage can be suppressed. This has the effect of reducing the variation in sense sensitivity and improving the sense sensitivity.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram of signals of various parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

4 is a waveform diagram of signals of various parts for explaining the operation of the embodiment shown in FIG. 3; FIG.

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor memory.

6 is a waveform diagram of signals of various parts for explaining the operation of the semiconductor memory shown in FIG. 5; FIG.

[Explanation of symbols]

1, 1a, 1b Sense amplifier circuit 2 Drive control circuit 3, 3a Well potential control circuit 31 Differential amplifier DL1, DL2 Digit line IV Inverter Q1 to Q5, Q11, Q12, Q21, Q22
transistor

Claims (2)

[Claims] 1. A flip-flop type sense amplifier circuit comprising first and second transistors and activated when a drive control signal reaches an activation level to amplify a potential difference between the first and second digit lines. , a drive control circuit that generates the drive control signal that changes from an inactivation level to an activation level when the control signal becomes an activation level;
and when the drive control signal changes from the inactivation level to the activation level, the drive control signal changes from the first level between the inactivation level and the activation level of the drive control signal to the well of the second transistor. A semiconductor memory comprising: a well potential control circuit that applies a well potential that changes to an activation level of a control signal. 2. The semiconductor memory according to claim 1, wherein the well potential control circuit is a circuit that controls the level of the well potential based on the level of the drive control signal.