KR100436052B1 - Sram reducing leakage current by controlling well electric potential of sram cell - Google Patents

Abstract

PURPOSE: An SRAM(Static Random Access Memory) is provided to reduce leakage current by controlling well electric potential using a well electric potential control circuit. CONSTITUTION: A memory cell of an SRAM includes a pair of load transistors(MP21,MP22) and driver transistors(MN21MN22) as a latch, and a pair of access transistors(MN23,MN24). A source-drain path of the access transistor is connected between a bit line and a bit line bar, and a gate is connected to a word line. The SRAM further includes well electric potential control circuits(234,235). The well electric potential control circuits supply a relatively high electric potential at a stand-by mode and supply a relatively low electric potential at an operation mode.

Description

SRAM reduces leakage current through well potential control of SRAM cell

The present invention relates to a static random access memory (SRAM) that reduces leakage current through well potential control of a memory cell.

In general, in a conventional static random access memory (SRAM), a well constituting a memory cell is fixedly connected to a ground voltage Vss, and thus a junction leakage current flowing in the memory cell. In addition, the transistor off leakage current (transistor off leakage current) is not reduced, and the power consumption increases in stand-by mode when the threshold voltage of the cell is lowered to operate at a low voltage.

1 is a circuit diagram of a conventional SRAM cell. Referring to the drawings, a conventional SRAM cell includes two load PMOS transistors MP1 and MP2 (load elements may be composed of resistors) and driver NMOS transistors MN1 and MN2 constituting a latch. A source-drain path is connected between two complementary output nodes of a latch and corresponding bit lines / bit line bars, and a pair of access NMOS transistors MN3 and MN4 having word lines connected to gates. In the drawing, the pull-up circuit connected to the bit line is the core circuit of the SRAM not included in the SRAM cell.

The driver NMOS transistor and the access NMOS transistor constituting the cell are formed in the P type well of the semiconductor substrate, and the well voltage is fixed to the ground. Therefore, the junction leakage current of the memory cell or the leakage current in the transistor turn-off state is not reduced, and the power consumption increases in the standby mode when the threshold voltage of the cell is lowered to operate at a low voltage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an SRAM for reducing data leakage current in a memory cell in a standby mode, thereby improving data storage capability, and allowing a cell to operate normally in a normal operation mode.

1 is a circuit diagram of a conventional SRAM cell.

2 is a circuit diagram of a well potential control circuit in an SRAM cell according to the present invention;

<Explanation of symbols for the main parts of the drawings>

211 ... ground voltage 222 ... well voltage

234 ... voltage divider 235 ... reverse inverter

The SRAM of the present invention for achieving the above object,

A pair of access elements, each of which includes a load element and driver transistor constituting a latch, a source-drain path connected between the two complementary output nodes of the latch, and a bit line / bit line bar corresponding thereto, and a word line connected to the gate. A memory cell comprised of a transistor,

A well of the memory cell receives a voltage from a well potential control circuit part in a state electrically isolated from a ground power supply terminal.

The well potential control circuit unit supplies a relatively high potential in the standby mode, and supplies a relatively low potential in the operation mode.

As described above, the SRAM according to the present invention reduces the leakage current by raising the well potential in the stand-by mode through the cell potential control circuit and controlling the well potential in the normal operation mode. Can be.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

2 is a circuit diagram of a well potential control method of a cell in an SRAM according to the present invention. Referring to the drawings, the SRAM cell includes two load PMOS transistors MP21 and MP22 (load elements may be composed of resistors) and driver NMOS transistors MN21 and MN22 constituting a latch. A source-drain path is connected between two complementary output nodes and corresponding bit lines / bit line bars, and a pair of access NMOS transistors MN23 and MN24 are connected to a word line at a gate thereof. In the drawing, the pull-up circuit connected to the bit line is the core circuit of the SRAM not included in the SRAM cell.

Unlike in the related art, wells in which the driver transistors MN21 and MN22 and the exciter transistors MN23 and MN24 constituting cells are not fixed to the ground potential VSS but are separated from each other. The wells of the memory cell are supplied with different levels of well potentials 222 in the standby mode and the operation mode through the well potential control circuits 234 and 235.

The well potential control circuits 234 and 235 are connected between a supply voltage supply terminal and a ground voltage supply terminal, and have a voltage divider circuit 234 for active resistance consisting of two NMOS transistors receiving a chip enable signal through a gate. A reverse inverter circuit 235 connected in series between the power supply voltage terminal supplied from the distribution circuit 234 and the ground power supply terminal and receiving the chip enable signal through a gate and outputting a well potential 222.

The chip enable signal 238, which is an input signal of the voltage distribution circuit 234 and the reverse inverter circuit 235, is a signal having a high or low state depending on the operation state of the SRAM circuit. In mode it is a low level signal.

As a result, in the SRAM according to the present invention, in the state where the ground voltage 211 and the well voltage 222 are separated, the well potential control circuits 234 and 235 are relatively in the standby mode (chip enable signal 'high'). The high voltage is supplied as the well potential 222. This reduces the leakage current to the node side, which causes power consumption in the standby mode, and reduces the leakage current flowing from the bit line and the bit line bar to the ground voltage terminal. In operation mode (a chip enable signal 'low'), a relatively low voltage (voltage used for VSS) is supplied as the well potential 222 of the cell, thereby performing normal operation.

Since the well potential control circuits 234 and 235 are implemented in the SRAM decoder circuit in the SRAM, the well potential control circuit units 234 and 235 may be implemented with the existing SRAM cell without additional area.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, in the well potential control method in an SRAM cell of a semiconductor memory device, a well potential control circuit is added to increase the well potential in the stand-by mode to reduce the leakage current, and in the normal operation mode. It is possible to provide a well potential control method in an SRAM cell in normal operation.

Claims (3)

A pair of access elements, each of which includes a load element and driver transistor constituting a latch, a source-drain path connected between the two complementary output nodes of the latch, and a bit line / bit line bar corresponding thereto, and a word line connected to the gate. A memory cell comprised of a transistor, A well of the memory cell receives a voltage from a well potential control circuit part in a state electrically isolated from a ground power supply terminal. The well potential control circuit unit supplies a relatively high potential in the standby mode and a relatively low potential in the operation mode. Sram characterized in that. The method of claim 1, The well potential control circuit part may include a voltage distribution circuit for an active resistor including two NMOS transistors connected in series between a supply voltage supply terminal and a ground voltage supply terminal and receiving a chip enable signal through a gate; And And an inverting inverter circuit connected in series between a power supply voltage terminal supplied from the voltage distribution circuit and a ground power supply terminal and receiving the chip enable signal through a gate and outputting a well potential. The method of claim 2, The chip enable signal is a signal having a 'high' level in the standby mode of the SRAM and a 'low' level in the operation mode.