JPH06350050A - Method for forming dielectric insulating film film in charge storage part of semiconductor - Google Patents
Method for forming dielectric insulating film film in charge storage part of semiconductorInfo
- Publication number
- JPH06350050A JPH06350050A JP5137579A JP13757993A JPH06350050A JP H06350050 A JPH06350050 A JP H06350050A JP 5137579 A JP5137579 A JP 5137579A JP 13757993 A JP13757993 A JP 13757993A JP H06350050 A JPH06350050 A JP H06350050A
- Authority
- JP
- Japan
- Prior art keywords
- pzt
- film
- forming
- plzt
- charge storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000002425 crystallisation Methods 0.000 claims abstract description 10
- 230000008025 crystallization Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 238000005546 reactive sputtering Methods 0.000 claims description 7
- 101000972349 Phytolacca americana Lectin-A Proteins 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 11
- 239000010408 film Substances 0.000 description 39
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000003746 surface roughness Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003980 solgel method Methods 0.000 description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子（ＬＳＩ）
に係り、特にＤＲＡＭの電荷蓄積部の誘電体絶縁膜にＰ
ＺＴ、ＰＬＺＴを用いる場合の形成方法に関するもので
ある。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device (LSI).
In particular, the P dielectric layer in the charge storage part of the DRAM is
The present invention relates to a forming method using ZT or PLZT.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、 （１）「Ｃ．Ｋ．Ｋｗｏｋ ｅｔ ａｌ．「Ｐｙｒｏｃ
ｈｌｏｒｅ ｔｏ ｐｅｒｏｖｓｋｉｔｅ ｐｈａｓｅ
ｔｒａｎｓｆｏｒｍａｔｉｏｎ ｉｎ ｓｏｌ−ｇｅ
ｌ ｄｅｒｉｖｅｄ ｌｅａｄ−ｚｉｒｃｏｎａｔｅ−
ｔｉｔａｎａｔｅｔｈｉｎ ｆｉｌｍｓ」，Ａｐｐｌ．
Ｐｈｙｓ，Ｌｅｔｔ，Ｖｏｌ．６０，Ｎｏ．１２、２３
ｍａｒｃｈ １９９２、Ｐ．１４３０−１４３２ （２）Ｋ．ＳＲＥＥＮＩＶＡＳ ｅｔ ａｌ．，「ＰＲ
ＯＰＥＲＴＩＥＳ ＯＦＤ．Ｃ．ＭＡＧＮＥＴＲＯＮ−
ＳＰＵＴＴＥＲＥＤ ＬＥＡＤ ＺＩＲＣＯＮＡＴＥ
ＴＩＴＡＮＡＴＥ ＴＨＩＮ ＦＩＬＭＳ」 Ｔｈｉｎ
ＳｏｌｉｄＦｉｌｍｓ，１７２（１９８９）Ｐ．２５
１−２６７」に開示されるようなものがあった。2. Description of the Related Art Conventionally, as a technique in such a field,
For example, (1) “CK Kwok et al.“ Pyroc
holo to perovskite phase
transformation in sol-ge
l derived lead-zirconate-
titanate thin films ", Appl.
Phys, Lett, Vol. 60, No. 12, 23
march 1992, P.M. 1430-1432 (2) K. SREENIVAS et al. , "PR
OPERIES OFD. C. MAGNETRON-
SPUTTERED LEAD ZIRCONATE
TITANATE THIN FILMS "Thin
Solid Films, 172 (1989) P. 25
1-267 ".
【０００３】上記（１）の文献によれば、ゾルゲル法を
用いたＰＺＴ（Ｌｅａｄ Ｚｉｒｏｎａｔｅ Ｔｉｔａ
ｎａｔｅ）薄膜の形成において、ＰＺＴのゾル液を塗布
後、空気中で６５０℃で５〜１５分間アニールを行うよ
うにしている。また、上記（２）の文献によれば、ＰＺ
ＴやＰＬＺＴ（Ｌｅａｄ Ｌａｎｔｈａｎｕｍ Ｚｉｒ
ｏｎａｔｅ−Ｔｉｔａｎａｔｅ）等の強誘電体材料を薄
膜として形成する場合には、例えば、２００℃程度の成
膜温度で、反応性スパッタ法により、誘電率の低い薄膜
を形成した後、熱処理を施すことにより、再結晶化さ
せ、誘電率の高い薄膜にする方法が用いられている。According to the above-mentioned document (1), PZT (Lead Zironate Tita) using the sol-gel method is used.
In the formation of a thin film, the PZT sol solution is applied and then annealed in air at 650 ° C. for 5 to 15 minutes. Further, according to the above-mentioned document (2), PZ
T and PLZT (Lead Lanthanum Zir)
When a ferroelectric material such as onate-titanate) is formed as a thin film, for example, a thin film having a low dielectric constant is formed by reactive sputtering at a film forming temperature of about 200 ° C., and then heat treatment is performed. , A method of recrystallizing it into a thin film having a high dielectric constant is used.
【０００４】ここでは、反応性スパッタ法により、ＰＺ
Ｔ薄膜を形成する。条件としては、Ｏ2 プラズマ雰囲気
で、複合金属ターゲットを用い、形成温度２００℃で膜
を形成した後、熱処理温度５５０℃で１０〜２０時間熱
処理を施す。Here, PZ is performed by the reactive sputtering method.
A T thin film is formed. As conditions, a composite metal target is used in an O 2 plasma atmosphere, a film is formed at a formation temperature of 200 ° C., and then heat treatment is performed at a heat treatment temperature of 550 ° C. for 10 to 20 hours.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記の
方法によりＰＺＴ膜を形成し、結晶化アニールを施した
後に、ホトリソグラフィ及びエッチングによりパターニ
ングを行う場合には、ＰＺＴ膜表面が結晶化アニールの
際に、表面荒れやクラックを発生するために、精度良く
加工することが困難となるという問題点がある。However, when the PZT film is formed by the above method and subjected to crystallization annealing and then patterned by photolithography and etching, the surface of the PZT film is subjected to crystallization annealing. In addition, there is a problem in that it is difficult to perform processing with high precision because surface roughness and cracks occur.
【０００６】特に、ＰＺＴ膜は従来の絶縁膜と比べ、屈
折率が３に近く、この表面荒れやクラックの発生は大き
な影響を及ぼす。本発明は、以上述べたＰＺＴの結晶化
アニールによる表面形状の荒れや、クラックがパターニ
ングに与える影響を除去するために、ＰＺＴの結晶化ア
ニール前にパターニングを施すようにした半導体素子の
電荷蓄積部の誘電体絶縁膜の形成方法を提供することを
目的とする。In particular, the PZT film has a refractive index close to 3 as compared with the conventional insulating film, and the surface roughness and cracks have a great influence. The present invention relates to a charge storage portion of a semiconductor device in which patterning is performed before crystallization annealing of PZT in order to remove the influence of surface roughness and cracks on patterning due to crystallization annealing of PZT described above. It is an object of the present invention to provide a method for forming the dielectric insulating film.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体素子の電荷蓄積部の誘電体絶縁膜
の形成方法において、基板上に電荷蓄積部の下部電極を
形成する工程と、該下部電極上にＰＺＴやＰＬＺＴのゾ
ル液塗布後、１２０℃〜１５０℃の熱処理を施しＰＺＴ
やＰＬＺＴのアモルファス層を形成する工程と、ホトリ
ソ・エッチングにより前記アモルファス層のパターニン
グを行う工程と、酸素雰囲気中での熱処理により前記ア
モルファス層の結晶化を行い、誘電体絶縁膜を形成する
工程とを施すようにしたものである。In order to achieve the above object, the present invention provides a method of forming a dielectric insulating film of a charge storage portion of a semiconductor device, which comprises forming a lower electrode of the charge storage portion on a substrate. After applying the sol liquid of PZT or PLZT on the lower electrode, heat treatment at 120 ° C. to 150 ° C. is applied to PZT.
A step of forming an amorphous layer of PLZT or PLZT, a step of patterning the amorphous layer by photolitho etching, and a step of crystallizing the amorphous layer by heat treatment in an oxygen atmosphere to form a dielectric insulating film. Is to be applied.
【０００８】また、半導体素子の電荷蓄積部の誘電体絶
縁膜の形成方法において、基板上に電荷蓄積部の下部電
極を形成する工程と、該下部電極上に反応性スパッタ法
により室温〜４００℃でＰＺＴやＰＬＺＴ膜を形成する
工程と、ホトリソ・エッチングにより前記ＰＺＴやＰＬ
ＺＴ膜のパターニングを行う工程と、酸素雰囲気中での
熱処理により前記ＰＺＴやＰＬＺＴ膜の結晶化を行い、
誘電体絶縁膜を形成する工程とを施すようにしたもので
ある。Further, in the method of forming the dielectric insulating film of the charge storage portion of the semiconductor element, the step of forming the lower electrode of the charge storage portion on the substrate and the room temperature to 400 ° C. on the lower electrode by the reactive sputtering method. Process of forming a PZT or PLZT film by using a PZT or PLZT film
The step of patterning the ZT film and the crystallization of the PZT or PLZT film by heat treatment in an oxygen atmosphere,
And a step of forming a dielectric insulating film.
【０００９】[0009]
【作用】本発明によれば、半導体素子の電荷蓄積部の誘
電体膜として、ＰＺＴ又はＰＬＺＴ膜をゾルゲル法によ
り形成する場合に、基板表面にＰＺＴ又はＰＬＺＴのゾ
ル液を塗布し、その後、１２０℃〜１５０℃で熱処理す
ることにより、ＰＺＴ又はＰＬＺＴをアモルファス状態
にし、その後、ホトリソ・エッチングにより微細加工を
行った後、レジスト剤を除去して６００℃〜７００℃で
熱処理することにより、誘電率の高いＰＺＴ又はＰＬＺ
Ｔの結晶とするようにしたものである。According to the present invention, when a PZT or PLZT film is formed by the sol-gel method as the dielectric film of the charge storage portion of the semiconductor element, the sol liquid of PZT or PLZT is applied to the surface of the substrate, and then 120 The PZT or PLZT is made into an amorphous state by heat treatment at ℃ to 150 ℃, after which fine processing is performed by photolitho etching, the resist agent is removed, and heat treatment is performed at 600 ℃ to 700 ℃. High PZT or PLZ
It is a crystal of T.
【００１０】また、反応性スパッタ法により、ＰＺＴ又
はＰＬＺＴ膜を形成した後、ホトリソ・エッチングによ
り微細加工を行い、その後、レジスト剤を除去して６０
０℃〜７００℃で熱処理することにより、誘電率の高い
ＰＺＴ又はＰＬＺＴの結晶とするようにしたものであ
る。このように、ＰＺＴ又はＰＬＺＴの結晶化アニール
を、微細加工後に行うようにしたので、アニールによる
誘電体絶縁膜の表面荒れや、クラックによる微細加工へ
の影響を低減することができる。Further, after the PZT or PLZT film is formed by the reactive sputtering method, fine processing is performed by photolitho etching, and then the resist agent is removed to remove 60
By heat treatment at 0 ° C. to 700 ° C., a crystal of PZT or PLZT having a high dielectric constant is obtained. As described above, since the crystallization annealing of PZT or PLZT is performed after the fine processing, it is possible to reduce the surface roughness of the dielectric insulating film due to the annealing and the influence of the cracks on the fine processing.
【００１１】[0011]
【実施例】以下、本発明の実施例について図を用いて説
明する。図１は本発明の第１実施例を示す半導体素子の
電荷蓄積部の誘電体絶縁膜の形成工程断面図である。こ
の実施例では、ＤＲＡＭの電荷蓄積部の製造に適用した
場合について説明する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a process of forming a dielectric insulating film in a charge storage portion of a semiconductor device according to the first embodiment of the present invention. In this embodiment, a case where the present invention is applied to manufacture of a charge storage portion of a DRAM will be described.
【００１２】まず、図１（ａ）に示すように、Ｓｉ基板
１上にＣＶＤ法により、ＳｉＯ2 層２を形成する。次
に、ホトリソ・エッチングにより、ＳｉＯ2 層２を、図
１（ｂ）に示すような形状に形成し、電荷蓄積部の下部
電極３を形成する。次いで、図１（ｃ）に示すように、
ゾルゲル法により、ＳｉＯ2 層２及び下部電極３上に、
ＰＺＴ又はＰＬＺＴのゾル液を塗布し、その後、１２０
℃〜１５０℃の熱処理を施すことにより、平坦性に優れ
たＰＺＴ又はＰＬＺＴのアモルファス層４Ａを形成す
る。First, as shown in FIG. 1A, a SiO 2 layer 2 is formed on a Si substrate 1 by a CVD method. Next, the SiO 2 layer 2 is formed into a shape as shown in FIG. 1B by photolithography and etching, and the lower electrode 3 of the charge storage portion is formed. Then, as shown in FIG.
By the sol-gel method, on the SiO 2 layer 2 and the lower electrode 3,
PZT or PLZT sol solution is applied, and then 120
By performing a heat treatment at a temperature of 150 ° C. to 150 ° C., an amorphous layer 4A of PZT or PLZT having excellent flatness is formed.
【００１３】次に、図１（ｄ）に示すように、ＰＺＴ又
はＰＬＺＴのアモルファス層４Ａ上にホトレジスト５を
形成する。次に、図１（ｅ）に示すように、ホトレジス
ト５をマスクとして、ホトリソ・エッチングにより、Ｐ
ＺＴ又はＰＬＺＴのアモルファス層４Ａをエッチングす
ることによりパターニングする。Next, as shown in FIG. 1D, a photoresist 5 is formed on the amorphous layer 4A of PZT or PLZT. Next, as shown in FIG. 1E, the photoresist 5 is used as a mask to perform P etching by photolithography and etching.
The amorphous layer 4A of ZT or PLZT is patterned by etching.
【００１４】次に、図１（ｆ）に示すように、オゾンア
ッシャー等により、ホトレジスト５を取り除き、誘電体
絶縁膜としてのＰＺＴ又はＰＬＺＴのアモルファス層４
を得る。以上の工程の後に、ＰＺＴ又はＰＬＺＴの誘電
率を高くするために、酸素雰囲気中で、６００℃〜７０
０℃の熱処理（アニール）を施す。Next, as shown in FIG. 1 (f), the photoresist 5 is removed by ozone asher or the like, and the PZT or PLZT amorphous layer 4 as a dielectric insulating film is removed.
To get After the above steps, in order to increase the dielectric constant of PZT or PLZT, in an oxygen atmosphere, 600 ° C. to 70 ° C.
Heat treatment (annealing) at 0 ° C. is performed.
【００１５】次に、図１（ｇ）に示すように、ＰＺＴ又
はＰＬＺＴのアモルファス層４と面一になるようにＳｉ
Ｏ2 層６を形成し、それらの上に上部電極７を形成す
る。次に、本発明の第２実施例について説明する。図２
は本発明の第２実施例を示す半導体素子の電荷蓄積部の
誘電体絶縁膜の形成工程断面図である。Next, as shown in FIG. 1 (g), Si is made to be flush with the amorphous layer 4 of PZT or PLZT.
The O 2 layer 6 is formed, and the upper electrode 7 is formed thereon. Next, a second embodiment of the present invention will be described. Figure 2
FIG. 6A is a sectional view showing a step of forming a dielectric insulating film in the charge storage portion of the semiconductor device according to the second embodiment of the present invention.
【００１６】まず、図２（ａ）に示すように、Ｓｉ基板
１１上にＣＶＤ法により、ＳｉＯ2層１２を形成する。
次に、ホトリソ・エッチングにより、ＳｉＯ2 層１２を
図２（ｂ）に示すような形状に形成し、電荷蓄積部の下
部電極１３を形成する。次いで、図２（ｃ）に示すよう
に、反応性スパッタ法により、ＳｉＯ2 層１２及び下部
電極１３上に、ＰＺＴ又はＰＬＺＴ膜１４Ａ（誘電率の
低い結晶膜）を形成する。First, as shown in FIG. 2A, the SiO 2 layer 12 is formed on the Si substrate 11 by the CVD method.
Next, the SiO 2 layer 12 is formed into a shape as shown in FIG. 2B by photolithography and etching, and the lower electrode 13 of the charge storage portion is formed. Next, as shown in FIG. 2C, a PZT or PLZT film 14A (crystal film having a low dielectric constant) is formed on the SiO 2 layer 12 and the lower electrode 13 by the reactive sputtering method.
【００１７】ここで、反応性スパッタの条件としては、
例えば、Ａr ＋Ｏ2 又はＯ2 プラズマ、焼結体ターゲッ
ト又は複合金属ターゲットを用い、成膜温度は室温〜４
００℃、成膜圧力は５ｍｔｏｒｒ〜１００ｍｔｏｒｒ、
ＲＦ電力は１５０〜５００Ｗとする。この状態で、誘電
率の低い結晶膜が得られる。次いで、図２（ｄ）に示す
ように、ＰＺＴ又はＰＬＺＴ膜１４Ａ上にホトレジスト
１５を形成する。Here, as the conditions of the reactive sputtering,
For example, Ar + O 2 or O 2 plasma, a sintered body target or a composite metal target is used, and the film formation temperature is from room temperature to 4
00 ° C., the film forming pressure is 5 mtorr to 100 mtorr,
RF power is 150 to 500 W. In this state, a crystal film having a low dielectric constant can be obtained. Next, as shown in FIG. 2D, a photoresist 15 is formed on the PZT or PLZT film 14A.
【００１８】次に、図２（ｅ）に示すように、ホトレジ
スト１５をマスクとして、ホトリソ・エッチングによ
り、ＰＺＴ又はＰＬＺＴ膜１４Ａをエッチングする。次
いで、図２（ｆ）に示すように、オゾンアッシャー等に
より、ホトレジスト１５を取り除き、誘電体絶縁膜とし
てのＰＺＴ又はＰＬＺＴ膜１４を得る。以上の工程の後
に、ＰＺＴ又はＰＬＺＴの誘電率を高くするために、酸
素雰囲気中で６００℃〜７００℃の熱処理（アニール）
を施す。Next, as shown in FIG. 2E, the PZT or PLZT film 14A is etched by photolithography etching using the photoresist 15 as a mask. Then, as shown in FIG. 2F, the photoresist 15 is removed by an ozone asher or the like to obtain a PZT or PLZT film 14 as a dielectric insulating film. After the above steps, heat treatment (annealing) at 600 ° C. to 700 ° C. in an oxygen atmosphere in order to increase the dielectric constant of PZT or PLZT.
Give.
【００１９】次に、図２（ｇ）に示すように、ＳｉＯ2
層１６をＰＺＴ又はＰＬＺＴ膜１４と面一になるように
形成し、それらの上に上部電極１７を形成する。なお、
本発明は上記実施例に限定されるものではなく、本発明
の趣旨に基づき種々の変形が可能であり、それらを本発
明の範囲から排除するものではない。Next, as shown in FIG. 2 (g), SiO 2
The layer 16 is formed so as to be flush with the PZT or PLZT film 14, and the upper electrode 17 is formed thereon. In addition,
The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.
【００２０】[0020]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、ＰＺＴ又はＰＬＺＴの結晶化アニールを、微細
加工後に行うようにしたので、アニールによる誘電体絶
縁膜の表面荒れや、クラックによる微細加工への影響を
低減することができる。更に、この効果に加えて、従来
の方法で熱処理工程で薄膜に生じる応力を、前記方法に
より低減する効果も期待でき、熱処理工程で形成される
表面荒れやクラック等を低減することができる。As described above in detail, according to the present invention, the crystallization annealing of PZT or PLZT is performed after the fine processing, so that the surface of the dielectric insulating film is not roughened or cracked by the annealing. It is possible to reduce the influence on the fine processing due to. In addition to this effect, the effect of reducing the stress generated in the thin film in the heat treatment step by the conventional method can be expected, and surface roughness and cracks formed in the heat treatment step can be reduced.
【図１】本発明の第１実施例を示す半導体素子の電荷蓄
積部の誘電体絶縁膜の形成工程断面図である。FIG. 1 is a cross-sectional view of a process of forming a dielectric insulating film of a charge storage portion of a semiconductor device showing a first embodiment of the present invention.
【図２】本発明の第２実施例を示す半導体素子の電荷蓄
積部の誘電体絶縁膜の形成工程断面図である。FIG. 2 is a sectional view of a step of forming a dielectric insulating film in a charge storage portion of a semiconductor device showing a second embodiment of the present invention.
１，１１ Ｓｉ基板 ２，６，１２，１６ ＳｉＯ2 層 ３，１３ 下部電極 ４，４Ａ ＰＺＴ又はＰＬＺＴ膜（アモルファス層） ５，１５ ホトレジスト ７，１７ 上部電極 １４，１４Ａ ＰＺＴ又はＰＬＺＴ膜（誘電率の低い
結晶膜）1,11 Si substrate 2,6,12,16 SiO 2 layer 3,13 Lower electrode 4,4A PZT or PLZT film (amorphous layer) 5,15 Photoresist 7,17 Upper electrode 14,14A PZT or PLZT film (dielectric constant) Low crystalline film)
Claims (3)
成する工程と、 （ｂ）該下部電極上にＰＺＴやＰＬＺＴのゾル液塗布
後、１２０℃〜１５０℃の熱処理を施しＰＺＴやＰＬＺ
Ｔのアモルファス層を形成する工程と、 （ｃ）ホトリソ・エッチングにより前記アモルファス層
のパターニングを行う工程と、 （ｄ）酸素雰囲気中での熱処理により前記アモルファス
層の結晶化を行い、誘電体絶縁膜を形成する工程とを施
すことを特徴とする半導体素子の電荷蓄積部の誘電体絶
縁膜の形成方法。1. A step of (a) forming a lower electrode of a charge storage portion on a substrate, and (b) a PZT or PLZT sol solution applied on the lower electrode, followed by heat treatment at 120 ° C. to 150 ° C. for PZT. And PLZ
A step of forming an amorphous layer of T; (c) a step of patterning the amorphous layer by photolithography etching; and (d) a crystallization of the amorphous layer by a heat treatment in an oxygen atmosphere to obtain a dielectric insulating film. And a step of forming a dielectric insulating film of a charge storage portion of a semiconductor element.
成する工程と、 （ｂ）該下部電極上に反応性スパッタ法により室温〜４
００℃でＰＺＴやＰＬＺＴ膜を形成する工程と、 （ｃ）ホトリソ・エッチングにより前記ＰＺＴやＰＬＺ
Ｔ膜のパターニングを行う工程と、 （ｄ）酸素雰囲気中での熱処理により前記ＰＺＴやＰＬ
ＺＴ膜の結晶化を行い、誘電体絶縁膜を形成する工程と
を施すことを特徴とする半導体素子の電荷蓄積部の誘電
体絶縁膜の形成方法。2. A step of (a) forming a lower electrode of a charge storage portion on a substrate, and (b) room temperature to 4 by reactive sputtering on the lower electrode.
A step of forming a PZT or PLZT film at 00 ° C., and (c) the PZT or PLZ by photolithographic etching.
The step of patterning the T film, and (d) the heat treatment in an oxygen atmosphere, the PZT or PL
A method of forming a dielectric insulating film in a charge storage portion of a semiconductor element, which comprises performing a step of crystallizing a ZT film to form a dielectric insulating film.
℃〜７００℃で行うことを特徴とする請求項１又は２記
載の半導体素子の電荷蓄積部の誘電体絶縁膜の形成方
法。3. The heat treatment in the step (d) is 600
The method for forming a dielectric insulating film in a charge storage portion of a semiconductor device according to claim 1 or 2, wherein the method is performed at a temperature of 700C to 700C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5137579A JPH06350050A (en) | 1993-06-08 | 1993-06-08 | Method for forming dielectric insulating film film in charge storage part of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5137579A JPH06350050A (en) | 1993-06-08 | 1993-06-08 | Method for forming dielectric insulating film film in charge storage part of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06350050A true JPH06350050A (en) | 1994-12-22 |
Family
ID=15202022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5137579A Withdrawn JPH06350050A (en) | 1993-06-08 | 1993-06-08 | Method for forming dielectric insulating film film in charge storage part of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06350050A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000028584A1 (en) * | 1998-11-06 | 2000-05-18 | Infineon Technologies Ag | Method for producing a structured layer containing metal oxide |
| KR100268415B1 (en) * | 1997-10-01 | 2000-10-16 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| US6288822B2 (en) | 1997-10-29 | 2001-09-11 | Teloptics Corporation | Discrete element light modulating microstructure devices |
| US6486996B1 (en) | 1998-10-27 | 2002-11-26 | Teloptics Corporations | Discrete element light modulating microstructure devices |
| US6586348B2 (en) | 1998-11-06 | 2003-07-01 | Infineon Technologies Ag | Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation anneal but while still amorphous and then thermally annealing to crystallize |
-
1993
- 1993-06-08 JP JP5137579A patent/JPH06350050A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100268415B1 (en) * | 1997-10-01 | 2000-10-16 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| US6288822B2 (en) | 1997-10-29 | 2001-09-11 | Teloptics Corporation | Discrete element light modulating microstructure devices |
| US6297899B1 (en) | 1997-10-29 | 2001-10-02 | Teloptics Corporation | Discrete element light modulating microstructure devices |
| US6310712B1 (en) * | 1997-10-29 | 2001-10-30 | Teloptics Corporation | Discrete element light modulating microstructure devices |
| US6381060B1 (en) | 1997-10-29 | 2002-04-30 | Teloptics Corporation | Total internal reflection light modulating microstructure devices |
| US6486996B1 (en) | 1998-10-27 | 2002-11-26 | Teloptics Corporations | Discrete element light modulating microstructure devices |
| WO2000028584A1 (en) * | 1998-11-06 | 2000-05-18 | Infineon Technologies Ag | Method for producing a structured layer containing metal oxide |
| US6586348B2 (en) | 1998-11-06 | 2003-07-01 | Infineon Technologies Ag | Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation anneal but while still amorphous and then thermally annealing to crystallize |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3122579B2 (en) | Pt film etching method | |
| US5464500A (en) | Method for taper etching metal | |
| US20030077843A1 (en) | Method of etching conductive layers for capacitor and semiconductor device fabrication | |
| US6750067B2 (en) | Microelectronic piezoelectric structure and method of forming the same | |
| US5453347A (en) | Method for constructing ferroelectric capacitors on integrated circuit substrates | |
| JPH06350050A (en) | Method for forming dielectric insulating film film in charge storage part of semiconductor | |
| US6482538B2 (en) | Microelectronic piezoelectric structure and method of forming the same | |
| JPH05335216A (en) | X-ray mask and its manufacture | |
| JP3969178B2 (en) | Electronic component and manufacturing method thereof | |
| JP3142457B2 (en) | Method of manufacturing ferroelectric thin film capacitor | |
| JP3348564B2 (en) | Method for manufacturing dielectric capacitor | |
| JP3169654B2 (en) | Method for manufacturing semiconductor device | |
| JP3216173B2 (en) | Method of manufacturing thin film transistor circuit | |
| JPH04293280A (en) | Manufacture of ceramic thin film element | |
| JP2007036206A (en) | Manufacturing method of ferroelectric film structure | |
| JPH03104127A (en) | Formation of fine pattern | |
| JPH06291253A (en) | Formation of dielectric film of electric charge storage section of semiconductor element | |
| JP2691175B2 (en) | Patterned oxide superconducting film formation method | |
| JPH07122752A (en) | Manufacture of thin film transistor | |
| JPH0589662A (en) | Manufacture of semiconductor device | |
| JPH0485823A (en) | Manufacture of semiconductor device | |
| JPH11204364A (en) | Manufacture of dielectric thin film capacitor | |
| JPH06107489A (en) | Production of crystalline thin film | |
| JPH0366127A (en) | Manufacture of semiconductor device | |
| JPS6080227A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000905 |