JPH0589662A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0589662A
JPH0589662A JP24585891A JP24585891A JPH0589662A JP H0589662 A JPH0589662 A JP H0589662A JP 24585891 A JP24585891 A JP 24585891A JP 24585891 A JP24585891 A JP 24585891A JP H0589662 A JPH0589662 A JP H0589662A
Authority
JP
Japan
Prior art keywords
etching
etched
pattern
mask
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24585891A
Other languages
Japanese (ja)
Inventor
Kazuhiro Takenaka
計廣 竹中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP24585891A priority Critical patent/JPH0589662A/en
Publication of JPH0589662A publication Critical patent/JPH0589662A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent Pt from adhering again and to enhance the quality of a Pt pattern by a method wherein a first thin film such as Pt is etched by making use of a second conductive film composed of Ti or the like as a mask. CONSTITUTION:An insulating film 102, a ferroelectric-capacitor Pt electrode 103 and a PZT ferroelectric 104 are formed on an Si substrate 101 by a prescribed method. Then, a ferroelectric-capacitor Pt electrode 105 and Ti 106 are laminated; the Ti 106 is etched by making use of a resist 107 as a mask; a prescribed Ti pattern 108 is formed. In addition, by making use of it as a mask, the Pt layer 105 is etched; a Pt pattern 109 is obtained. When Ti whose etch rate is slower than that of Pt is used as a mask and an etched operation is executed, it is possible to prevent the Pt from adhering again and to from the Pt pattern which is good.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、Ptなどを用いた半導
体装置、特にPtを電極とした強誘電体キャパシタが集
積された半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using Pt or the like, and more particularly to a method of manufacturing a semiconductor device in which a ferroelectric capacitor having Pt as an electrode is integrated.

【0002】[0002]

【従来の技術】従来のPt電極の形成方法としては、P
tを例えばスパッタ法などで形成した後、レジストでP
t上に所定のパターンを形成した後、イオンビームエッ
チングや、スパッタエッチにより、Ptのパターンを形
成していた。
2. Description of the Related Art A conventional method for forming a Pt electrode is P
After t is formed by, for example, a sputtering method, P is formed with a resist.
After forming a predetermined pattern on t, a Pt pattern was formed by ion beam etching or sputter etching.

【0003】[0003]

【発明が解決しようとする課題】しかし、イオンビーム
エッチングやスパッタエッチなどのエッチング方法は、
反応性エッチングではないため、エッチングされたPt
がレジストの側面に付着しレジストの剥離後に、突起上
にPtが残ってしまうという問題がある。そこで、例え
ば、レジストを200度ぐらいに加熱することにより、
レジストをフローさせてテーパー化させ、レジストの側
面に付着しないようにしたりする方法が取られている。
しかし、この場合には、テーパー化させるため、微細化
には向かないという課題が残る。反応性エッチングを用
いれば再付着の問題はないが、Pt等の金属は蒸気圧が
低いため、反応性のガスがないため、ここで説明したよ
うにイオンビームエッチングやスパッタエッチなどのエ
ッチング方法が用いられているのが普通である。
However, the etching methods such as ion beam etching and sputter etching are
Etched Pt because it is not reactive etching
However, there is a problem that Pt remains on the protrusions after being attached to the side surface of the resist and peeling off the resist. Therefore, for example, by heating the resist to about 200 degrees,
A method is used in which the resist is flowed to be tapered so as not to adhere to the side surface of the resist.
However, in this case, since the taper is made, there is a problem that it is not suitable for miniaturization. If reactive etching is used, there is no problem of redeposition, but since metals such as Pt have a low vapor pressure and there is no reactive gas, etching methods such as ion beam etching and sputter etching are used as described here. It is usually used.

【0004】[0004]

【課題を解決するための手段】本発明は、Ptなどを用
いた半導体装置、特にPtを電極とした強誘電体キャパ
シタが集積された半導体装置の製造方法において、P
t、またはPdを主成分とする第1薄膜と、イオンビー
ムエッチングにおいてエッチング速度がPtよりも遅い
Tiなどからなる第2導電膜を積層し、第2導電膜を従
来技術である反応性エッチングによりエッチングし、エ
ッチングされた、第2導電膜をマスクとしてPtなどの
第1薄膜をエッチングするような工程としたことを特徴
とする。
The present invention relates to a method of manufacturing a semiconductor device using Pt or the like, particularly a semiconductor device in which a ferroelectric capacitor having Pt as an electrode is integrated.
A first thin film containing t or Pd as a main component and a second conductive film made of Ti or the like having an etching rate lower than Pt in ion beam etching are stacked, and the second conductive film is formed by reactive etching which is a conventional technique. It is characterized in that the etching is performed and the first thin film of Pt or the like is etched using the etched second conductive film as a mask.

【0005】[0005]

【作用】本発明の製造方法によると、第2導電膜である
Tiなどは、反応性エッチングが可能のため、再付着な
どの問題がなくエッチング、パターンの形成が出来る。
そして、その後このTiをマスクにしてその下に形成さ
れたPtをエッチングするが、この際にはTiのエッチ
ングレートはPtに比較して約1/4のため、Ptの厚
みの約1/4のTiによりPtをエッチングできる。ま
た、Pt、Tiともに導電膜であるため、かりにTiの
側面にPtが再付着しても何等問題とはならない。
According to the manufacturing method of the present invention, since the second conductive film such as Ti can be reactively etched, etching and pattern formation can be performed without problems such as redeposition.
Then, using this Ti as a mask, Pt formed below is etched. At this time, since the etching rate of Ti is about 1/4 that of Pt, it is about 1/4 of the thickness of Pt. Pt can be etched by the Ti. Further, since both Pt and Ti are conductive films, even if Pt is reattached to the side surface of Ti, there is no problem.

【0006】[0006]

【実施例】以下、本発明の詳細を実施例を基に説明す
る。ここでは、例として強誘電体を用いたキャパシタの
電極としてPtを用いた場合に本発明を適用した場合に
ついて説明する。
EXAMPLES The details of the present invention will be described below with reference to examples. Here, a case where the present invention is applied to the case where Pt is used as an electrode of a capacitor using a ferroelectric substance will be described as an example.

【0007】図1に、本発明の製造方法の工程断面図を
示す。
FIG. 1 is a process sectional view of the manufacturing method of the present invention.

【0008】図1(a)で、101は基板となる例えば
Siである。102はSi上に形成された絶縁膜で、例
えば、熱酸化したSiO2を用いる。103は強誘電体
キャパシタの一方の電極となるたとえばPtで、約30
00Aスパッタ法により形成する。このPtは例えば従
来技術であるイオンビームエッチングなどで所定のパタ
ーンに形成する。104は強誘電体であるPZTで組成
として例えば、Zr:Ti=52:48のPZTを約5
000Å形成する。このPZTのエッチングとしては例
えば、HF:NH4F=1:4のエッチング液を用い
る。105が強誘電体キャパシタの他方の電極となるP
tであり、約3000Åの厚さのPtをスパッタ法によ
り形成する。そして、Ptの上に106のTiを約15
00Å同じくスパッタ法により形成する。
In FIG. 1A, 101 is a substrate, for example, Si. Reference numeral 102 denotes an insulating film formed on Si, for example, thermally oxidized SiO 2 is used. 103 is one electrode of the ferroelectric capacitor, for example, Pt, and is about 30
00A sputtering method. This Pt is formed into a predetermined pattern by, for example, ion beam etching which is a conventional technique. 104 is a ferroelectric PZT, for example, about 5 PZT of Zr: Ti = 52: 48.
000Å form. For etching the PZT, for example, an etching solution of HF: NH4F = 1: 4 is used. 105 serves as the other electrode of the ferroelectric capacitor P
t, and Pt having a thickness of about 3000 Å is formed by the sputtering method. Then, about 106 of Ti on Pt
00Å Similarly, it is formed by the sputtering method.

【0009】図1(b)で、次にレジスト107を所定
のパターンに形成する。
Next, in FIG. 1B, a resist 107 is formed in a predetermined pattern.

【0010】図1(c)で、107のレジストをマスク
として106のTiを、NH4OH、H2O2、H2O
の混合液や、CF4を含むガスによりエッチングする。
その後107のレジストを除去し、108のTiパター
ンを得る。
In FIG. 1 (c), Ti of 106 is added to NH4OH, H2O2, H2O using the resist of 107 as a mask.
Etching is performed by using the mixed liquid of or the gas containing CF4.
After that, the resist 107 is removed to obtain a Ti pattern 108.

【0011】図1(d)で、次に108のTiパターン
をマスクにして、イオンビームエッチングにより105
のPtをエッチングして、109のPtパターンを得
る。Tiのエッチング速度はPtのエッチング速度と比
較して約1/4であるため、3000ÅのPtをエッチ
ングする間にTiは約750Åエッチングされ、約75
0Åが残る。この際、Ptの再付着物が110のように
Ti、108の即壁にかりに残っても、金属同士である
ため、レジストの即壁に残った場合のように突起上には
ならない。
In FIG. 1 (d), the Ti pattern 108 is used as a mask to perform 105 by ion beam etching.
Of Pt is etched to obtain a Pt pattern of 109. Since the etching rate of Ti is about 1/4 of the etching rate of Pt, Ti is etched by about 750Å while etching Pt of 3000Å,
0Å remains. At this time, even if the reattachment of Pt remains on the immediate wall of Ti and 108 like 110, since it is a metal, it does not become on the protrusion as when it remains on the immediate wall of the resist.

【0012】図1の実施例においては、第2導電膜とし
てTiを用いた場合について説明したが、TiN、Ti
W、MoSiなどの導電膜を用いても良いことは言うま
でもない。
In the embodiment of FIG. 1, the case where Ti is used as the second conductive film has been described, but TiN, Ti
It goes without saying that a conductive film such as W or MoSi may be used.

【0013】また、図1の説明においては強誘電体の電
極にPtを使用した場合について説明したが、Pt電極
を用いたその他の半導体装置、例えばバイポーラトラン
ジスタ等に本発明が適用できることも言うまでもない。
In the description of FIG. 1, the case where Pt is used for the ferroelectric electrode has been described, but it goes without saying that the present invention can be applied to other semiconductor devices using the Pt electrode, such as bipolar transistors. ..

【0014】[0014]

【発明の効果】以上説明してきたように、本発明の製造
方法によれば、Ptなどを用いた半導体装置、特にPt
を電極とした強誘電体キャパシタが集積された半導体装
置の製造方法において、Pt、またはPdを主成分とす
る第1薄膜と、イオンビームエッチングにおいてエッチ
ング速度がPtよりも遅いTiなどからなる第2導電膜
を積層し、第2導電膜を従来技術である反応性エッチン
グによりエッチングし、エッチングされた、第2導電膜
をマスクとしてPtなどの第1薄膜をエッチングするよ
うな工程としたことにより、Ptの再付着が防げ、仮に
再付着が起きたとしても、突起上にPtが残らず、良好
なPtパターンが形成できるという効果がある。
As described above, according to the manufacturing method of the present invention, a semiconductor device using Pt or the like, particularly Pt is used.
In a method of manufacturing a semiconductor device in which a ferroelectric capacitor having an electrode as an electrode is integrated, a second thin film containing Pt or Pd as a main component and Ti having an etching rate lower than Pt in ion beam etching is used. By stacking the conductive films, etching the second conductive film by the conventional reactive etching, and etching the first thin film such as Pt using the etched second conductive film as a mask, There is an effect that Pt reattachment can be prevented, and even if reattachment occurs, Pt does not remain on the protrusions and a good Pt pattern can be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の工程断面図である。FIG. 1 is a process sectional view of an example of the present invention.

【符号の説明】[Explanation of symbols]

101 Si基板 102 SiO2膜 103 電極 104 強誘電体膜 105 Pt膜 106 Ti膜 107 レジスト 108 Tiパターン 109 Ptパターン 101 Si substrate 102 SiO2 film 103 Electrode 104 Ferroelectric film 105 Pt film 106 Ti film 107 Resist 108 Ti pattern 109 Pt pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】Pt、またはPdを主成分とする第1薄膜
を形成する工程と、前記第1薄膜上に主成分がTiから
なる第2導電膜を形成する工程と、前記第2導電膜上
に、所定のパターンをレジストにより形成する工程と、
前記第2導電膜を前記所定のパターンにエッチングする
工程と、前記エッチングされた、第2導電膜をマスクと
して前記第1薄膜をエッチングする工程を含むことを特
徴とする半導体装置の製造方法。
1. A step of forming a first thin film containing Pt or Pd as a main component, a step of forming a second conductive film containing Ti as a main component on the first thin film, and the second conductive film. And a step of forming a predetermined pattern with a resist,
A method of manufacturing a semiconductor device, comprising: a step of etching the second conductive film into the predetermined pattern; and a step of etching the first thin film using the etched second conductive film as a mask.
JP24585891A 1991-09-25 1991-09-25 Manufacture of semiconductor device Pending JPH0589662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24585891A JPH0589662A (en) 1991-09-25 1991-09-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24585891A JPH0589662A (en) 1991-09-25 1991-09-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0589662A true JPH0589662A (en) 1993-04-09

Family

ID=17139882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24585891A Pending JPH0589662A (en) 1991-09-25 1991-09-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0589662A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0786805A2 (en) * 1996-01-26 1997-07-30 Matsushita Electronics Corporation Method of plasma etching a film made of one of a ferroelectric material, high dielectric constant material or platinum
KR19980024743A (en) * 1996-09-20 1998-07-06 가나이 쯔도무 Manufacturing Method of Semiconductor Integrated Circuit Device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0786805A2 (en) * 1996-01-26 1997-07-30 Matsushita Electronics Corporation Method of plasma etching a film made of one of a ferroelectric material, high dielectric constant material or platinum
EP0786805A3 (en) * 1996-01-26 1997-08-20 Matsushita Electronics Corp
US5840200A (en) * 1996-01-26 1998-11-24 Matsushita Electronics Corporation Method of manufacturing semiconductor devices
KR19980024743A (en) * 1996-09-20 1998-07-06 가나이 쯔도무 Manufacturing Method of Semiconductor Integrated Circuit Device
US6057081A (en) * 1996-09-20 2000-05-02 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device
US6497992B1 (en) 1996-09-20 2002-12-24 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device

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