JPH06349948A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid a usual method that power supply wirings are directly connected to a peripheral power supply wiring so as to easily carry out an automatic layout wiring by a method wherein a branch power supply wiring connected to either of a first and a second peripheral main power supply wire is provided inside a large scale circuit block. CONSTITUTION:A branch power supply wiring 34 connected to a peripheral power supply wiring 36 is provided inside a large scale circuit block 35. By this setup, branch power supply wirings 14 and 16 for feeding a GND potential to the large scale circuit block 35 can be connected to the branch power supply wiring 34. In result, the large scale circuit block 35 and the peripheral power supply wiring 36 are restrained from becoming complicated in wiring, so that connection wiring sections can be standardized into rectilinear and simple structures, and an automatic layout wiring operation can be easily carried out. Therefore, a semiconductor integrated circuit device high in performance and function can be developed in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit in which peripheral main power supply wiring is formed so as to surround the periphery of a large scale circuit block.

[0002]

2. Description of the Related Art Conventionally, in order to develop a high-performance and high-performance semiconductor integrated circuit device in a short period of time, a semiconductor integrated circuit in which a large-scale circuit block of a cell base system is mixedly mounted inside a semiconductor integrated circuit device of a gate array system. Circuit devices are known. This semiconductor integrated circuit device has a structure in which a logic circuit portion is mainly composed of a gate array type logic circuit element having a short development period, and a large-scale cell-based type circuit block having a high degree of integration is mounted therein. is doing. Such a semiconductor integrated circuit device has an embedded cell structure.
l Array device (hereinafter referred to as ECA device).

FIG. 2 is a wiring layout diagram of a conventional general ECA device. Referring to FIG. 2, in the conventional ECA device, input / output is performed along the periphery of the chip of the semiconductor integrated circuit device 1.
A peripheral circuit 2 such as an output buffer circuit is arranged.
Cell-based large-scale circuit blocks 3 and 4 are arranged in a predetermined area surrounded by the peripheral circuit 2. A gate array type logic circuit element 11 is also arranged in a region surrounded by the peripheral circuit 2.

Branch line power supply wirings 9 and 10 for supplying the GND potential and the VDD potential are provided to the logic circuit element 11 and the large-scale circuit blocks 3 and 4 so as to traverse the semiconductor integrated circuit device 1 left and right. There is. Branch line power supply wires 9 and 1 so as to intersect with branch line power supply wires 9 and 10.
0 is provided with main power supply wirings 5 and 6 for supplying the potentials of GND and VDD, respectively.

The branch line power supply line 9 and the main line power supply line 5 are connected via a via hole 7 provided in an interlayer insulating film (not shown) interposed therebetween, and the branch line power supply line 10 and the main line power supply are connected. The wiring 6 is connected via a via hole 8.

Signal wiring (not shown) is used for the logic circuit element 1.
1 and the regions outside the large-scale circuit blocks 3 and 4 or the columns of the logic circuit elements 11 are wired with a relatively narrow line width.

The branch power supply wirings 9 and 10, the trunk power supply wirings 5 and 6, and the signal wirings are basically left and right wirings in the first wiring layer, and vertical wirings in the second wiring layer. It is unified throughout. Then, as described above, the interlayer insulating film is interposed between the first wiring layer and the second wiring layer, and the connection between the first wiring layer and the second wiring layer is performed by the interlayer insulating film. It is performed through a via hole provided in.

Here, in order to develop a high-performance and high-performance integrated circuit device in a short period of time, it is general to use an automatic placement and routing program in designing. However, when such an automatic placement and routing program is used in the conventional general ECA device shown in FIG. 2, it is difficult to supply power to the large scale circuit blocks 3 and 4. That is, branch line power supply wirings 9 and 1 for supplying the GND and VDD potentials to the gate array type logic circuit element 11.
0 and the main power supply wirings 5 and 6 are normally arranged at constant intervals. However, the wiring shape of the power supply system and the positions of the terminals of the large-scale circuit blocks 3 and 4 are as follows:
In reality, it is difficult to standardize because it is different from the interval of 10 and the interval of the main power supply wirings 5 and 6. Therefore, in the conventional ECA device, it is difficult to supply power to the large-scale circuit blocks 3 and 4.

Therefore, conventionally, a method has been proposed in which a peripheral power supply wiring having a sufficiently wide width is provided around a large-scale cell-based circuit block. These are, for example, Japanese Patent Laid-Open No.
It is disclosed in Japanese Patent Publication No.-86145.

FIG. 3 is a wiring layout diagram of a semiconductor integrated circuit device having a sufficiently wide peripheral power supply wiring around such a conventionally proposed large-scale circuit block. With reference to FIG. 3, in this conventional proposal example, a large-scale circuit block 3
5, peripheral power supply wiring 37 for supplying VDD potential is arranged so as to surround 5, and further peripheral power supply wiring 3
A peripheral power supply line 36 for supplying a GND potential is arranged so as to surround 7. Main power supply wires 21, 23, 22, and 24 are connected to the peripheral power supply wires 36 and 37, respectively. Further, branch power supply wirings 25 and 27 are connected to the peripheral power supply wiring 36, and branch power supply wirings 26 and 28 are connected to the peripheral power supply wiring 37.

Large-scale circuit block 35 and peripheral power supply wiring 3
GND to the large-scale circuit block 35 so as to connect to 6
Branch line power supply wirings 14, 16 and 19 for supplying a potential are arranged. V is connected to the large-scale circuit block 35 so as to connect the large-scale circuit block 35 and the peripheral power supply wiring 37.
Branch line power supply lines 12, 18, 2 for supplying DD potential
0 is placed.

The branch power supply wiring 19 and the peripheral power supply wiring 36 are connected via a via hole 29, and the branch power supply wiring 20 and the peripheral power supply wiring 37 are connected via a via hole 30. The branch power supply wires 25 and 26 and the peripheral power supply wires 36 and 37 are connected via via holes 31 and 32, respectively. Main line power supply lines 23 and 24 and peripheral power supply lines 36 and 37 are connected via via holes 38 and 39, respectively. Via holes 40 and 41 are provided at the corners of the peripheral power supply wirings 37 and 36, respectively. Further, signal wirings 13, 15 and 17 are connected to the large scale circuit block 35.

[0013]

Conventionally, as shown in FIG. 3, by providing peripheral power supply wirings 36 and 37 having a sufficiently large width around a large-scale circuit block, the peripheral power supply wirings 36, 37 are provided. And branch power supply wiring 25, 2
6, 27, 28 and main power supply wirings 21, 22, 23,
The connection with 24 was made easy.

However, if the positions of the branch line power supply wires 25 to 28 and the main line power supply wires 21 to 24 are arranged at positions different from those shown in FIG. It was

FIG. 4 is a wiring layout diagram for explaining the conventional problems. Referring to FIG. 4, branch line power supply wiring 25-
When the 28 and the main power supply wirings 21 to 24 are connected at the positions shown in FIG. 4, the branch power supply wirings 14 and 16 for supplying the GND potential to the large-scale circuit block 35 are complicated as shown in the portion A. There was a problem that it was necessary to make a proper connection. As a result, there is a problem that the automatic placement and routing cannot be performed easily and the development period becomes long.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of easily performing automatic placement and routing.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device, wherein a large-scale circuit block and a large-scale circuit block are formed so as to surround the large-scale circuit block and supply a first potential to the large-scale circuit block. A first peripheral mains power supply wiring, and a second peripheral mains power supply wiring formed to surround the first peripheral mains power supply wiring at a predetermined distance from the first peripheral mains power supply wiring. It is provided inside the large-scale circuit block and has branch line power supply wirings connected to one of the first and second peripheral trunk power supply wirings.

[0018]

In the semiconductor integrated circuit device according to the first aspect of the present invention, the branch line power supply line connected to one of the first and second peripheral main line power supply lines is provided inside the large-scale circuit block. By connecting a plurality of power supply wirings from the large-scale circuit block to the power supply wirings, it becomes unnecessary to directly connect the plurality of power supply wirings to the peripheral power supply wirings as in the conventional case. As a result, there is no inconvenience that the wiring becomes complicated around the connection between the large-scale circuit block and the peripheral power supply wiring as in the conventional case. As a result, in the semiconductor integrated circuit device, the connection wiring portions are unified into a linear simple structure, and automatic placement and wiring is facilitated.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a wiring layout diagram of an ECA device according to an embodiment of the present invention. Referring to FIG. 1, E of the present embodiment
In the CA device, a branch line power supply wiring 34 connected to the peripheral power supply wiring 36 is provided inside the large-scale circuit block 35.
Thereby, the branch power supply wirings 14 and 16 for supplying the GND potential to the large-scale circuit block 35 can be connected to the branch power supply wiring 34. As a result, unlike the conventional ECA device shown in FIG.
The wiring in the wiring portion between the power supply wiring 36 and the peripheral power supply wiring 36 (the portion B in FIG. 1) does not become complicated. As a result, the connection wiring portion can be unified into a linear simple structure, and automatic placement and wiring can be easily performed. As a result,
It is possible to develop a high-performance and highly-functional semiconductor integrated circuit device in a short time.

The other structures are the same as those of the conventional ECA device shown in FIG. That is, the peripheral power supply wiring 37 for supplying the VDD potential is provided so as to surround the large-scale circuit block 35, and the peripheral power supply wiring 3 is provided.
A peripheral power supply line 36 for supplying a GND potential is provided so as to surround 7. For the surrounding power supply wiring 37, V
Main power supply wirings 22 and 24 for supplying the DD potential
Are connected. Main power supply lines 21 and 23 for supplying a GND potential are connected to the peripheral power supply line 36. In addition, the peripheral power supply wiring 37 includes the branch power supply wiring 2
6 and 28 are connected, and branch power supply wirings 25 and 27 are connected to the peripheral power supply wiring 36. Branch line power supply wirings 12, 18 and 20 for supplying VDD potential to the large-scale circuit block 35 are provided so as to connect the large-scale circuit block 35 and the peripheral power supply wiring 37. In addition, the large-scale circuit block 35 includes the signal wiring 13,
15 and 17 are connected.

Large-scale circuit block 35 and peripheral power supply wiring 3
6 is connected to the large-scale circuit block 35 so that
Branch line power supply wiring 19 for supplying the D potential is provided.

The branch power supply wiring 19 and the peripheral power supply wiring 36 are connected via a via hole 29, and the branch power supply wiring 20 and the peripheral power supply wiring 37 are connected via a via hole 30. The branch line power supply line 25 and the peripheral power supply line 36 are connected via a via hole 31, and the branch line power supply line 26 and the peripheral power supply line 36 are connected via a via hole 32. The branch line power supply wirings 14 and 16 and the branch line power supply wiring 34 are connected via a via hole 33. Vias 38 are provided between the main power supply wiring 23 and the peripheral power supply wiring 36.
The main power supply wiring 24 and the peripheral power supply wiring 37 are connected via a via hole 39.
Also, the via hole 4 is provided at the corner of the peripheral power supply wiring 36.
1 is provided, and a via hole 40 is provided at a corner portion of the peripheral power supply wiring 37.

[0024]

As described above, according to the semiconductor integrated circuit device of the first aspect, the first and second peripheral mains power supply wirings surrounding the large-scale circuit block are provided inside the large-scale circuit block. By connecting the branch power supply wiring to one of the above, the multiple power supply wiring that was conventionally connected to the peripheral power supply wiring from the large-scale circuit block is connected to the branch power supply wiring provided inside the large-scale circuit block. Therefore, the wiring around the connecting portion between the large-scale circuit block and the peripheral power supply wiring does not become complicated unlike the conventional case.
As a result, the automatic wiring arrangement can be easily performed. This makes it possible to develop a high-performance and highly-functional semiconductor integrated circuit device in a short time.

[Brief description of drawings]

FIG. 1 is a wiring layout diagram of an ECA device according to an embodiment of the present invention.

FIG. 2 is a wiring layout diagram of a conventional general ECA device.

FIG. 3 is a wiring layout diagram of a conventional improved ECA device.

FIG. 4 is a wiring layout diagram for explaining problems of the conventional improved ECA device shown in FIG.

[Explanation of symbols]

 14, 16: Branch line power supply wiring 34: Branch line power supply wiring 35: Large-scale circuit block 36: Peripheral power supply wiring 37: Peripheral power supply wiring In each drawing, the same reference numerals indicate the same or corresponding parts.

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[Procedure amendment]

[Submission date] August 20, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Fig. 2]

[Figure 3]

[Figure 1]

[Figure 4]

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Chikako Yamauchi 4-61-5 Higashino, Itami City, Hyogo Prefecture Mitsubishi Electric Engineering Co., Ltd.

Claims (1)

[Claims] 1. A large-scale circuit block, and a first peripheral mains power supply wiring formed to surround the periphery of the large-scale circuit block and for supplying a first potential to the large-scale circuit block, A second peripheral power supply wiring formed to surround the first peripheral main power supply wiring at a predetermined distance from the first peripheral main power supply wiring.
The semiconductor integrated circuit device comprising: a peripheral mains power supply wiring; and a branch power supply wiring provided inside the large-scale circuit block and connected to one of the first and second peripheral mains power supply wirings.