JPH06334974A - Interpolation circuit - Google Patents

Abstract

PURPOSE:To share an interpolation processing part to reduce the circuit scale at the time of interpolating signals of two systems respectively and to reduce the power consumption by the reduction of the circuit scale. CONSTITUTION:A brightness signal and a chrominance signal are supplied to input terminal 200 and 218 respectively, and a selection circuit 204 supplies original brightness and chrominance signals to selection circuits 209 and 252 in time division, and selection circuits 214 to 217 supply brightness and chrominance signals different by delay times to an interpolation circuit 280 in time division. The interpolation circuit 280 supplies interpolation values of the brightness signal and the chrominance signal to selection circuits 209 and 252 in time division, and the selection circuit 209 selectively leads out the brightness signal and inputs it to memories 210 and 213 alternately every line, and the selection circuit 252 selectively leads out the chrominance signal and inputs it to memories 253 and 254 alternately every line. A selection circuit 211 leads out the brightness signal subjected to interpolation processing from memories 210 and 213 alternately, and a selection circuit 256 leads out the chrominance signal subjected to interpolation processing from memories 253 and 254 alternately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolation circuit for calculating inter-sample interpolation values of digital signals of a plurality of systems.

[0002]

2. Description of the Related Art At present, there are NTSC, PAL, SECAM systems and the like as terrestrial broadcasting television systems. In all of these broadcasting systems, the horizontal and vertical ratios (aspect ratios) of the transmitted screen are the same, and the aspect ratio of 4: 3 is adopted. However, in recent years, there has been a demand for wider screens. At the same time that 16: 9 signal sources have appeared, wide-screen televisions having a 16: 9 display section have been released by various companies. However, when trying to display the current 4: 3 video on such a television, the video becomes horizontally long. In this case, the video is compressed 3/4 times in the horizontal direction and displayed to eliminate distortion. ing. Examples of ICs that perform such processing include TDC9103CFP manufactured by Toshiba. In this IC, signals of two systems, such as luminance and color, are time-compressed 3/4 times in units of one horizontal scanning period, and a direct current (DC) component called a side panel is fitted into a region vacated by the compression to produce a non-image part. Is making.

In this type of IC, as described above, signals of two systems such as luminance and color signals are individually time-compressed. FIG. 7 shows an example of a conventional compression circuit. First, the compression processing operation section of the luminance signal which is the first system signal will be described with reference to FIG. 8 and the luminance processing timing chart of FIG. 9 following this figure. A digitized luminance signal is input to the luminance input terminal 300, and the state of this signal is shown in FIGS. 8 and 9 (b).
It shows in (c). In FIG. 8 and FIG. 9B, white circles indicate samples, and as shown in FIG. 8 and FIG. 9C, Y
The description will be made assuming that (0), Y (1), ... In addition, in FIG. 8 and FIG. 9B, times are listed in order to explain the process. Luminance signal input terminal 30
The digital luminance signal supplied from 0 is the D flip-flops 301, 302, 303, 304, 305, 30.
It is supplied to the selection circuit 308 via 6 and 307, and the output of the D flip-flop 307 becomes as shown in (g) of FIGS. 8 and 9. The digital luminance signal supplied from the luminance signal input terminal 300 is also supplied to the selection circuits 313 and 316. The output of the D flip-flop 301 is supplied to the selection circuits 314 and 315. The output of the D flip-flop 301 is shown in FIGS. 8 and 9 (d). The output of the D flip-flop 302 is the selection circuits 314 and 31.
5 is supplied. The output of the D flip-flop 302 is shown in FIGS. 8 and 9 (e). D flip-flop 3
The output of 03 is supplied to the selection circuits 313 and 316. D
The output of the flip-flop 303 is shown in FIG. 8 and FIG.
Shown in. The selection circuits 313, 314, 315, 316 are
Either one of the two inputs is output. The selection circuits 313, 314, 315, and 316 are (h), (i), (j), and (k) of FIGS. 8 and 9, respectively.
It is controlled so that the pixel data shown in FIG. The cycle marked with "*" in the figure has nothing to do with the interpolation process, and any output may be made. The outputs of the selection circuits 313, 314, 315, and 316 are output from the luminance signal interpolating unit input terminal 50 of the luminance signal interpolating unit 500, respectively.
1, 502, 503, 504.

The data supplied from the luminance signal interpolating unit input terminal 501 is supplied to the adder 531 via the D flip-flop 510. Further, the data supplied from the luminance signal interpolating unit input terminal 504 is supplied to the adder 531 via the D flip-flop 513 and the 1/2 multiplication coefficient unit 543. The output of the adder 531 is supplied to the minus side input terminal of the subtracter 534 via the D flip-flop 523, the 1/8 multiplier 544, and the D flip-flop 524. The data supplied from the luminance signal interpolating unit input terminal 502 is the D flip-flops 511, 514, 51.
5, the output of the D flip-flop 511 is supplied to the minus side input terminal of the subtracter 530 via the quarter multiplier 540.
The data supplied from the luminance signal interpolating unit input terminal 503 is the D flip-flop 512 and the 1/2 multiplication coefficient unit 54.
It is supplied to the plus side input terminal of the subtractor 530 via 2. The output of the subtractor 530 is the D flip-flop 517.
Then, it is supplied to the plus side input terminal of the subtractor 533, and at the same time, supplied to the minus side input terminal of the subtractor 533 via the 1/4 multiplier 541. Here, a process of multiplying the output of the D flip-flop 517 by 3/4 is performed. The output of the subtractor 533 is the D flip-flop 51.
8 and is supplied to the plus side input terminal of the subtractor 534. The output of the subtractor 534 is the D flip-flop 519.
And is supplied to the adder 532. The output of the adder 532 is led to the luminance signal interpolating unit output terminal 505 via the D flip-flop 520, the overflow processing circuit 550, and the D flip-flop 521.

The luminance signal interpolating section 500 has the above-mentioned configuration and the luminance signal interpolating section input terminals 501, 502, 50.
Input data of 3 and 504 are -2/16 times and 13 respectively.
/ 16 times, 6/16 times, and -1/16 times are added and the interpolated value output is obtained. Luminance signal interpolator input terminal 50
1, 502, 503, and 504 are times (t) as shown in (h), (i), (j), and (k) of FIGS. 8 and 9.
+4) to Y (1), Y (2), Y (3), Y
(4) is supplied. The luminance signal interpolator 500 performs the above calculation on these data, and the interpolated pixel data y (t + 2 + 1) at the time (t + 2 + 1/3) in FIGS. 8 and 9B.
/ 3) is calculated, and y (t + 2 + 1/3) is obtained at the luminance signal interpolating unit output terminal 505 at time (t + 10). Similarly, the luminance signal interpolation unit input terminals 501, 502, 5
03 and 504, (h), (i) of FIGS.
As shown in (j) and (k), Y (5), Y (4), Y (3), and Y (2) are supplied at time (t + 5), respectively. The luminance signal interpolating unit 500 performs the above calculation on these data, and the time (t + 3 + 2 //) in FIGS. 8 and 9B.
3) Interpolation pixel data y (t + 3 + 2/3) is calculated,
The luminance signal interpolating unit output terminal 505 receives y at time (t + 11).
(T + 2 + 2/3) is output. Similarly, from the luminance signal interpolating unit output terminal 505, interpolation pixel data y (t + 6 + 1/3) and y (t + 7 + 2/2) indicated by black circles in FIG.
3) are successively obtained at the timings shown in (l) of FIGS. 8 and 9.

The output of the luminance signal interpolating section output terminal 505 is
It is supplied to the selection circuit 308. In the selection circuit 308, the interpolation output of the luminance signal interpolation unit output terminal 505 and the D flip
Select one of the outputs of the flop 307 to output it,
The data string shown in (m) of FIGS. 8 and 9 is output. The output of the selection circuit 308 is derived by the switch 313,
Alternately, the memories 309 and 3 are used with the horizontal scanning cycle as a cycle.
12 are supplied. Data writing is performed in the memory to which the data is supplied, and reading is performed in the other memory. When writing data, the data marked with "*" shown in (l) of FIGS. 8 and 9 should not be written. The memory which has completed the write cycle turns to the read cycle in the next cycle, and the memory output becomes as shown in (n) of FIGS. 8 and 9. The selection circuit 310 alternately switches the horizontal scanning cycle as a cycle and selects the output of the memory which is always in the reading cycle. At the luminance output terminal 311, a sample string as shown in (m) of FIGS. 8 and 9 is obtained, and a signal waveform shown in (n) of FIGS. 8 and 9 is obtained. As can be seen by comparing (b) and (n) of FIGS. 8 and 9, the time compression is 3/4 times.

Next, the compression operation of the color signal which is the second signal sequence will be described with reference to the color signal processing timing charts of FIGS. The input terminal 400 has
A digitized color signal is input. The state of this signal component is shown in (b) and (c) of FIGS. There are I and Q (or R-Y, B-Y) components as color signals, but here it is assumed that both IQ signals are time-division-multiplexed and this is subjected to compression processing. 10 and 11
In (b), the white circles represent the samples, and I (0), Q (1), I (2), and Q as shown in FIG.
(2) ... will be described as a color signal sample sequence. In addition,
In FIG. 6A, the times are listed in order to explain the process. The digital color signal supplied from the color signal input terminal 400 is the D flip-flops 401, 402, 40.
It is supplied to the selection circuit 405 via 3, 404. The output of the D flip-flop 404 is shown in (e) of FIGS. The digital color signal supplied from the color signal input terminal 400 is also supplied to the selection circuits 410 and 411. The output of the D flip-flop 402 is the selection circuit 41.
0,411. D flip-flop 402
Output is shown in FIG. 10 and FIG.

The selection circuits 410 and 411 output either one of the two inputs.
From 411, FIG. 10 and FIG.
It is controlled so that the pixel data shown in (g) is output. The cycle marked with "*" in the figure has nothing to do with the interpolation process, and any output may be made. The outputs of the selection circuits 410 and 411 are supplied to the color signal interpolation unit input terminals 413 and 414 of the color signal interpolation unit 412, respectively.

The data supplied from the color signal interpolator input terminal 413 is supplied to the adder 419 through the D flip-flop 415 and the 1/2 multiplication coefficient unit 417. The output of the D flip-flop 415 is the 1/4 multiplier 418.
And is supplied to the adder 419. The output of the adder 419 is supplied to the adder 422 via the D flip-flop 420. The data supplied from the color signal interpolating unit input terminal 414 is supplied to the adder 422 via the D flip-flop 416, the quarter multiplier 430, and the D flip-flop 421. The output of the adder 422 is the D flip-flop 423, the overflow processing circuit 424, D
It is led to a color signal interpolator output terminal 426 via a flip-flop 425.

The color signal interpolating section 412 obtains an interpolated value by adding the input data of the color signal interpolating section input terminals 413 and 414 by 3/4 times and 1/4, respectively, by the above-mentioned configuration, and outputs it. is doing. Color signal interpolator input terminal 41
3 and 414, as shown in (f) and (g) of FIGS. 10 and 11, I (2) and I (4) at time (t + 4), respectively.
Is supplied. The color signal interpolating unit 412 performs the above calculation on these data, and the time (t + 2 + 2 /
3) Interpolated pixel data i (t + 2 + 2/3) is calculated,
At the time (t + 8), the i signal is output to the color signal interpolating unit output terminal 426.
Obtain (t + 2 + 2/3). In addition, the color signal interpolating unit input terminals 413 and 414 have (f) in FIGS.
As shown in (g), Q at time (t + 5)
(3) and Q (5) are supplied. The color signal interpolating unit 412 performs the above calculation on these data, and
(B) at time (t + 3 + 2/3) of the interpolated pixel data q
(T + 3 + 2/3) is calculated, and the color signal interpolation unit output terminal 4
At time (t + 9), the above q (t + 3 + 2/3) is obtained at 26. Similarly, from the color signal interpolating unit output terminal 426 to the interpolated pixel data i (t) indicated by black circles in FIGS.
+ 5 + 1/3), q (t + 6 + 1/3), i (t + 10)
+2/3), q (t + 11 + 1/3) ... Are successively obtained at the timings shown in (h) of FIGS. 10 and 11.

The output of the color signal interpolator output terminal 426 is supplied to the selection circuit 405. The selection circuit 405 selects and outputs the output of the color signal interpolator output terminal 426 and the output of the D flip-flop 404, and outputs the data shown in (i) of FIGS. 10 and 11. The output of the selection circuit 405 is supplied to the switch 427 and alternately supplied to the memories 406 and 409 with the horizontal scanning cycle as a cycle. In the memory to which the data is supplied, the data writing is performed, and in the other memory, the reading is performed. When writing data, the data marked with "*" shown in (i) of FIGS. 10 and 11 is not written. The memory which has completed the write cycle turns to the read cycle in the next cycle, and the memory output becomes as shown in (i) of FIGS. 10 and 11. The selection circuit 407 alternately switches the horizontal scanning cycle as a cycle and selects the output of the memory which is always in the reading cycle. At the color signal output terminal 408, the sample train as shown in (j) of FIGS. 10 and 11 is obtained, and the signal waveform shown in (k) of FIG. By such processing, the color signal is converted into the color signal shown in FIG.
As can be seen by comparing 0 and (b) and (k) of FIG. 11, time compression of 3/4 times is performed.

By the above-mentioned processing, the 3/4 time compression processing of the luminance signal and the color signal is performed. By the way, according to the above-described circuit configuration, the luminance signal interpolating unit 500 is configured as shown in FIGS.
As shown in (l), two interpolation value data may be calculated for every four cycles, and unnecessary dummy data is output for the remaining two cycles. As for the output of the D flip-flop 307, one data may be given to the selection circuit 308 every four cycles, and dummy data is output for the remaining three cycles. The same applies to the color signal, and the color signal interpolating unit 412 may calculate four interpolation value data for every 8 cycles as shown in (k) of FIGS. 10 and 11, and the remaining cycles are dummy data. Is being output. As for the output of the D flip-flop 404, two data may be given to the selection circuit 405 every eight cycles, and dummy data is output for the remaining six cycles. As described above, according to the above configuration, there are many cycles of generating dummy data.

[0013]

SUMMARY OF THE INVENTION The present invention provides an interpolation circuit which focuses on the generation of dummy data and causes the dummy data cycle to perform signal processing of the other system.

[0014]

According to the present invention, a plurality of systems of interpolating value calculating units are shared. That is, the first selection means for extracting the plurality of parallel data pieces of the digital data strings of the plurality of systems in a time division manner and the plurality of parallel data pieces output from the first selection means are supplied. The data processing apparatus further includes an interpolating unit that creates the interpolated data using the data, and a second selecting unit that separates and extracts the data of the same system among the interpolated data output from the interpolating unit.

[0015]

As a result, the circuit for calculating the interpolation value of one system is completely unnecessary, and the scale of the interpolation value calculating circuit can be reduced.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a time compression circuit according to an embodiment of the present invention. This will be described with reference to the timing charts of FIGS.

A digitized luminance signal is input to the luminance input terminal 200, and the state of the signal is shown in FIG.
It shows in (d). In FIG. 2B, white circles represent samples, and as shown in FIG. 2D, Y (0), Y (1), ... On the other hand, color input terminal 2
A digitized color signal is input to 18, and the state of the signal train is shown in FIGS. 2 (c) and 2 (h). The color signal has I and Q (or RY and BY) components, but here, it is assumed that both IQ signals are time-division multiplexed. In FIG. 2C, the white circles represent the sample,
As shown in (h), I (0), Q (1), I (2), Q
(2) ... will be described as a color signal sample sequence. In addition,
In FIG. 2A, times are listed in order to explain the process.

The digital luminance signal supplied from the luminance input terminal 200 is the D flip-flops 201, 202,
It is supplied to the selection circuits 204, 214 and 217 via 203. The output of the D flip-flop 203 is shown in FIG.
Shown in. The digital brightness signal supplied from the brightness input terminal 300 is also supplied to the selection circuits 214 and 217. D
The output of the flip-flop 201 is the selection circuits 215, 2
16 are supplied. The output of the D flip-flop 201 is shown in FIG. The output of the D flip-flop 202 is supplied to the selection circuits 215 and 216. The output of the D flip-flop 202 is shown in FIG.

On the other hand, the digital color signal supplied from the color signal input terminal 218 is the D flip flops 219, 2.
20, 221, 222, selection circuits 204, 214,
216. The output of the D flip-flop 222 is shown in FIG. The digital color signal supplied from the color input terminal 218 is also supplied to the selection circuits 214 and 216. The output of the D flip-flop 220 is the selection circuit 2
15 and 217. D flip-flop 22
The output of 0 is shown in FIG.

Selection circuits 204, 214, 215, 21
6 and 217 are respectively shown in FIG. 2 (k), FIG. 3 (m),
It is controlled to output the pixel data shown in (n), (o), and (p). Selection circuits 214, 215, 21
6 and 217 output luminance and color signals alternately
Input terminals 223, 224, 2 of the color signal interpolation processing unit 225
25, 226.

The selection circuit 204 is controlled so as to output the pixel data shown in FIG. Selection circuit 20
Also in No. 4, the luminance and color signals are output alternately. The output of the selection circuit 204 is the D flip-flops 205, 20.
It is supplied to the selection circuits 209 and 252 via 6, 207 and 208. The output of the D flip-flop 208 is shown in FIG.
It shows in (l). Selection circuits 214, 215, 216, 21
7 outputs the luminance and the luminance of the color signal interpolation unit 280, respectively.
Color signal interpolator input terminals 223, 224, 225, 226
Is supplied to.

The data supplied from the luminance / color signal interpolation unit input terminal 223 is supplied to the adder 249 via the D flip-flop 281. The data supplied from the luminance / color signal interpolating unit input terminal 226 is D flip
Adder 2 through flop 284 and 1/2 multiplier 232
49. The output of the adder 249 is a D flip
Flop 250, 1/8 multiplier 248, D flip
It is supplied to the minus side input terminal of the subtractor 241 via the flop 247. The data supplied from the luminance / color signal interpolating unit input terminal 224 is supplied to the adder 236 via the D flip-flop 282 and the 1/4 multiplier 230. After passing through the D flip-flop 282, D
It is supplied to the adder 243 via the flip-flops 233, 234 and 235. Luminance / color signal interpolator input terminal 2
The data supplied from 25 is the D flip-flop 2
It is supplied to the adder 236 via the 83 and 1/2 multiplication unit 231. The output of the adder 236 is the D flip-flop 2
After passing through 37, it is supplied to the plus side input terminal of the subtractor 239, and at the same time, it passes through the quarter multiplier 238 and the subtractor 23
9 is supplied to the minus side input terminal. Here, a process of multiplying the output of the D flip-flop 237 by 3/4 is performed. The output of the subtractor 239 is supplied to the plus side input terminal of the subtractor 241 via the D flip-flop 240. The output of the subtractor 241 is the D flip-flop 24.
It is supplied to the adder 243 via 2. The output of the adder 243 is supplied to the luminance / color signal interpolating unit output terminal 251 via the D flip-flop 244, the overflow processing circuit 245, and the D flip-flop 246.

The luminance / color signal interpolating unit 280 has the above-mentioned configuration, and the luminance / color signal interpolating unit input terminals 223 and 2 are provided.
Input the input data of 24, 225 and 226 to -1/2 respectively
Interpolated values obtained by adding 6 times, 13/16 times, 6/16 times, and -1/16 times are output. Thus, not only the luminance signal but also the color signal is the same as the circuit shown in the conventional example. Luminance / color signal interpolator input terminals 223, 2
24, 225, and 226 are shown in FIGS.
As shown in (o) and (p), Y (1), Y (2), Y (3), and Y (4) at time (t + 4), and Y (5) at time (t + 5), respectively. , Y (4), Y
(3), Y (2), I (6), I (4), I (6), I (4) at time (t + 6) and Q (7) at time (t + 5), respectively. ), Q (5), Q
Luminance / color signals are alternately input such as (7), Q (5). Regarding the color signal, the pixel data of the same color signal is supplied to the luminance / color signal interpolating unit input terminals 223 and 225, which is 1/4 times (-) the pixel data. This is to obtain (2/16) + (6/16). Similarly, the luminance / color signal interpolation unit input terminals 224 and 226 are also provided.
Also, the pixel data of the same color signal is supplied in order to obtain 3/4 times (13/16)-(1/16) of the pixel data. The luminance / color signal interpolation unit 280 performs the above calculation on these data, and after 6 cycles, the time (t + 2
+1/3) luminance interpolation pixel data y (t + 2 + 1 /)
3), luminance interpolation pixel data y at time (t + 3 + 2/3)
(T + 3 + 2/3), color interpolation pixel data i (t + 4 + 2/3) at time (t + 4 + 2/3), time (t + 5 + 2/3)
The color interpolation pixel data q (t + 5 + 2/3) ... Of 3) is continuously obtained at the output terminal 251 of the luminance / color signal interpolation unit 280.

The output of the luminance / color signal interpolation section output terminal 251 is supplied to the selection circuits 209 and 252. Selection circuit 2
In 09, the output of the luminance / color signal interpolating unit output terminal 251 and the output of the D flip-flop 208 are selected and output,
A portion of the luminance signal as shown in FIG. 3 (r) is selected. The output of the selection circuit 209 is supplied to the switch 260, and alternates with the horizontal scanning cycle as a cycle.
0,213. Data writing is performed in the memory to which the data is supplied, and reading is performed in the other memory. When writing data, see Figure 3.
Do not write the data marked with "*" shown in (r). The memory that has completed the write cycle shifts to the read cycle in the next cycle. In the selection circuit 211,
The horizontal scanning cycle is switched alternately as a cycle, and the output of the memory that is always in the read cycle is selected. The luminance output terminal 212 is shown in FIG.
A sample train as shown in Fig. 3 is obtained, and the signal waveform shown in Fig. 3 (v) is obtained.

The selection circuit 252 selects and outputs the output of the luminance / color signal interpolation output terminal 251 and the output of the D flip-flop 208, and selects the color signal portion as shown in FIG. 3 (s). . The output of the selection circuit 252 is supplied to the switch 261, and alternately supplied to the memories 253 and 254 with the horizontal scanning cycle as a cycle. Data writing is performed in the memory to which the data is supplied, and reading is performed in the other memory. When writing data, the data marked with "*" shown in FIG. 3 (s) is not written. The memory that has completed the write cycle shifts to the read cycle in the next cycle. Selection circuit 2
Reference numeral 56 alternately switches the horizontal scanning cycle as a cycle, and selects the output of the memory which is always in the read cycle. The color output terminal 257 is shown in FIG.
A sample train as shown in (u) is obtained, and a signal waveform shown in FIG. 3 (w) is obtained. Through the above processing, the luminance / color signal compression processing is performed.

Although the conventional image compression circuit and the embodiment shown in FIG. 1 are completely the same in characteristics, when the circuit configuration is focused, the color signal interpolation processing section 412 dedicatedly used as the conventional color signal interpolation circuit is used. It has disappeared and the circuit scale has become smaller. The larger the interpolation processing unit, the greater the merit of circuit scale reduction according to the present invention.

FIG. 4 shows another embodiment. As described above, the interpolation value calculation method in the conventional example and the above-described embodiment uses -2 // for each of four continuous luminance pixel data in the luminance signal.
The interpolation value is calculated by multiplying 16, 13/16, 6/16, and -1/16 to obtain the sum. As for color signals, two consecutive color pixel data are divided into 1/4 and 3 respectively.
Interpolation values have been calculated by multiplying by / 4 to obtain the sum.
The reason why the interpolation value calculation is performed only for color signals by using two color pixel data is to avoid the increase in the scale of hardware.
In order to perform the color signal interpolation better, it is necessary to calculate the interpolation value from four pixels like the luminance signal. According to the configuration shown in FIG. 3, the D flip-flops 800, 801,
803 and 804 are added, and the selection circuit 215 of FIG.
217 is replaced with the selection circuits 805 and 806 of FIG. 3, and the selection circuits 204, 214, 805, 216 and 80 of FIG.
The input of 6 has changed. As the operation, the above-mentioned first
Since it is exactly the same as the embodiment described above, the description thereof will be omitted. 5 and 6 are timing charts showing the operation of the embodiment of FIG. In the figure, (a) is time, (b) is a luminance signal waveform diagram supplied to the luminance input terminal 200, (c) is a color signal waveform diagram supplied to the color input terminal 218, and (c) is a luminance signal input terminal 200. Luminance signal, (d) color signal supplied to the color input terminal 218, (e) D flip-flop 201 output,
(F) is D flip-flop 202 output, (g) is D
Flip-flop 203 output, (h) color input terminal 2
18 is a color signal, (i) is a D flip-flop 801 output, (j) is a D flip-flop 220 output, (k) is a D flip-flop 222 output, and (m).
Is the output of the selection circuit 204, (n) is the output of the D flip-flop 208, (o) is the output of the selection circuit 214, (p) is the output of the selection circuit 805, (q) is the output of the selection circuit 216,
(R) is the output of the selection circuit 806, (s) is the output of the brightness / color signal interpolator output terminal 251, (t) is the output of the selection circuit 209, (u) is the output of the selection circuit 252, and (v) is the brightness output terminal 212. Output, (w) is the color output terminal 257 output, (x)
Shows a compressed luminance signal waveform diagram, and (y) shows a compressed chrominance signal waveform diagram.

In the description of the present invention, the 3/4 time compression circuit is used as an example throughout the description.
It goes without saying that the present invention can also be applied to time compression with other ratios. Further, the present invention is characterized in that, when the inter-sample interpolation of a plurality of signals is simultaneously performed, the circuit scale can be reduced by sharing a part or all of the interpolation value calculation unit. Therefore, according to the present invention, the interpolation circuit can be applied not only to the time compression but also to the sample rate conversion device and the time expansion circuit.

In the embodiment of FIG. 1, only one interpolator 280 is shown. However, a plurality of such interpolators are provided in parallel, and the interpolated data from each interpolator is arbitrarily selected for each same system. You may make it isolate | separate into. Even in this case, the circuit scale can be markedly reduced as compared with the case where the interpolation circuit is provided for each system, and the effect of the present invention becomes remarkable. In the case of performing time expansion or time compression, by providing the interpolation units in parallel in this way, it is possible to obtain an interpolation circuit that is easy to use. The types of signals to be handled are not limited to luminance and color signals, and may be combinations of other signals. For example, it is a low frequency component and a high frequency component or a high definition component of the luminance signal. Further, the clock frequency to be used may be switched or the clock frequency may be partially switched depending on the type of the signal to be handled.

[0030]

According to the present invention described in detail above, when two systems of signals are respectively interpolated, the interpolation processing section can be shared and the circuit scale can be reduced. Moreover, since the circuit scale is reduced, the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram shown to explain the operation of the circuit of FIG.

FIG. 3 is a timing chart showing a continuation of FIG. 2;

FIG. 4 is a diagram showing a second embodiment of the present invention.

5 is a timing diagram shown to explain the operation of the circuit of FIG.

FIG. 6 is a timing chart showing a continuation of FIG. 5;

FIG. 7 is a diagram showing a conventional 3/4 image compression circuit.

8 is a timing diagram shown for explaining the operation of the circuit of FIG.

FIG. 9 is a timing chart showing a continuation of FIG. 8;

10 is a timing diagram shown for further explaining the operation of the circuit of FIG.

FIG. 11 is a timing chart showing a continuation of FIG. 10;

[Explanation of symbols]

201-208, 219-222, 281-284, 2
33-235, 237, 240, 242, 244, 24
6, 247, 250, ... D flip-flops, 20
4, 214-217, 209, 252, 211, 256
... Selection circuit, 210, 213, 243, 254 ... Memory, 245 ... Overflow processing circuit, 230, 23
1, 232, 238, 248 ... Coefficient unit, 280 ... Luminance
Color signal interpolation unit 280.

Claims (4)

[Claims] 1. A first selection means for extracting, in a time division manner, a plurality of parallelized data of digital data strings of a plurality of systems, and a plurality of parallelized data output from the first selection means are supplied. An interpolating means for time-divisionally creating interpolation data for each system using the plurality of data; and a second selecting means for separately extracting data of the same system among the interpolation data output from the interpolating means. An interpolating circuit comprising: 2. A plurality of input terminals to which digital data trains of a plurality of systems are respectively supplied, first selecting means for taking out digital data trains of the respective input terminals in time division, and each of the digital data trains. Of the data of (1) is controlled by delay time to interpolate the interpolated data of each digital data string in a time division manner, and the output interpolated data from the interpolated means is supplied and the output of the first selection means is commonly used. A plurality of systems of selection means for extracting only the data of the systems that are respectively supplied in advance, a plurality of systems of memory means to which the outputs selected by the plurality of systems of selection means are respectively supplied, and an output of the memory means. An interpolating circuit comprising: deriving means for deriving each. 3. A first data string sampled at a first sampling frequency is supplied to an interpolation value calculation circuit, and the output of this interpolation value calculation circuit is selected to select the first sampling frequency and the periodicity. And a first data deriving means for generating a new second data string sampled at a second sampling frequency, and the third data string sampled at a third sampling frequency are interpolated as described above. A second sequence for supplying a value calculation circuit and selecting an output of the interpolation value calculation circuit to generate a fourth data string sampled at a fourth sampling frequency having periodicity with the third sampling frequency. The data deriving means and the control means for operating the interpolation value calculation circuit in a time division manner. 4. A first delay means for synchronizing a plurality of pixels of a first signal pixel row and making them parallel to each other, and a second delay means for making a plurality of pixels of a pixel row of a second signal simultaneously and making them parallel. Delay means, first selection means to which the first set of first signal pixels and second signal pixels from the first and second delay means are supplied, and the first and second delay means First signal pixel and second signal from the means
Of the plurality of second selection means to which the remaining first signal pixels and second signal pixels are respectively supplied, and output pixels of the plurality of second selection means. An interpolating unit that obtains the interpolated pixel and the second interpolated pixel in a time division manner, and an output pixel from the interpolating unit are respectively supplied, and a pixel from the first selecting unit is supplied to each of the first and second interpolating units. An interpolation circuit, comprising: third and fourth selecting means for deriving a pixel row of signals and a pixel row of second signals, respectively.