JPH06327035A - Muse/ntsc converter - Google Patents

Abstract

PURPOSE:To decrease the number of circuit parts, to reduce a circuit scale, to attain cost reduction, and to realize high picture quality by reducing the flurring in the contour parts of an output picture. CONSTITUTION:A vertical filter 5 converts the 1125 pieces of scanning lines of a MUSE system into the number of scanning lines in a prescribed mode of NTSC system. At the same time, an enhancer in a vertical direction is operated, and each processing of a sub-sample turn-back processing, and line sequential decode processing is operated. A time base conversion circuit 7 converts a data rate from the MUSE system to the NTSC system. In an NTSC system processing circuit 9, an extending circuit 10 extends a TCI-transmitted color difference signal into four-fold data, a point successive decoder 11 operates a point successive decode processing to a chrominance signal, and separates two color difference signals, an NTSC processing circuit 12 adds an NTSC system synchronizing signal or a blanking to a video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion device, and more particularly to a video signal of MUSE system in NTSC.
The present invention relates to a MUSE / NTSC converter for converting a video signal of a standard format.

[0002]

2. Description of the Related Art In high-definition broadcasting, video signals are compressed by the MUSE system and transmitted by satellite waves. For the principle of this MUSE system, the signal processing system, the configuration of the receiving device, etc., see “Development of MUSE System”, “NHK Technical Research Journal, Vol. 39, No. 2, pp.
987) ”, which is characterized in that the number of scanning lines is 1125 and the aspect ratio of the screen is 16: 9. Further, in the MUSE system, for band compression, subsample transmission is performed by thinning out pixels every other sample for transmission, and color signals are also subjected to ¼ time compression and TCI (Time Compressed Integration) signalization by line-sequential multiplexing. Is going.

This MUSE video signal (hereinafter referred to as MU
To receive (SE signal) MUSE decoder,
Alternatively, a MUSE / NTSC converter for converting a high-definition MUSE signal into a current NTSC video signal (hereinafter referred to as an NTSC signal) in a simpler manner is required, and the development of these products is currently in progress. Of these, the latter method of converting the MUSE signal into the NTSC signal is described in "TV Society Journal, VOL. 44,
NO. 6pp705-712 "Development of MUSE-525 converter", (1990) ".

This MUSE / NTSC converter is roughly divided from the viewpoint of signal processing, and includes a MUSE signal processing section, a time axis conversion processing section for converting the data rate from the MUSE system to the NTSC system, a scanning line conversion and an aspect conversion. It is composed of an NTSC system signal processing unit for performing processing and converting it into an NTSC format signal.

As a method of displaying an MUSE original image with an aspect ratio of 16: 9 on an NTSC display with an aspect ratio of 4: 3, a 16: 9 image is compressed in the horizontal direction and a full mode is displayed, There are three methods: a wide mode in which a horizontally long image of 9: 9 is displayed as it is and the top and bottom of the screen are blank areas, and a zoom mode in which the left and right portions of a 16: 9 image are cut off and the central portion is extracted and enlarged.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention MUSE / N
In the TSC converter, it is necessary to perform scanning line conversion and aspect conversion processing in order to display a desired NTSC image on a normal display. It is necessary to perform the returning process and the TCI decoding process for converting the color signal into the TCI signal.

However, in the conventional MUSE / NTSC converter, each processing as described above is performed in a separate block, so that each block requires a circuit component such as a dedicated digital circuit or line memory. However, there has been a problem that the circuit scale is greatly increased and the cost is also increased. Also the conventional MUSE
In the / NTSC converter, a vertical filter and a horizontal filter are used in order to perform the above-mentioned scanning line conversion and sub-sample returning processing, but because of this, the frequency characteristics of the high frequency band of the output image drop and the outline part is blurred. There was a problem.

An object of the present invention is to solve the above-mentioned problems of the prior art, reduce the number of circuit parts, reduce the circuit scale, and reduce the cost.
/ NTSC converter.

Another object of the present invention is to provide a MUS capable of realizing high image quality by reducing blurring of the contour portion of an output image.
It is to provide an E / NTSC converter.

[0010]

In order to achieve the above object, according to the present invention, in a MUSE / NTSC converter, a MUSE signal processing circuit, a scanning line converting means, a vertical enhancing means, a sub-sample returning processing means, and a color signal A vertical filter composed of line-sequential decoding processing means, a time axis conversion means for converting the data rate from the MUSE system to the NTSC system, and N including color expansion and point-sequential decoding processing means.
And a TSC signal processing circuit.

[0011]

The MUSE signal processing circuit carries out input processing and synchronization detection processing of MUSE signals. In the above-mentioned vertical filter, basically, the scanning line conversion means performs the scanning line conversion from the MUSE system to the NTSC system, but at the same time, it also serves as the line memory and the coefficient unit, and the high frequency component is extracted by the vertical enhancement means. Addition is performed, and interpolation processing is performed by the sub-sample returning processing means. Further, in the vertical filter, the line-sequential decoding processing means also performs dot-sequential processing or separation processing of color signals. At least with the time axis conversion means,
The data rate of the video signal is converted from the MUSE system to the NTSC system, but time extension of the color signal is also performed. Next, the above NT
The SC signal processing circuit converts at least the video signal after time-axis conversion into a predetermined NTSC signal format.
It also performs time extension of the color signal and dot-sequential decoding operation.

Thus, according to the present invention, MUSE / NTS
By performing the sub-sample returning processing of the MUSE signal and the line-sequential decoding processing of the color difference signals, which are both necessary for the C conversion processing, in the vertical filters that perform the scanning line conversion, the digital circuit and the like can be shared. A block for performing the sub-sample returning process and a block for performing the line-sequential decoding process related to the TCI decoding process are not required, so that circuit components can be reduced, the circuit scale can be reduced, and the cost can be reduced. In addition, by performing vertical enhancement processing in the vertical filter as well, line memory and digital circuits can be shared, circuit components can be reduced, and blurring of the outline portion can be reduced by enhancing the outline of the output image. Therefore, high image quality can be realized.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a MUSE as an embodiment of the present invention.
It is a block diagram which shows a / NTSC converter. In FIG. 1, 1 is a MUSE signal input terminal, 2 is an A / D converter, 3 is a MUSE signal processing circuit, 4 is a MUSE clock generation circuit, 5 is a vertical filter, 6 is a horizontal filter, and 7
Is a time axis conversion circuit, 8 is an NTSC clock generation circuit,
Reference numeral 9 is an NTSC processing circuit, 13 is a D / A converter, 14 is an NTSC encoder, and 15, 16 and 17 are output terminals. The NTSC processing circuit 9 is composed of a decompression circuit 10, a dot sequential decoder 11 and an NTSC processing circuit 12.

In FIG. 1, the A / D converter 2 samples the MUSE signal from the input terminal 1 at a sampling frequency of 16.2.
Converted to MHZ digital signal. The MUSE signal processing circuit 3 includes a de-emphasis process, a sync detection process, and an ALC.
(Automatic Level Control) Operates. The MUSE clock generation circuit 4 generates various MUSE clocks required by the MUSE signal processing circuit 3.

The vertical filter 5 converts 1125 scanning lines of the MUSE system into the number of scanning lines of a predetermined mode of the NTSC system. At the same time, in the vertical filter 5, as will be described later in detail, the enhancer in the vertical direction is applied, the MUSE signal returned by the sub-sample is returned (sub-sample returned), and the color difference transmitted by the line-sequential is transmitted. Each processing such as signal decoding processing (line-sequential decoding processing) is also performed. That is, in the present embodiment, a vertical filter for performing scanning line conversion, which is necessary for the MUSE / NTSC conversion process, is the sub-sample returning process of the MUSE signal, the line-sequential decoding process of the color difference signals, and the vertical direction enhancing process. 5 is done at the same time.

Now, the configuration and operation of the vertical filter 5 will be described in detail. FIG. 2 shows the vertical filter 5 of FIG.
It is a block diagram which shows one specific example. In FIG. 2, first, the scanning line conversion processing unit for the luminance signal Y will be described.

In FIG. 2, reference numeral 18 is an input terminal for the MUSE signal from the MUSE signal processing circuit 3, 19, 20, and 2.
1, 22 are line memories connected in cascade, 23, 25, 2
6, 28, 29 and 31 are coefficient multipliers for multiplying the coefficient (−α / 4), and 24, 27 and 30 are coefficient (1 + α) respectively.
/ 2) coefficient multipliers, 32, 33, 34 adders, 3
5, 36 and 37 are variable coefficient data converters, 38 is a control circuit, and 39, 40, 41 and 42 are input terminals for mode switching signals, field switching signals, line switching signals, and sub-sample phase signals.

In FIG. 2, the line memories 19, 20,
Reference numerals 21 and 22 each serve as a 374 pixel delay memory corresponding to the number of luminance signal 1 line samples in MUSE transmission. Next, the coefficient units 23 to 31 respectively input the output signals from the line memories 19, 20, 21, and 22, multiply by the above-mentioned predetermined coefficient, and output. And coefficient unit 2
The outputs of 3, 24 and 25 are the adder 32 and the coefficient units 26 and 2
The outputs of 7, 28 are added by the adder 33, and the coefficient units 29, 3
The outputs of 0 and 31 are added by the adder 34, respectively.

As is well known, the coefficient unit and the adder each constitute a vertical enhancer of the luminance signal. That is, in the adder 32, the signal obtained by multiplying the current incoming signal by the value α / 2 in the coefficient (1 + α / 2) by the coefficient unit 24, the signal one line before the current incoming signal and the one line delay The coefficients (-α /
4) and the signal obtained by multiplying, respectively, to extract the high frequency component of the current signal, and at the same time, multiply the value 1 in the coefficient (1 + α / 2) by the coefficient unit 24 to obtain the current signal. The signal itself is added to create a signal with increased gain in the high frequency range. Therefore, its output becomes the vertical contour emphasis signal of the output signal of the line memory 19 described above. The output of the adder 33 is the vertical contour enhancement signal of the signal from the memory 20, and the output of the adder 34 is the vertical contour enhancement signal of the signal from the memory 21. In addition, 1 to 0.5 is suitable for α in the above-mentioned coefficient value.

Next, the variable coefficient data converters 35, 36,
37 inputs the signals from the adders 32, 33 and 34, respectively, multiplies the signals by a predetermined coefficient, and outputs the signals to the adder 43. These variable coefficient data converters 35, 36, 37 are
By the operation of the control circuit 38, the coefficient is appropriately switched and controlled based on the mode switching signal for switching the display mode (scanning line conversion mode), the field switching signal, the line switching signal, and the sub-sampling phase signal. In this way, the signal obtained as the output of the adder 43 is the scanning line converted luminance signal, and at the same time,
Vertical enhancement processing and sub-sample returning processing described later are also performed. This output signal is led to the output terminal 44.

The above scanning line conversion processing operation of the luminance signal is one of the display modes in the wide mode (the number of scanning lines is 3 → 1).
Book) will be described with reference to FIG. First, in the first field, the incoming signal and 1 line and 2
The line-delayed signals (the outputs of the adders 32, 33, and 34 with the enhancer in FIG. 2) are added to the coefficients (k1, k2, k) in variable coefficient data converters 35, 36, and 37.
3) is multiplied, for example, as (1/4, 1/2, 1/4), the signals obtained thereby are added to each other in the adder 43, and one scan of a new center of gravity is performed from three scan lines. Make a line. Next, also in the second field, as shown in FIG.
Similar conversion processing is performed as shown in FIG. Since the scanning line conversion process is different for each display mode, the coefficients (k1, k) in the variable coefficient data converters 35, 36, 37 described above are used.
2, k3) are changed and controlled by the function of the control circuit 38 for each display mode. Further, as will be described later, the variable coefficient data converters 35, 36 and 37 also perform sub-sample returning processing at the same time.

Here, these variable coefficient data converters 3
A specific example of the variable coefficient data converter 35 among 5, 36 and 37 will be described with reference to FIG. FIG. 4 is a block diagram showing a specific example of the variable coefficient data converter 35 of FIG. 4, 68 is the adder 32 of FIG.
Input terminals for signals from, 69, 70, 71, 72 are level converters, 73, 74, 75, 76 are switch circuits, 7
Reference numeral 7 is an adder, 78 is an input terminal for a control signal from the control circuit 38 of FIG. 2, and 79 is an output terminal.

In FIG. 4, level converters 69, 70,
Reference numerals 71 and 72 respectively represent signals input from the adder 32 of FIG. 2 via the input terminal 68 by 1/16, 1/8, 1 /.
Convert the level to 4 or 1/2. Switch circuits 73 and 7
4, 75, and 76 have level converters 69-
The signal from 72 is input, and the "0" level signal is input to the b terminal. The adder 77 is c of the switch circuits 73 to 76.
The output signals from the terminals are added together and the result is output to terminal 7.
Output to 9.

The opening / closing control of the switch circuits 73 to 76 is performed based on the control signal input from the control circuit 38 of FIG. 2 via the input terminal 78. For example, the setting of the coefficient k1 of the variable coefficient data converter 35 is as shown in FIG.
K1 = 1/4 when converting from 3 luminance signals to 1 luminance signal
In the case of, only the switch circuit 75 is closed to the point a, and the other switch circuits 73, 74 and 76 are closed to the point b. Therefore, the output of the adder 77 is a signal multiplied by the coefficient 1/4. In addition, the coefficients other than this are the switch circuits 73 to 76.
The combination of the open / closed states is sequentially changed by the action of the control signal from the input terminal 78 to generate. Also, the level converter 69
As a realization method of ˜72, for example, for the level converter 72 which performs level conversion of ½, input data is MS
For the level converter 71 that performs 1-bit level conversion from B to LSB and also performs 1/4 level conversion,
Each can be achieved by bit shifting.

The variable coefficient data converter 35 also performs sub-sample returning processing at the same time. The sub-sample returning process will be described below with reference to FIG.
FIG. 5 is an explanatory diagram for explaining the sub-sample returning processing performed by the variable coefficient data converter 35 of FIG. 4, in which the vertical direction corresponds to the vertical direction of the screen and the horizontal direction corresponds to the horizontal direction of the screen. ing.

In the MUSE system, as shown in FIG.
The sample pattern is a sample pattern in which each pixel and line are alternately arranged with sample points marked with ◯ and non sample points marked with × that are transmitted at a sample rate of 6.2 MHz. The variable coefficient data shown in FIG. In each of the switch circuits 73 to 76 of the converter 35, the "0" level data is interpolated at the timing of the non-sampling point of X that is not transmitted. This is a sub-sample phase signal (input terminal 42 of FIG. 2) transmitted as a control signal in the MUSE signal.
Is input to the control circuit 38. ), The switch circuits 73 to 76 are all closed to the terminal b. Therefore, the data rate of the luminance signal from the variable coefficient data converter 35 is 32.4 MHz which is twice the transmission rate.

The configuration and operation of the variable coefficient data converter 35 described above are the same as those of the other variable coefficient data converters 36 and 37.
Is also the same.

Next, referring to FIG. 2, the scanning line conversion processing unit for the color difference signal C will be described. In FIG. 2, 41 is a delay circuit, 45, 46, 47, 48, 49 are line memories, 5
0, 51, 52, 53, 54, 55 are variable coefficient data converters, 56, 57 are adders, 58 is a multiplexer, 5
9 is an output terminal.

In FIG. 2, the delay circuit 41 delays the MUSE signal from the input terminal 18 for a period of four lines. This is because the color signal in the MUSE signal is transmitted four lines ahead of the luminance signal, so that the delay circuit 41 matches the luminance signal and the color signal with the timing on the same scanning line to facilitate the subsequent processing. This is because

Next, since the chrominance signal in the MUSE signal is compressed to 1/4 of the luminance signal and transmitted, the line memories 45, 46, 47, 48 and 49 serve as line memories for color difference signal processing. , 1/4 the capacity of the luminance signal. Also, these line memories 45 to 49,
Variable coefficient data converters 50 to 55 and adders 56 and 57
Constitute a scanning line conversion filter for color signals (vertical filter), and the two color difference signals R-Y and B-Y subjected to scanning line conversion are alternately output from the adder 56 for each line. Similarly, the adder 57 outputs the two scanning-line converted color difference signals BY and RY alternately for each line.

Further, in the variable coefficient data converters 50 to 55, at the same time, the sub-sample returning process is performed on the color difference signals as in the case of the luminance signals.

Next, the multiplexer 58 operates the adder 5
Color difference signals R alternately output from 6 and 57 for each line
-Y and BY are alternately multiplexed for each pixel to create a dot-sequential color difference signal and lead it to the output terminal 59. This multiplexer 5
The multiplex control of 8 is performed by the control signal from the control circuit 38.

The scanning line conversion processing operation of the color difference signals described above will be described with reference to FIG. 3B in the wide mode (3 scanning lines → 1 conversion) as in the case of the luminance signal. In the MUSE system, the color difference signals RY and BY are shown in FIG.
Since it is sent line-sequentially as in (b), each color difference signal is subjected to filter calculation by sampling pixel data every two lines. Therefore, in the first field, for example, when the incoming signal is the color difference signal RY, the coefficients (k4, k5, k) of the variable coefficient data converters 50, 51, 52 in FIG.
6), for example, (1/4, 1/2, 1/4),
(1/2, 1/2, 0) is alternately repeated at a cycle of 7 lines. At this time, the coefficients (k7, 5) of the variable coefficient data converters 53, 54, 55 for the color difference signal BY
k8, k9) are (1/2, 1/2, 0), (1
/ 4, 1/2, 1/4) are alternately repeated in a cycle of 7 lines. Also in the second field, similar conversion processing is performed as shown in FIG.

The configuration and operation of the variable coefficient data converter 35 described with reference to FIGS. 4 and 5 are the same for the variable coefficient data converters 50 to 55 described above. Therefore, the outputs from the variable coefficient data converters 50 to 55 are subjected to the sub-sample returning process and have a rate of 32.4 MHz. Therefore, as described above, the color difference signals RY, which have undergone the scanning line conversion and the sub-sample returning processing,
BY is subjected to 32.4 by the multiplexer 58 of the next stage.
Each pixel is alternately multiplexed at the MHZ rate. Above, FIG.
The configuration and operation of the vertical filter 5 in FIG.

Next, referring to FIG. 1, the horizontal filter 6 is
The luminance signal and the color difference signal processed by the vertical filter 5 are subjected to high-frequency correction filter processing. Although not shown in the drawing, the horizontal filter 6 may be configured to have a horizontal enhancer function, like the vertical filter 5 described above.

Next, the time axis conversion circuit 7 converts the MUSE data rate into the NTSC data rate. A field memory of several megabits is usually used for this data rate conversion, and the video signal data from the horizontal filter 6 is supplied to the MUSE clock generation circuit 4
This is performed by writing to the field memory with the MUSE write clock from the above and read with the NTSC read clock described later.

On the other hand, the NTSC system clock generation circuit 8
The NTSC system read clock required by the time axis conversion circuit 7 described above and various clocks required by the NTSC system processing circuit 9 and the NTSC encoder 14 described later are generated and supplied.

Next, the NTSC processing circuit 9 inputs the luminance signal Y and the color difference signal from the time base conversion circuit 7, and the decompression circuit 10 receives TCI (Time-Compressed Integration).
The transmitted color-difference signal is time-expanded to four times the data to have the same data length as the luminance signal. A FIFO memory, for example, is used for the decompression circuit 10.

In the next dot-sequential decoder 11, the color-difference signal line-sequentially decoded by the vertical filter 5 is further dot-sequentially decoded to obtain two color-difference signals R-Y,
Separate into BY. Here, the configuration and operation of the dot-sequential decoder 11 will be described in detail.

FIG. 6 is a circuit diagram showing a specific example of the dot-sequential decoder 11 shown in FIG. 6, 80 is an input terminal for the color difference signal Cd from the expansion circuit 10 in FIG. 1, 81 is a clock input terminal, 82 and 84 are data latch circuits, and 83 is an inverter circuit.

In FIG. 6, the color difference signal Cd from the input terminal 80 is input to the data input terminals of the data latch circuits 82 and 84, and the clock ck from the input terminal 81 is input to the clock input terminal of the data latch circuit 82. At the same time, it is inverted by the inverter circuit 83 and input to the clock input terminal of the data latch circuit 84. The clock ck from the input terminal 81 is synchronized with the color difference signal Cd from the input terminal 80.

Regarding the dot-sequential color difference signal Cd input, for example, the data latch circuit 82 separates and outputs the color difference signal RY, and the data latch circuit 84 separates and outputs the color difference signal BY. Output terminals 85, 8
It is output from 6.

The configuration and operation of the dot-sequential decoder 11 in FIG. 1 have been described above in detail.

Next, referring to FIG. 1, the NTSC processing circuit 1
2 adds an NTSC system synchronizing signal to the obtained video signal, or adds blanking to the video signal so that the projected image has a predetermined aspect display.

The D / A converter 13 receives the digital luminance signal Y and the digital color difference signals RY and BY from the NTSC processing circuit 9 and converts them into analog signals.

Further, the NTSC encoder 14 uses D /
The luminance signal Y and the color difference signals RY, B- from the A converter 13
A luminance signal Y in NTSC format, a chroma signal C or a composite video signal C.V is created from Y and output to output terminals 15, 16 and 17, respectively. Although not shown, these video signals from the output terminals 15, 16 and 17 are input to, for example, a TV monitor or the like and displayed as NTSC images.

The overall signal processing by the MUSE / NTSC converter of FIG. 1 described above is as shown in FIG. FIG. 7 is an explanatory diagram for explaining changes in the data structure of the video signal in each signal processing by the MUSE / NTSC converter of FIG.

In FIG. 7, first, in the incoming MUSE signal, the chrominance signal C precedes the luminance signal Y by four lines, and the chrominance signal C is transmitted line-sequentially in the order of RY and BY. The signals are time-multiplexed and transmitted from the No. 5 position. In addition, the color signal C is compressed to 1/4 on the time axis, and
As sample points of the line, the luminance signal Y is 374 points, while the color signal C is 94 points.

Next, regarding the scanning line conversion processing by the vertical filter 5, in the wide mode for converting from three scanning lines to one, as shown in FIG. 7, the color signal C is line-sequentially decoded and input three lines are input. To 1 line to the color difference signal R
-Y is 94 points, BY is 94 points, and luminance signal Y is 374 points.

At the same time, by the sub-sample returning process by the vertical filter 5, the sample points in one line are
Both the color signal C and the luminance signal Y are doubled, and the color signal C is alternately multiplexed with the color difference signals RY and BY, and as a point-sequential color difference signal, 188 × 2 = 376 points, and the luminance signal Y is 748. It becomes a point. The color signal C and the luminance signal Y are separately output from the vertical filter 5.

Next, as shown in FIG. 7, the color signal is expanded four times through the time axis conversion circuit 7 and the expansion circuit 10, and 752 sampling points of the color difference signals RY and BY are obtained. And is output separately from the luminance signal.

Next, the color signals are processed by the dot-sequential decoder 11 as shown in FIG.
The luminance signal is separated into two signals of Y and the luminance signal is 748 points, and the color difference signal RY and the color difference signal B are separated.
-Y is 752 points. In addition, (*) in FIG.
This will be described later.

By the way, the specific example of the vertical filter 5 described in FIG. 2 is an example in which the luminance signal and the chrominance signal are passed through different line memories to perform the filtering process.
Focusing on the fact that the E signal is time-division multiplexed with the luminance signal and the chrominance signal, an example of performing filter processing using a line memory common to both signals will be described below.

FIG. 8 is a block diagram showing another specific example of the vertical filter 5 of FIG. 8, the same components as those in FIG. 2 are designated by the same reference numerals. In addition, 60 is a luminance signal / color signal transmission timing signal input terminal, 61 is a selector, 62, 63, 64, 64, 65 and 66 are line memories, and 67 is a control circuit.

In FIG. 8, the selector 61 is a MUSE.
The luminance signal transmission period of the signal is closed at point a, and the color signal transmission period is closed at point b. Therefore, the color signal transmitted four lines ahead is output from the selector 61 via the delay circuit 41, so that the timing is matched with the same scanning line period as the luminance signal, and the subsequent processing becomes easy. The selector 61 is controlled by a control signal c1 from a control circuit 67 described later.
By. Line memories 62, 63, 64, 64, 6
Reference numerals 5 and 66 each serve as a delay memory of 480 elements in which the numbers of samples of the luminance signal and the color signal are combined.

The vertical enhancer function of the luminance signal by the line memories 62 to 66, the coefficient units 23 to 31, and the adders 32 to 34, and the variable coefficient data converters 35 and 3 are provided.
The scanning line conversion operation and the sub-sampling returning processing by 6 and 37 are the same as those in the specific example described in FIG. However, since the control circuit 67 needs to perform the variable control of the variable coefficient data converters 35, 36, 37 and the control of the selector 61 by the time division control with the luminance signal / color signal, the luminance from the input terminal 60 is controlled. The signal / color signal transmission timing signal c2 is input, and the above-mentioned control signal c1 is output based on it. Further, since the scanning line conversion processing of the color signal is also performed by sharing the above-mentioned line memories 62 to 66 in a time division manner, the operation is also the same as that of the specific example described in FIG.

In the embodiment of FIG. 1 described above, the color difference signal decompression circuit 10 is arranged in the NTSC system processing circuit 9, but the decompression circuit 10 is arranged in the time axis conversion circuit. The time extension of the color difference signal may be performed simultaneously with the data rate conversion. Further, the color-difference signal dot-sequential decoder 11 is also arranged in the NTSC system processing circuit 9. However, the color-difference signal dot-sequential decoding processing is arranged in the vertical filter to perform scanning line conversion. It may be performed at the same time as the processing. An embodiment having such a configuration will be described with reference to FIG.

FIG. 9 shows a MUS as another embodiment of the present invention.
It is a block diagram which shows an E / NTSC converter. Figure 9
In FIG. 1, the same components as those in FIG. 1 are designated by the same reference numerals. In addition, 90 is a vertical filter, 91 is a horizontal filter, and 92 is a time axis conversion circuit.

One of the differences of the present embodiment from the embodiment of FIG. 1 is that in the vertical filter 90, the color difference signal processing is not only scanning line conversion and sub-sample returning processing but also line sequential / point sequential decoding processing. , And the color difference signals RY and BY are output in parallel with the luminance signal Y. Therefore, in the horizontal filter 91, the luminance signal Y and the color difference signal R-
Y and B-Y are input to perform high frequency correction filter processing.

Two different points are the time axis conversion circuit 9
2, the time axis conversion circuit 7 described in the embodiment of FIG.
Not only the data rate conversion that is the function of
The point is that time extension of -Y and BY is also performed. This can be realized by setting the rate of the above-mentioned NTSC system read clock to 1/4 for the color difference signal. That is, the NTSC system read clock of the luminance signal is the same ck as the embodiment of FIG.
n, and the NTSC system read clock of the color difference signal is supplied from the NTSC system clock generation circuit 8 as ckc having a rate of 1/4 thereof.

The luminance signal Y converted to the NTSC data rate and the TCI-decoded color difference signals RY and BY by the above configuration and operation are respectively NTSC.
The signal is input to the signal processing circuit 12, and the same processing as described in the embodiment of FIG. 1 is performed.

FIG. 10 is a block diagram showing a specific example of the vertical filter 90 shown in FIG. 10, the same components as those in FIG. 8 are designated by the same reference numerals. In addition, 93 is a data separation conversion circuit, and 94 and 95 are output terminals.

This specific example is different from the specific example shown in FIG.
The color difference signal output processing unit. That is, in FIG.
The data separation conversion circuit 93 receives the color difference signal R from the adder 56.
-Y and BY are alternately input for each line, and the adder 57
Similarly, the color difference signals RY and BY are alternately input line by line, and the input color difference signals are separated into color difference signals RY and color difference signals BY. , And output to the output terminals 94 and 95 in parallel. The data separation conversion processing operation by the data separation conversion circuit 93 is performed by the control signal from the control circuit 67.

The change in the data structure of the video signal in such signal processing is shown in (*) of FIG. That is, FIG.
In (*), the vertical filter 5 performs scanning line conversion,
A line-sequential / dot-sequential decoding process is also performed together with the sub-sample returning process, and the color difference signals R-Y, B along with the luminance signal Y are performed.
It shows that -Y is output in parallel.

In the present embodiment, the time extension of the color difference signal is performed in the time axis conversion circuit 92, but this processing may be performed by the vertical filter 90. In that case, the color difference signal in FIG. A time extension function may be added to the data separation conversion circuit 93. That is, the vertical filter 90 can be provided with a TCI decoding function for color signals.

[0067]

According to the present invention, in the vertical filter for performing the scanning line conversion, the sub-sample returning processing of the MUSE signal and the processing relating to the TCI decoding processing of the color difference signals, which are necessary for the MUSE / NTSC conversion processing, are performed by the vertical filter. By doing this together, the digital circuit and the like can be shared, the block for performing the sub-sample returning process and the block for performing the TCI decoding process are not required, and the circuit components can be reduced, the circuit scale can be reduced, and the cost can be reduced. be able to.

Further, the vertical filter is also used in the vertical direction, so that the line memory and the digital circuit can be shared, and the circuit components can be reduced, and the contour portion is blurred by the contour enhancement of the image. Can be reduced and high image quality can be realized.

[Brief description of drawings]

FIG. 1 shows MUSE / NTSC as an embodiment of the present invention.
It is a block diagram which shows a converter.

FIG. 2 is a block diagram showing a specific example of the vertical filter 5 of FIG.

3 is an explanatory diagram for explaining scanning line conversion in the vertical filter 5 in FIG.

FIG. 4 is a block diagram showing a specific example of the variable coefficient data converter 35 of FIG.

5 is an explanatory diagram for explaining a sub-sample returning process performed by the variable coefficient data converter 35 of FIG.

6 is a circuit diagram showing a specific example of the dot-sequential decoder 11 of FIG.

7 is an explanatory diagram for explaining a change in a data structure of a video signal in each signal processing by the MUSE / NTSC converter of FIG.

FIG. 8 is a block diagram showing another specific example of the vertical filter 5 of FIG.

FIG. 9 shows MUSE / NTS as another embodiment of the present invention.
It is a block diagram which shows a C converter.

10 is a block diagram showing a specific example of the vertical filter 90 of FIG.

[Explanation of symbols]

 3 ... MUSE signal processing circuit 4 ... MUSE system clock generation circuit 5, 90 ... Vertical filter 6, 91 ... Horizontal filter 7, 92 ... Time axis conversion circuit 8 ... NTSC system clock generation circuit 9 ... NTSC system processing circuit 10 ... Expansion circuit 11 ... Point-sequential decoder 58 ... Multiplexer 93 ... Data separation / conversion circuit

Claims (6)

[Claims] 1. A MUSE signal processing means for inputting a received MUSE video signal (hereinafter referred to as a MUSE signal), performing an input processing as a preprocessing and a synchronization detection processing, and outputting the MUSE signal processing means and the MUSE signal processing means. A vertical filter for inputting the output signal, converting the number of scanning lines of the MUSE system to the number of scanning lines of the NTSC system, and outputting the result.
The signal output from the vertical filter is input, and MUSE is input.
A time axis conversion means for performing data rate conversion from a system data rate to an NTSC system data rate and outputting the same, and a signal output from the time axis conversion means are input, and an NTSC format signal is created from the signal. Output as NT
SC system processing means, and the received MUS
In a MUSE / NTSC converter for converting an E signal into an NTSC video signal (hereinafter referred to as an NTSC signal) and outputting the same, the vertical filter is provided with sub-sample returning processing means and line-sequential decoding processing means. Said MUS
Based on the sub-sampled phase signal contained in the E signal,
By the sub-sample returning processing means, a non-transmitted non-sample point existing between the transmitted sample point and the sample point in the signal input to the vertical filter is interpolated at a predetermined level. Of the signals input to the vertical filter by the line-sequential decoding processing means, the line-sequential color signals are converted into dot-sequential color signals, and the NTSC system processing means performs dot-sequential decoding. A processing means is provided, and the dot-sequential decoding processing means allows the NTSC
Among the signals input to the system processing means, a dot-sequential color signal is separated into two color difference signals.
E / NTSC converter. 2. A MUSE signal processing means for inputting a received MUSE video signal (hereinafter referred to as MUSE signal), performing an input processing as a preprocessing and a synchronization detection processing, and outputting the MUSE signal processing means and the MUSE signal processing means. A vertical filter for inputting the output signal, converting the number of scanning lines of the MUSE system to the number of scanning lines of the NTSC system, and outputting the result.
The signal output from the vertical filter is input, and MUSE is input.
A time axis conversion means for performing data rate conversion from a system data rate to an NTSC system data rate and outputting the same, and a signal output from the time axis conversion means are input, and an NTSC format signal is created from the signal. Output as NT
SC system processing means, and the received MUS
In a MUSE / NTSC converter for converting an E signal into an NTSC video signal (hereinafter referred to as an NTSC signal) and outputting the same, the vertical filter includes a sub-sample returning processing means and a line-sequential / point-sequential decoding processing means. The sub-sampling processing means is provided, and based on the sub-sampling phase signal included in the received MUSE signal, the sub-sampling processing unit divides between the transmitted sampling points and sampling points in the signal input to the vertical filter. Interpolation signals of a predetermined level are inserted into non-transmitted non-sampling points existing in between, and the line-sequential / point-sequential decoding processing means selects line-sequential signals from the signals input to the vertical filter. The MUSE / NTSC converter, which converts the color signal of the above into two color difference signals. 3. The MUSE / N according to claim 1 or 2.
In the TSC converter, the vertical filter includes a data converter that multiplies a signal in the vertical filter by a predetermined coefficient to convert the level of the signal, and the data converter includes scanning line conversion that performs the scanning line conversion. A MUSE / NTSC converter, which is shared by the means and the sub-sample returning processing means. 4. The MUSE according to claim 1, 2, or 3.
In the / NTSC converter, the NTSC system processing means or the time axis conversion means is provided with a decompression means, and the decompression means converts the color signal among the signals input to the NTSC system processing means or the time axis conversion means to 4 MUSE / NTSC converter characterized by doubling the time extension. 5. The MU according to claim 1, 2, 3 or 4.
In the SE / NTSC converter, the vertical filter is provided with an enhancing means, and the enhancing means
A MUSE / NTSC converter, wherein a high-frequency component is extracted from the signal input to the vertical filter, and a signal whose contour is emphasized is created using the high-frequency component. 6. The MUSE / NTSC converter according to claim 5, wherein the enhancing means includes a plurality of cascaded delay memories that sequentially delay the signal input to the vertical filter, and each of the delay memories. An MU, which comprises a plurality of level converting means for multiplying an input signal or an output signal by a predetermined coefficient and outputting the result, and an adding means for adding the signals output from the level converting means.
SE / NTSC converter.