JPH0292186A - Television signal converter - Google Patents

Abstract

PURPOSE:To suppress the increase of the frequencies of a resampling clock for an interpolation processing and to facilitate an LSI-operation by constituting a system signal route so as to convert an aspect ratio. CONSTITUTION:A digitized signal is inputted to an aspect converter 22 on a next stage, and a standard television signal is obtained here. The output signal of the aspect converter 22 executes the interpolation processings in the same field commonly for a luminance signal and a color difference signal, and the number of scanning lines is inputted to a filter 23, which arranges the number to that of the standard television signal. A delay part 23a of the filter device 23 successively delays the input signals by one horizontal period, obtains the plural television signals, a selector part 23b selects arbitrary two of the plural television signals, an adder part 23c executes primary to tertiary adding processings, a selector part 23d inputs the standard television signal and the respective signals from the primary to tertiary adding processings, and selects and derives any one of them. Thus, a circuit size can be made smaller and LIS-operated.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention is a method for converting a high-definition television signal having a greater number of scanning lines and an aspect ratio than a standard television signal into a standard television signal. The present invention relates to a television signal conversion device.

(Prior Art) As a high-definition television signal, TC has a greater number of scanning lines and an aspect ratio than a standard television signal, and has two color difference signals line-sequential using the dot interlace method.
There are some that are encoded using the I method.

FIG. 8 shows a television signal converter for converting the high-definition television signal into a standard television signal.

A high-definition television signal is input to an analog-to-digital (hereinafter referred to as A/D) converter 11 via an input terminal 10 and converted into a digital signal. The input pattern of the luminance signal is dot interlaced, for example, as shown in FIG. 9(a). The solid line is the scanning line of the first field, and the position of the * mark is the subsample phase position of the luminance signal. Further, the dotted line is the second field, and the position of the black mark is the subsample phase position of the luminance signal. This signal is input to the intra-field interpolation device 12, and interpolation processing using upper, lower, left, and right data is performed. This results in a dot pattern signal as shown in FIG. 9(b). At this time, the number of pigs is doubled due to field interpolation, so if the sampling clock rate of the A/D converter 11 is a, then
The clock rate 1 of the interpolated output data is also doubled 2a
becomes.

Next, the interpolated data is input to the scanning line conversion device 13, where the 1125 lines/6011z, 2:1 signal is converted into a 525 lines/60 Hz, 1:1 interlaced signal. Further, this signal is input to the aspect conversion device 14 and is converted from an aspect ratio of 5:3 to 4=3. In the aspect conversion device 14, in order to perform the above conversion, the number of samples of the human input signal in the IH (horizontal period) is 9t3 (in the case of 1 sample, it is multiplied by 3/4 to 720 samples).

Therefore, the clock rate of the data output from this conversion device 14 is also 2 a X (3/4) = (3/
2) It becomes a.

Next, the output signal of the aspect conversion device 14 is input to the time axis conversion device 15 . The time axis conversion device 15 is 11
It converts one horizontal scanning time of 25 lines/BOHz, 2:1 signal into the horizontal time of 525 lines/BOHz, 1:1 signal, and this process is performed for both luminance signals and color difference signals. be exposed.

Here, the luminance signal Y and color difference signal C are further separated, and the luminance signal is input to the D/A converter 16 and converted into an analog signal. On the other hand, the color difference signal C is input to the color signal processing device 17 and subjected to TCI decoding and expansion. That is, the color difference signal is time-compressed during the horizontal blanking period of the luminance signal, compressed to, for example, 1/4, and multiplexed, and the (RY) signal and the (B-Y) signal are line-sequential. Decode this to find it. As shown in FIG. 10, the color difference signal C is expanded four times by the expansion device 17a, and further expanded by the TCI decoding device 17b (R
-Y) signals and (B-Y) signals that are not present on the current line are interpolated using the upper and lower lines, and the two color difference signals are made simultaneous.

Then, the (RY) signal and (B-Y) signal are each D
The signal is input to /A converters 18a and 18b and becomes an analog signal.

As described above, a television signal of 525 lines/BO1lz, 1:1 interlace, and aspect ratio of 4:3 is obtained. 1125125 main line television signal and 5
A synchronization signal for the 25-line television signal is generated in a synchronization signal generator 19, and the system and both signals are synchronized.

(Problems to be Solved by the Invention) In the above conversion system, the field interpolation processing device generally requires a digital filter having a large number of taps in order to perform processing in the horizontal and vertical directions. Also, in the scanning line number conversion device, a digital filter having a large number of taps and performing processing in the vertical direction is required.

For this reason, the scale of the hardware has become extremely large.

Furthermore, since the clock rate of the output signal after field interpolation processing is twice the clock rate of the input signal before interpolation processing, if interpolation is performed before time axis conversion,
The write clock frequency of the memory for time axis conversion becomes a high frequency. Therefore, it is necessary to use a memory that can operate at high speed or to perform serial-to-parallel conversion, which poses the problem of substantially increasing the memory capacity.

Furthermore, the circuit between the interpolation processing section and the memory is also required to operate at high speed, and when integrated into an LSI, the operation becomes difficult and the hardware scale increases.

In addition, as mentioned above, processing such as aspect ratio conversion, time axis conversion, and intra-field interpolation processing.

When color expansion processing is performed, several types of clocks are required, which poses a problem in that the synchronization circuit becomes extremely complex.

Therefore, this invention: ■ By performing time axis processing (aspect ratio conversion) first, the frequency of the sample clock for interpolation processing is suppressed from increasing, and the memory capacity used in the subsequent stage is prevented from increasing. It is an object of the present invention to provide a television signal conversion device that alleviates the need for high-speed operation circuits and is effective for reducing the circuit scale and implementing LSI.

■Furthermore, this invention realizes a circuit with a simple configuration that can simultaneously perform intra-field interpolation processing and conversion of the number of scanning lines, and can also commonly perform interpolation and scanning line conversion for luminance signals and color difference signals. It is an object of the present invention to provide a television signal conversion device that can significantly reduce the hardware scale.

■Also, by performing time axis processing (aspect ratio conversion) first, this invention suppresses the increase in the frequency of the sample clock for interpolation processing, prevents an increase in the memory capacity used in the subsequent stage, and This TV reduces the need for high-speed operation circuits, reduces the frequency of memory control clocks in the color signal processing section, prevents complication of synchronous circuits, and is effective in reducing circuit scale and implementing LSI. The purpose of the present invention is to provide a signal conversion device.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a TC1 signal having a larger number of scanning lines and a wider aspect ratio than a standard television signal, and in which two color difference signals are line-sequential using a dot interlace method. A device for converting a high-definition television signal encoded by a method into a standard television signal, comprising an aspect conversion means for converting the high-definition television signal into an aspect ratio of the standard television signal, and a signal from the aspect conversion means. is supplied, and this signal is used to perform interpolation processing for both the luminance signal and the chrominance signal within the same field.

filter means for converting the number of scanning lines into the number of scanning lines of a standard television signal;
a time axis conversion means for converting a horizontal scanning time into one horizontal scanning time of a standard television; and a time axis conversion means for converting the output color difference signal from the filter means from line sequential to sequential scanning, and decompressing the signal within the scanning line. The color signal processing means converts a standard television signal into one horizontal scanning time, and converts a high-definition television signal into a standard television signal.

(Function) By using the above method, since the aspect ratio is converted first, time leeway is obtained, and the clock rate of data processing from the next stage can be lowered. It is possible to suppress the increase in clock rate frequency. Further, this makes it easy to perform intra-field interpolation processing and scanning line number conversion simultaneously and for the luminance signal and one color signal in common, and the filter means for performing this can also be implemented using hardware with a small circuit scale. Further, since the clock rate of the subsequent stage circuit is low, it can be realized with a small capacity memory.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. It has more scanning lines and aspect ratio than a standard television signal (e.g. NTSC television signal), and has two color difference signals (e.g. (R-Y) signal and (B
-Y) signal) is line-sequential, and a high-definition television signal (for example, a MUSE television signal) encoded by the TC1 system is input to the A/D converter 21 via the input terminal 20 and converted into a digital signal. converted.

Here, the δ sampling clock Φ1 is, for example, Φ1 =
l[i, 2MHz.

The digitized signal is sent to the next stage aspect converter 2.
2 is input. Here, the number of scanning lines is 1125, the field frequency is 80 Hz, 2:1 interlace,
A high-definition television signal with an aspect ratio of 5:3 is
As shown in the figure, processing is performed to delete the shaded portion of the image signal. As a result, a semi-standard television signal with 525 scanning lines, 60 Hz field frequency, 1:1 interlace, and 4:3 aspect ratio is obtained. Here, when the aspect conversion device 22 outputs the extracted signal, for example, if the number of samples in one horizontal period of a high-quality system is 480 samples, 15% of this inner side
output at a data rate of 360 samples.

Therefore, this aspect conversion device 22 has Φl =1[
i, capture the input signal with a 2 MHz clock, for example Φ2 = 12.15 MHz (16,2 MHz
Signal output is performed with a clock of (3f30)/(480)).

The output signal of the aspect conversion device 22 is input to a filter device 23 that performs interpolation processing within the same field for both luminance signals and color difference signals, and adjusts the number of scanning lines to the number of scanning lines of a standard television signal. .

This filter device 23 includes a delay section 23a, a selector section 23b, an adder section 23c, and a selector section 23d.

The delay unit 23a sequentially delays the input signal by one horizontal period to obtain a plurality of television signals. The selector unit 23b selects and derives any two of the plurality of televisions. The adder 2'3c includes a primary addition processor that adds the two television signals, an interpolated television signal obtained by the primary addition processor, and the selected television signal selected by the selector 23b. and a tertiary addition processing section that further adds the outputs of the secondary addition processing section and the primary addition processing section. The selector section 23d selects a reference television signal (signal of tap M) located in the middle in the time axis direction among the plurality of television signals obtained from the delay section 23a, and each of the signals from the first to third addition processing sections. The signals are input, and one of them is selected and derived.

That is, the delay unit 23a connects the line memories 31 to 34 in series, and the input side and output side signals of the line memory 31 are supplied to the selector 35, and the input side and output side signals of the line memory 34 are supplied to the selector 35. The signal is supplied to the selector 36. The intermediate tap M (output of the line memory 32) is the selector 41
is supplied to

Next, the signals selected by selectors 35 and 36 are supplied to selector 37 and also to adder 38,
Primary addition processing is performed. The output of this adder 38 is input to an adder 39 and added to the signal selected by the selector 37 (
(quadratic addition).

Further, the addition output of the adder 39 is input to an adder 40 and added to the output of the adder 38 (cubic addition).

The selector 41 also receives addition outputs from the adders 38, 39, and 40. Note that each adder adds the input signals, halves the result, and outputs the result.

FIG. 3 is shown to explain the filtering function of the above circuit.

Assume now that the sample pattern of the input signal is that of a high-definition television signal that has been dot sampled as shown in FIG. Figure 3(a) shows the luminance signal; Figure 3(a) shows the luminance signal;
b) is a color difference signal according to the TC1 method which is compressed to 1/4 and multiplexed within the horizontal synchronization period.

In the figure, the solid line is the first field, and the broken line is the line for the second field. In Figure 3(b), the Q mark and
-Y) Signal In is the (B-Y) signal, and the (R-Y) signal and (B-Y) signal are line sequential.

The selectors 35 and 36 are supplied with a control signal S1 generated by a timing generation circuit 45, the selector 37 is supplied with a control signal S2 from the same circuit, and the selector 41 is supplied with a control signal S3 of the same circuit. ing.

Here, Xl on the line No. 4 in FIG.
If we interpolate (vertical interpolation) the data of , it is obtained by addition processing using the data of the upper line No. 3 and the lower line No. 5 of the same field from the luminance signal pattern of Fig. 3 (a). be able to.

However, since the color difference signals in FIG. 3(b) are line sequential, it is not possible to immediately use the signal of the upper limit line. Therefore, line No. 2, which is two lines away,
The data of line N006 will be used to interpolate the data of X2.

Therefore, if we now assume that the signal here is the previous line No. 4 with the intermediate tap M in FIG.
The signal on the input side of corresponds to line NO36. Therefore,
In order to obtain an interpolated signal at the position X2 of line N014 in FIG.
If the signal on the output side of the line memory 34 corresponding to O, 2 is taken into the adder 38 via the selector 36, and the added output is taken out from the selector 41, an interpolated signal at the position X2 of line N014 can be obtained. This processing system is common when processing color difference signals, so for example, when the control signal S1 is at a high level, the selectors 35 and 36
should make the above selection.

On the other hand, when interpolating the luminance signal in FIG. 3(a), the control signal S1 is set to low level and the line N01
If the signals corresponding to the upper and lower sides of 4, that is, the outputs of line memory 33 and 32 are selected and led to adder 38, Xl
An interpolated signal can be obtained. Then, the selector 41 may be controlled by the control signal C to select the interpolation signal, and the incoming signal may be selected by the selector 41 at the next clock.

Next, when the second field signal shown by the broken line has arrived, if you want to interpolate data to the position of line No. 4, X3 of the first field shown by the solid line, first interpolate from the upper and lower lines. It is sufficient to generate a signal and perform interpolation processing between this interpolated signal and the signal of the adjacent line. This interpolated signal can be obtained from adder 39.

Also, in the second field, when obtaining an interpolated signal at the position data, add this first data to the data of the adjacent line, and then add the second data obtained as a result to the previous first data, then an interpolated signal is placed at the position of X4. Obtainable. This interpolated signal is sent to the adder 4
It can be obtained from 0.

As mentioned above, in order to obtain an interpolated signal, the selector must be selected depending on the conversion method, the multiplexing position of the luminance signal and chrominance signal, the odd field, the even field, the subsampling phase of the luminance signal, and the subsampling phase of the chrominance signal. 35
, 36, 37. 41 need to make appropriate data selections. To that end, each selector 35, 36, 37.41
are controlled by control signals SL, S2, and S3 from the timing generation circuit 45, respectively. The timing generation circuit 45 generates a luminance signal/color difference signal multiple position identification signal A.
, odd/even field identification signal B, luminance signal sub-sample phase identification signal 01, color difference signal signal sub-sample phase identification signal 1, the control signals Sl, S2, and S3 are generated. In the case of a high-definition television signal, as shown in Figure 4, the luminance signal and color difference signal are transmitted in a time-divided manner in the horizontal direction, so the identification signal A is used to identify this time position. Ru.

The signal derived from the selector 41 as described above is sent to the luminance signal time axis conversion circuit 24 and the horizontal low-pass filter 2.
3e.

The horizontal low-pass filter 23e includes a latch circuit 42° adder 4
3. It is constituted by a selector 44 and performs time alignment of color difference signals. That is, as shown in FIG. 3(b),
There is no problem when creating an interpolation signal at the position of X2 in the first field indicated by the solid line, but when creating an interpolation signal at the position indicated by the solid line in the second field indicated by the broken line, as shown at the position X4, there is no problem. It will be created at a position different from the sampling data position. Therefore, this data such as X4 is further processed and shifted in the horizontal direction so that it matches accurately with the sampling data position of the solid line. Therefore, selector 44 is controlled by odd/even field identification signal B.

The output of the selector 44 is supplied to the color signal processing circuit 26. The color signal processing circuit 26 receives (R-
The color difference signals of Y) and (B-Y) are as shown in FIG.
Since it is line sequential, this circuit converts it to sequential scanning and also performs time axis conversion.

In the color signal processing circuit 26, the line memory 50.51
．． Adder 52 constitutes a vertical filter. As for the input signal, for example, only the (B-Y) signal is transmitted on the line NO, 2 in Fig. 5, and the (RY) signal is interpolated using the pigs on the upper and lower lines NO, 1, NO, 3. I will do it. In line No. 3, the (RY) signal is used as is, and the (B-Y) signal is interpolated using the upper and lower lines.

An interpolated signal is obtained from adder 52. For example, line No. 12 in FIG. 5 is located at the output section of the line memory 50,
Assuming that it is a reference, an interpolated signal of (R, -Y) is obtained from the adder 52. The selector 54 supplies the (RY) signal to the time axis conversion and expansion circuit 54 and the (BY) signal to the time axis conversion and expansion circuit 55 . Next, when the signal on line N013 becomes the reference, the (RY) signal is obtained at the output of line memory 50, and from adder 52,
An interpolated signal of (B-Y) is obtained. Here selector 53
supplies the (RY) signal to the time axis conversion and expansion circuit 54, and supplies the (B-Y) signal to the time axis conversion and expansion circuit 55. Therefore, the selector 53 can switch the transfer destination of the two-person transfer every horizontal period by the signal E.

In the time axis conversion and expansion circuits 54 and 55, for example, a memory of approximately 14 Kbit is used, and the frequency of the input data write clock Φ3 is 24.3 M)Iz,
The frequency of read clock Φ5 is 5.67 MHz.

As a result, the color difference signals for one horizontal scanning time, which have been compressed to a 1/4 time axis for high-definition television signals, are each expanded to one horizontal scanning time of a standard television signal. Each expanded (RY) signal and (B-Y)
The signals are derived by being converted into analog (RY) and (B-Y) signals input to the D/A converters 27a and 27b, respectively.

On the other hand, in the time axis conversion circuit 24 of the luminance signal processing path, processing is performed to convert one horizontal scanning time of a high-quality television signal into one horizontal time of a standard television signal. In this example, the input data has a frequency of 24.3 M
It is once written to approximately 100Kbit memory by the clock Φ3 of Hz, and then written to the memory of approximately 100Kbit by the clock Φ3 of frequency 22.68MHz.
4. As a result, 525/6011
z, 1:1 interlace, aspect ratio 4;3
standard television signal.

Furthermore, the time axis conversion circuit 24 simultaneously has 525 lines/60H.
It is also possible to convert a 1:1 interlaced signal into a 2:1 interlaced signal.

That is, 525 lines/BOHz, 1:1 interlaced signal is written every other line and by changing the vertical position every field without thinning out, and read out at a frequency of clock Φ4 = 11.34 MHz. This can be achieved by Conversion to 2,1 interlace can also be performed in the color signal processing circuit 26 in the same way.

FIG. 6 shows another embodiment of the invention. Components having the same functions as those in the previous embodiment are designated by the same reference numerals as in FIG. In this embodiment, in the color difference signal processing path, the output from the selector 44 of the fill device 23 is first input to the time axis conversion and expansion circuit 60. In the time axis conversion and expansion circuit 60, the frequency is 24.3MH.
Input data is taken in at clock Φ3 of Z, and read out at clock Φ5 of frequency 51 (2).This allows expansion of the color difference signal to the line and conversion of the standard television signal to one horizontal scanning time at the same time. In this way, a 1125 lines/80Hz, 1:1 interlace signal can be converted to either a 525 lines/60 degrees, 1:1 interlace signal or a 525 lines/60Hz, 2:1 interlace signal. The thus-converted multiple color difference signal is converted into sequential scanning in the vertical filter section and the selector 53 as in the previous embodiment, and each (RY) signal of the selector 53, (B-Y)
The signals are fed directly to A/D converters 27a and 27b, respectively.

FIG. 7 shows yet another embodiment of the invention. In this embodiment, when converting the aspect ratio in the aspect conversion device 22, approximately 70 Kbit memory is used, the writing frequency is 18.2NH4, and the reading frequency is 11.
．． The frequency shall be 84MHz. Soshite 1125 pieces/60H2,2
: 1 interlaced signal with an aspect ratio of 5:3,
Delete the top and bottom lines to 1050 lines/130Hz, 2
: Convert to 1 interlaced signal, delete about 15% on both sides (horizontal direction), and write to memory. Then, the read signal whose aspect ratio has been converted to 423 is subjected to the same processing as before in the filter device 23. Therefore, if the output (luminance signal) of the filter device 23 is subjected to interlace conversion in the interlace conversion device 71,
525 lines/8011z, 2:1 interlace,
A standard television signal with an aspect ratio of 4:3 can be obtained. Also, regarding the color difference signal, line sequential is converted to sequential scanning as before, and the (R-Y) signal and (B-Y)
and the interlace conversion and decompression circuit 72, respectively.
．． By processing at 73, a color signal can be obtained in a standard television signal.

The synchronization generating circuit 80 in FIG. 1 synchronizes the internal system clock with the input television signal according to the control signal of the high-definition television, and also generates the basic clock of the standard television signal to be output. The input and output televisions are synchronized.

[Effects of the Invention] As explained above, according to the present invention, the signal path of the system first converts the aspect ratio.

For this reason, it is possible to suppress the frequency of the sample clock for subsequent interpolation processing from increasing. This does not cause an increase in hardware scale due to a high clock rate, and can be easily integrated into an LSI.

Next, the fill device that performs interpolation processing of the signal after aspect ratio conversion processes the luminance signal and color difference signal in common, and converts the scanning line by combining the delay section, selector section, addition section, and timing signal generation circuit. A configuration that can perform this has been realized using simple hardware. Furthermore, since the configuration that performs this scanning line conversion process is realized by interpolating high-quality lines without thinning them out, there is little loss of information and little decrease in vertical resolution.

Furthermore, in color difference signal processing, time axis conversion and expansion are performed simultaneously, which is effective in reducing hardware requirements.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation of the aspect conversion device shown in FIG. 1, and FIG. 3 is an illustration showing the operation of the device shown in FIG. 4 is an explanatory diagram shown to explain the position of a color difference signal compressed in the time axis, and FIG. 5 is an explanatory diagram shown to explain the line sequential state of the color difference signal. FIGS. 6 and 7 are circuit diagrams showing other embodiments of the present invention, FIG. 8 is a block diagram showing a conventional television signal converter, and FIG. 9 is a high-definition television signal converter. FIG. 10 is a block diagram showing the color signal processing circuit of FIG. 8. 21... A/D converter, 22... Aspect conversion device, 23... Filter device, 23a... Delay unit, 3
2b, 23d...Selector section, 23c...Addition section,
23e... Horizontal low-pass filter, 24... Time axis conversion circuit, 25. 27 a, 27 b--A/D converter, 26... color signal processing circuit. Applicant's agent Patent attorney Takehiko Suzue0 Φ z z

Claims (1)

[Claims] (1) A high-definition television encoded using the TCI method, which has a greater number of scanning lines and a wider aspect ratio than a standard television signal, and in which two color difference signals are line-sequential using the dot interlaced method. A device for converting a signal into a standard television signal, comprising: aspect conversion means for converting the high-definition television signal into an aspect ratio of a standard television signal; and a signal from the aspect conversion means is supplied, and the apparatus comprises: A filter means that performs interpolation processing on both the luminance signal and the color signal within the same field and also converts the number of scanning lines into the number of scanning lines of a standard television signal, and one horizontal scanning time of the output luminance signal of this filter means. time axis converting means for converting into one horizontal scanning time of a standard television signal, and converting the output color difference signal from the filter means from line sequential to sequential scanning and decompression processing to convert the scanning line time into one horizontal scanning time of a standard television signal. 1. A television signal conversion device comprising: color signal processing means for converting into horizontal scanning time. (2) The filter means includes a delay means for obtaining a plurality of television signals by sequentially delaying the input television signal to the means by one horizontal period; a first selector means capable of selectively deriving a selected television signal as a selected television signal; a primary addition processing section for adding two selected television signals from the selector means; and an interpolated television signal obtained by the first addition processing section. a secondary addition processing section that adds the signal and any one selected television signal selected by the selector means; an addition means having a tertiary addition processing section for further adding the interpolated television signals; and a reference television signal located in the middle in the time axis direction among the plurality of television signals obtained from the delay means; A second selector means receives each of the interpolated television signals from the tertiary addition processing section and selects and derives one of the interpolated television signals; At least a multiplexed position identification signal indicating the time of arrival, a sub-sampled phase identification signal of the luminance signal, a sub-sampled phase identification signal of the chrominance signal, and a field identification signal indicating the odd field and even field of the input television signal are input, and timing generating means for obtaining a control signal for determining the signal to be selected by the first and second selector means based on the signal and supplying it to the control terminals of the first and second selector means. The television signal conversion device according to claim 1, characterized in that: (3) The time axis converting means converts the luminance signal from the filtering means into one horizontal scanning time of the standard television signal, and at the same time converts the 1:1 interlaced standard television signal into the 2:1 interlaced standard television signal. 2. The television signal conversion device according to claim 1, wherein the television signal conversion device is configured to perform the following. (4) The color signal processing means first expands the output color difference signal from the filter means, converts the signal within the scan into one horizontal scanning time of a standard television signal, and then converts the signal within the scanning into one horizontal scanning time of a standard television signal, and then converts the signal within the scanning into one horizontal scanning time of a standard television signal. 2. The television signal converting device according to claim 1, wherein said television signal converting device is configured to convert into one horizontal scanning time of a standard television signal.