JPH06233324A - Down converter device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of a down converter device by using the clock selected by a selector means as a reading clock of a time base conversion memory which converts the TV signal rate of high precision into a standard TV signal rate. CONSTITUTION:In regard of a color difference signal, the TV signal rate of high precision is converted into a standard TV signal rate by a FIFO memory of a color expanding circuit 13 and then supplied to a line sequential decoding part 10. The part 10 consists of the line memories 14 and 15, an adder 16, and a selector circuit 17 and interpolates a color difference signal in the vertical direction. This interpolated color difference signal is supplied to a blanking circuit 18. The circuit 18 blanks a luminance signal Y and two types of color difference signals R-Y and B-Y at each part including a color difference signal period when these signals are read out of a time base conversion memory 12. Then the blanked signals are supplied to the D/A converters 19, 20 and 21 which supply these luminance and color difference signals to an NTSC encoder which converts these signals into the analog signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a down converter for converting a high definition television system signal into a standard television system signal.

[0002]

2. Description of the Related Art As a method of band-compressing a high-definition television signal for transmission, NHK (Japan Broadcasting Corporation) has issued a MUSE (multiple sub-nyquist).
A sampling encoding method has been proposed, and experimental broadcasting using this method has been conducted. MUS
The E method has 1125 scanning lines and color difference signals RY and B
As for -Y, as shown in FIG. 6, it is time-division multiplexed as a line-sequential signal in the blanking period of the video signal. Less than,
A case where a high definition television signal in which the luminance signal Y and the color difference signals RY and BY are time division multiplexed is converted into a standard television signal will be described. As shown in FIG. 7, 1032 effective scanning lines of high-definition television signals are decimated in half so as to be line-sequential signals while being time-division-multiplexed, and 480 of the 516 decimated lines are standard. FIG. 1 shows the case of using as an effective scanning line of a television signal.
0 and the conventional example shown in FIG. 11 will be described.

In FIG. 10, the MUSE signal is supplied to the input terminal 1, the analog signal is converted by the A / D converter 2 into a digital signal having a clock frequency of 16.2 MHz, and then supplied to the MUSE processing circuit 3. MUS
The E processing circuit 3 performs de-emphasis and field interpolation processing on the digital signal supplied from the A / D converter 2, and supplies it to the vertical filter 11 at a data rate of a clock frequency of 32.4 MHz. At the same time, the sync signal is separated and supplied to the memory control circuit 9 and the 1125 system clock generation circuit 4.

The vertical filter 11 attenuates a component of the video signal output from the MUSE processing circuit 3 which is folded back during thinning of scanning lines, and supplies the attenuated component to the time base conversion memory 30. On the other hand, in the 1125 system clock generation circuit 4, 32.4 MHz and 16.
A 1MHz system clock of 2 MHz is created and supplied to the 525 system clock generation circuit 5, the memory control circuit 9, the time axis conversion memory 30 and necessary parts.

In the 525-system clock generation circuit 5, a 525-system clock is generated from the 1125-system clock by a PLL, and the 525-system clock is divided by the frequency divider circuit 6, the color expansion circuit 31, the memory control circuit 9, and the time axis conversion memory. 30 and necessary parts are supplied. The memory control circuit 9 writes the video signal from the vertical filter 11 into the time-axis conversion memory 30 by thinning out only half of the video signal of the color difference signals RY and BY and the luminance signal Y in the vertical direction. As shown in FIG. 8A, a write enable signal as shown in FIG.
Supply to 0.

In the time axis conversion memory 30, the video signal written at the 1125 system clock according to the write enable signal is read at the 525 system clock to convert the high definition television signal rate to the standard television signal rate. , Blanking circuit 18 and color expansion circuit 31. Since the color difference signals R-Y and B-Y and the luminance signal Y are serially read from the time base conversion memory 30, the 525-system clock frequency is the color difference signal R.
When the sample numbers of −Y and BY and the luminance signal Y are 188 and 748, respectively, as shown in FIG. 9A, the sum of the sample numbers is multiplied by the horizontal frequency to obtain 936 fh (14.7 MH).
z) (fh is the horizontal frequency).

The color expansion circuit 31 is constructed by using a FIFO memory in which writing and reading are asynchronous, and only the color difference signals RY and BY are written in the memory at the time of writing by the 525 system clock, and the frequency dividing circuit at the time of reading. 6 in 4
The clock divided by 1 is read from the memory at the same time as the luminance signal Y, so that the color is expanded four times and is supplied to the line-sequential decoding unit 10.

The line-sequential decoding unit 10 includes a line memory 1
4 and 15, an adder 16 and a selector circuit 17, which interpolates the color difference signals RY and BY in the vertical direction and supplies them to a blanking circuit 18. The blanking circuit 18 has a luminance signal Y and two color difference signals R-Y and B-Y.
Of the color difference signal period at the time of reading from the time base conversion memory 30, the blanking is performed and the blanked portion is supplied to the D / A converters 19, 20, and 21. D / A converter 1
9, 20, and 21, the luminance signal Y and the two types of color difference signals R-
Y and BY are converted into analog signals and are supplied to the NTSC encoder, though omitted in FIG.

In this conventional example, the luminance signal Y and the color difference signal R-
Time axis conversion memory 3 while Y and BY are time-division multiplexed
The configuration is such that the time axis conversion memory needs only one system, but on the other hand, the color difference signal period of the time axis conversion memory output becomes blanking as shown in FIG. Is 80% of the total horizontal period, NT
It is less than about 83.5% of the SC standard. In order to avoid this problem, there is also a method of providing two systems of time axis conversion memories 32 and 33 for the luminance signal and the color difference signal as shown in FIG. 11 and performing time axis conversion of the luminance signal and the color difference signal separately. In FIG. 9, the portions corresponding to those in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted.

[0010]

In the above-mentioned conventional apparatus, as described above, there is a possibility that a horizontal video period is insufficient with respect to the NTSC standard, a blanking portion may appear in a horizontal corner of the screen, and color difference may occur. Since the scanning lines are thinned while the signals are line-sequentially time-division-multiplexed, there is a problem that the vertical resolution of the color becomes one half of the NTSC standard. Further, in order to prevent the blanking part from being displayed in the horizontal corner of the screen, the time axis conversion memory provided separately for the luminance signal and the color difference signal requires an extra large time axis conversion memory, There was a problem of high cost.

[0011]

In order to solve the above problems, the present invention provides a high-definition television system clock in a down converter for converting a high-definition television system signal into a standard television system signal. Clock generating means for generating a standard television system clock, second clock generating means for generating a standard television system clock, and third clock generating means for generating a clock having a frequency higher than the standard television system clock. Time axis conversion memory means for converting the time axis of the high definition television system signal by writing the high definition television system signal with the high definition television system clock and changing the clock frequency at the time of reading And the standard television system clock for reading the luminance signal written in the time axis conversion memory means A selector for selectively outputting the clock from the third clock generator for reading the color difference signal, and the clock selected by the selector is changed from a high definition television signal rate to a standard television signal rate. It is used as the read clock of the time-axis conversion memory means for converting into.

Further, in a down converter for converting a high definition television system signal into a standard television system signal, a first clock generating means for generating a high definition television system clock and a standard television system. Second clock generating means for generating a clock and a signal of the high definition television system are written by the high definition television system clock and the clock frequency of the high definition television system is changed by changing the clock frequency at the time of reading. The time axis conversion memory means for converting the time axis of the, the standard television system clock for reading the luminance signal written in the time axis conversion memory means, and the high definition television system clock for reading the color difference signals selectively. And a selector means for outputting the clock to a clock selected by the selector means. Conversion from degrees television signal rate to a standard television signal rate so that use with the read clock of the time-axis conversion memory means.

Furthermore, in the converter device having the above structure, a luminance signal and two kinds of luminance signals are provided in one scanning line to be written in the time base conversion memory means for converting the high definition television signal rate to the standard television signal rate. It is provided with a writing means for writing the color difference signal and two systems of color expansion means provided corresponding to the two kinds of color difference signals, and two kinds of the two kinds of color difference signals are read out from the time axis conversion memory means. To the color expansion means for color line sequential decoding.

[0014]

According to the above construction, the high-definition television system signal is thinned out and written in the time base conversion memory means by the high-definition television system clock. Of the video signals thinned out and written in the time-axis conversion memory means, the luminance signal is read out by the standard television system clock and converted into the standard television signal rate, but the color difference signal is the standard television system. A clock having a frequency higher than the clock or a high definition television system clock is read and converted to a standard television signal rate. Therefore, the reading period of the color difference signal from the time axis conversion memory is shortened, and instead the reading clock frequency of the luminance signal can be lowered to lengthen the reading period of the luminance signal.
It is possible to improve the shortage of the video period with respect to the entire horizontal period. Further, the luminance signal and the two kinds of color difference signals are written in the time base conversion memory for one scanning line of the standard television system, and the two kinds of color difference signals are supplied to the two systems of color expansion means at the time of reading, whereby the color lines are sequentially arranged. Decoding can be done and the vertical resolution of colors can be improved.

[0015]

1 is a block diagram of a first embodiment of the present invention. The MUSE signal is supplied to the input terminal 1, and the A / D
The analog signal is converted into a digital signal by the converter 2 and then supplied to the MUSE processing circuit 3. MUS
The E processing circuit 3 performs MUSE processing necessary for the video signal section such as de-emphasis and field interpolation processing on the digital signal supplied from the A / D converter 2 and supplies it to the vertical filter 11 and a synchronizing signal. Are supplied to the memory control circuit 9 and the 1125 system clock generation circuit 4.

The vertical filter 11 attenuates the component of the video signal output from the MUSE processing circuit 3 that is folded back during thinning of the scanning lines, and supplies the attenuated component to the time axis conversion memory 12.
On the other hand, in the 1125 system clock generation circuit 4, the 1125 system clock is generated by the PLL from the waveform of the horizontal synchronizing signal,
The 1125 system clock is supplied to the 525 system clock generation circuit 5, the third clock generation circuit 7, the memory control circuit 9, the time axis conversion memory 12, and necessary parts. In the 525 system clock generation circuit 5, the 525 system clock is generated from the 1125 system clock by the PLL.
The 25-system clock is supplied to the frequency dividing circuit 6, the memory control circuit 9, the clock switching circuit 8 and necessary parts. 5
The clock frequency of the 25 system is 896 so that the luminance signal period becomes 83.5% of the entire horizontal period as shown in FIG. 9B.
It is set to fh (14.11 MHz).

In the third clock generation circuit 7, the above 11
16.5 of the entire horizontal period by the PLL from the 25 system clock
A third clock having a frequency of 1140 fh (17.96 MHz) is generated so that the reading of the color difference signal 188 samples is completed in the time of%, and is supplied to the clock switching circuit 8. The clock switching circuit 8 supplies the 525-system clock during the luminance signal reading period and the third clock during the color difference signal reading period.
Is selected, and the selected clock is the color expansion circuit 13 and the time base conversion memory 12.
Is supplied to.

The memory control circuit 9 generates a write enable signal so that the video signal is written into the time base conversion memory 12 by thinning out the video signal only in the video period of the color difference signal and the luminance signal and halving it in the vertical direction. , To the time axis conversion memory 12. In the time axis conversion memory 12, the video signal written at the 1125 system clock in accordance with the write enable signal is read at the 525 system clock in the luminance signal period to convert the high definition television signal rate to the standard television signal rate. , Is supplied to the blanking circuit 18, is read at the third clock in the color difference signal period, and is supplied to the color expansion circuit 13.

The conversion from the high definition television signal rate to the standard television signal rate for the color difference signals can be realized by the FIFO memory in the color expansion circuit 13. In the color expansion circuit 13, the color difference signal is written in the FIFO memory at the third clock, and at the time of reading, the 525 system clock is read from the memory at the same time as the luminance signal by the clock whose frequency is divided by 1 in the frequency dividing circuit 6. As a result, color expansion is performed and the line-sequential decoding unit 10 is supplied.

The line-sequential decoding unit 10 is a line memory 1
4, 15 and the adder 16 and the selector circuit 17 interpolate the color difference signal in the vertical direction, and the color difference signal thus interpolated is supplied to the blanking circuit 18.
The blanking circuit 18 blanks the portion of the luminance signal Y and the two types of color difference signals R-Y and B-Y that were in the color difference signal period at the time of reading from the time base conversion memory 12, and D
It is supplied to the / A converters 19, 20, 21. The D / A converters 19, 20, and 21 convert the luminance signal and the two types of color difference signals into analog signals, which are omitted in FIG.
It is supplied to the C encoder.

FIG. 2 is a block diagram of a second embodiment of the present invention, and the portions corresponding to the first embodiment shown in FIG. 1 are designated by the same reference numerals. In FIG. 2, the MUSE signal is supplied to the input terminal 1, converted from an analog signal to a digital signal by the A / D converter 2, and then supplied to the MUSE processing circuit 3. The MUSE processing circuit 3 performs necessary MUSE processing such as de-emphasis and field interpolation processing on the digital signal supplied from the A / D converter 2 and supplies the digital signal to the vertical filter 11. The sync signal is separated and supplied to the memory control circuit 9 and the 1125 system clock generation circuit 4.

The vertical filter 11 attenuates the components that are turned back when the scanning lines are thinned out, and supplies them to the time axis conversion memory 23. On the other hand, in the 1125 system clock generation circuit 4, the 1125 system clock is generated by the PLL from the waveform of the horizontal synchronization signal. The 1125 system clock is generated by the 525 system clock generation circuit 5, the clock switching circuit 22, the memory control circuit 9, the time axis conversion memory. 23 and necessary parts. In the 525 system clock generation circuit 5, the 525 system clock is generated from the 1125 system clock by the PLL.
The 25-system clock is supplied to the frequency dividing circuit 6, the memory control circuit 9, the clock switching circuit 22 and necessary parts.
The clock frequency of the 525 system is 89 so that the luminance signal period becomes 83.5% of the entire horizontal period as shown in FIG. 9B.
It is set to 6 fh (14.11 MHz).

The clock switching circuit 22 is constructed so that the 525 series clock is selected during the luminance signal reading period and the 1125 series clock is selected during the color difference signal reading period. The selected clock is the color expansion circuit 24 and It is supplied to the time axis conversion memory 23. The memory control circuit 9 thins out the video signal only in the video period of the color difference signal and the luminance signal and halves it in the vertical direction, and the time axis conversion memory 2
A write enable signal as shown in FIG. 8A is generated so as to be written in 3, and is supplied to the time axis conversion memory 23. In the time axis conversion memory 23, the video signal written at the 1125 system clock according to the write enable signal is read at the 525 system clock during the video signal period, so that the high definition television signal rate is converted to the standard television signal rate. Is supplied to the blanking circuit 18 during the color difference signal period and is 1125
It is read by the system clock and supplied to the color expansion circuit 24.

The conversion from the high definition television signal rate to the standard television signal rate for the color difference signals can be realized by the FIFO memory in the color expansion circuit 24. In the color expansion circuit 24, the color difference signal is transmitted to the FIF by the 1125 system clock.
The color expansion is performed by writing the data in the O memory and reading the 525 system clock at the same time as the luminance signal with the clock whose frequency is divided into ¼ by the frequency dividing circuit 6 at the time of reading, and the line sequential decoding unit 10 Is supplied to.

The line-sequential decoding unit 10 is composed of line memories 14 and 15, an adder 16 and a selector circuit 17 for vertically interpolating the color difference signals, and the color difference signals thus interpolated are blanking circuits. 18 are supplied. In the blanking circuit 18, the luminance signal and the two types of color difference signals are blanked in the portion that was in the color difference signal period when the color axis signal was read from the time base conversion memory 23, and the D / A converter 1
It is supplied to 9, 20, and 21. D / A converters 19, 2
0 and 21, the luminance signal Y and the two types of color difference signals RY and B-
Y is converted into an analog signal and is supplied to the NTSC encoder although omitted in FIG.

Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 3, parts corresponding to the first and second embodiments of the present invention shown in FIGS. 1 and 2 are designated by the same reference numerals. The MUSE signal is supplied to the input terminal 1, and the A / D
The analog signal is converted into a digital signal by the converter 2 and then supplied to the MUSE processing circuit 3. MUS
The E processing circuit 3 performs MUSE processing necessary for the video signal section such as de-emphasis and field interpolation processing on the digital signal supplied from the A / D converter 2 and supplies the MUSE processing to the vertical filter 11. The signals are separated and supplied to the memory control circuit 9 and the 1125 system clock generation circuit 4.

The vertical filter 11 attenuates the components that are turned back when the scanning lines are thinned out, and supplies the attenuated components to the time axis conversion memory 25. On the other hand, in the 1125 system clock generation circuit 4, the 1125 system clock is generated by the PLL from the waveform of the horizontal synchronizing signal, and the 1125 system clock is transmitted to the 525 system clock generation circuit 5, the memory control circuit 9, the time axis conversion memory 25 and necessary parts. Supplied. The 525-series clock generation circuit 5 outputs 52 clocks from the 1125-series clock by PLL.
A 5-system clock is generated, and this 525-system clock is supplied to the frequency dividing circuit 6, the memory control circuit 9 and necessary parts.

The memory control circuit 9 writes the video signal to the time axis conversion memory 25 only in the video period of the color difference signal and the luminance signal while thinning out the luminance signal by half in the vertical direction and without thinning out the color difference signal. Thus, a write enable signal as shown in FIG. 8B is generated and supplied to the time axis conversion memory 25. In the time axis conversion memory 25, 11 is written according to the write enable signal.
The high definition television signal rate is converted to the standard television signal rate by reading the video signal written with the 25 system clock with the 525 system clock,
A blanking circuit 18 and a two-system color expansion circuit 26,
27.

The two systems of color decompression circuits 26 and 27 are constructed by using FIFO memories in which writing and reading are asynchronous. One color difference signal RY is sent to the color expansion circuit 26 and the other is sent to the color expansion circuit 27. The color difference signal BY is written in the memory at the clock of 525 system, and at the time of reading, the color is expanded by being read from the memory at the same time as the luminance signal by the clock frequency-divided by the frequency dividing circuit 6. Is supplied to the blanking circuit 18.

In the blanking circuit 18, when the luminance signal Y from the time base conversion memory 25 and the two kinds of color difference signals RY and BY from the color expansion circuits 26 and 27 are read from the time base conversion memory 25. The portion that was in the color difference signal period is blanked and supplied to the D / A converters 19, 20, and 21. The D / A converters 19, 20 and 21 convert the luminance signal Y and the two types of color difference signals RY and BY into analog signals, which are omitted in FIG.
Supplied to the encoder.

In the third embodiment of the present invention shown in FIG. 3, the number of samples read from the time base conversion memory 25 of the color difference signal is doubled, so that the vertical resolution of color can be improved. However, since the 525-system clock processes 748 samples of the luminance signal and 188 × 2 samples of the color difference signals of the two systems in one horizontal period, 1124 fh
The frequency needs to be as high as (17.70 MHz), which results in a short horizontal image period. Therefore, the third
In the case of improving the vertical resolution of color by the above embodiment, as shown in FIGS. 4 and 5 as the fourth and fifth embodiments of the present invention, a method of combining with the first or second embodiment is effective. Is.

4 and 5 of the present invention shown in FIGS. 4 and 5.
In the embodiment of the present invention, the first embodiment of the present invention shown in FIGS.
Through the corresponding parts of the third embodiment, the same reference numerals are given and the description thereof is omitted. 4 and 5, 13-1, 24
-1 is the color expansion circuit 26 of FIG. 3 for expanding one color difference signal R-Y, and 13-2 and 24-2 are the other color difference signal B.
This corresponds to the color expansion circuit 27 of FIG. 3 for expanding -Y. Further, the color difference signal may be sub-sampled to reduce the number of samples to prevent the horizontal video period from being shortened.

[0033]

As described above, the present invention has the above-described structure. Therefore, when the time axis of the down converter is extended, the horizontal video period can be set substantially in accordance with the NTSC standard with a simple circuit structure, and the overscan section can be obtained. There is no fear that blanking will appear in the horizontal corners of the screen until the image exists. In addition, when a high definition television system signal is written in a memory for time axis conversion, a thinned luminance signal and two color difference signals are written for each luminance signal. In the case where the two-system color expanding circuit for expanding is provided, the vertical resolution of color becomes the same as NTSC, and the conventional line-sequential decoding circuit becomes unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a fifth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a video signal in which color signals are time-division multiplexed.

FIG. 7 is an explanatory diagram of scanning line conversion.

FIG. 8 is an operation explanatory diagram of a time axis conversion memory.

FIG. 9 is a diagram for explaining a signal format of a horizontal video signal.

FIG. 10 is a block diagram of a conventional example.

FIG. 11 is a block diagram of another conventional example.

[Explanation of symbols]

 4 1125 system clock generation circuit 5 525 system clock generation circuit 7 Third clock generation circuit 8, 22 Clock switching circuit 9 Memory control circuit 12, 23, 25 Time axis conversion memory 13-1, 24-1 Color expansion circuit 13- 2, 24-2 color expansion circuit

Claims (3)

[Claims] 1. A down converter for converting a high-definition television system signal into a standard television system signal, wherein a first clock generating means for generating a high-definition television system clock and a standard television system are provided. Second clock generating means for generating a clock, third clock generating means for generating a clock having a frequency higher than that of the standard television system clock, and a signal of high definition television system for the high definition television. Time axis conversion memory means for converting the time axis of the high definition television signal by changing the clock frequency at the time of writing and reading with a system clock, and reading the luminance signal written in the time axis conversion memory means From the third clock generating means for reading the standard television system clock and the color difference signal, And a selector means for selectively outputting a clock, and using the clock selected by the selector means as a read clock of a time base conversion memory means for converting a high definition television signal rate to a standard television signal rate. Down converter device characterized by. 2. A down converter for converting a high-definition television system signal into a standard television system signal, and a first clock generating means for generating a high-definition television system clock, and a standard television system. Second clock generating means for generating a clock and a signal of the high definition television system are written by the high definition television system clock and the clock frequency of the high definition television system is changed by changing the clock frequency at the time of reading. The time axis conversion memory means for converting the time axis of the, the standard television system clock for reading the luminance signal written in the time axis conversion memory means, and the high definition television system clock for reading the color difference signals selectively. And a selector unit for outputting the clock selected by the selector unit. A down converter device for use as a read clock of the time axis conversion memory means for converting a revision signal rate to a standard television signal rate. 3. The down converter device according to claim 1 or 2, wherein the luminance is provided in one scanning line written in the time axis conversion memory means for converting a high definition television signal rate to a standard television signal rate. A writing means for writing the signals and the two kinds of color difference signals, and two systems of color expanding means provided corresponding to the two kinds of color difference signals. The color difference signal is supplied to each of the two systems of color expansion means,
A down-converter device characterized by sequentially decoding color lines.