JPS63171091A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To attain the display of a high definition freezing picture by storing chrominance signals and scanning line interpolation signals corresponding to movements in the frame memory of a luminance signal/chrominance signal (Y/C) separation circuit and a field memory for interpolation respectively and outputting them. CONSTITUTION:The movements of pictures are detected in a movement detection circuit 6 which an input signal which is delayed by one frame passing through the frame memory 2 of the Y/C separation circuit and an input signal and the mixing rate of signals which pass through a line comb-line filter 3 and a frame comb-line filter 4 in a mixer 5 is adjusted and a C signal is obtained. The C signal is supplied to a subtracter 31 to be a Y signal corresponding to the movement of the picture and interpolated in the field memory 7 and an interpolation circuit 8 to output one field scanning inter-polation signal. Meanwhile, when switches 18 and 21 are switched to contacts (b) the output from the mixer 5 is written in a memory 2 and the output from the circuit 8 is written in the memory 7 so as to be repeatedly read out, so that the display of the high definition freezing picture can be attained even when the movement of the picture is large.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit for television display systems and video equipment, and is particularly suitable for playing back high-quality still images. Regarding.

[Conventional technology]

As a Y/C separation circuit for separating the luminance signal and chrominance signal of a composite color television signal, the difference between the input and output of a frame memory is disclosed in 15, for example, in Japanese Patent Application Laid-open No. 58-115995. Detects the movement of the subject by
When the movement is small, use frame correlation to Y/C
(Hereinafter, a circuit that performs such Y/C separation is referred to as a frame comb filter.) When the movement is large, vertical correlation (line correlation) is used to perform Y/C separation (hereinafter, such Y/C separation is performed. A circuit that performs /C separation is called a line comb filter).

FIG. 7 is a block diagram illustrating an example of the conventional Y/C separation circuit described above. In the block diagram shown in FIG. Flow is indicated by dashed lines.

In FIG. 7(a), 1 is a composite color television signal input signal, 702 is a luminance signal output terminal, and 2 is a 1-frame memory. 6 is a motion detection and control circuit, 4 is a frame comb filter, 7o1 is a delay circuit, 5 is a line (diamond filter, 7o4 is a delay circuit (DL), 5 is a mixer, 31
703 is a subtracter, and 703 is a carrier color signal output terminal.

Further, FIG. 8 is a block diagram showing a specific circuit configuration of the main circuits in FIG. 7(a).

Next, the operation of the circuit shown in FIG. 7(a) will be explained.

In the NTSC system, the phase of the carrier color signal is reversed between lines or frames, so the carrier color signal can be extracted by taking the difference between lines or frames, and the luminance signal can be extracted by taking the sum. Can be done.

Therefore, first, the frame comb filter 4 that obtains a carrier color signal by taking the difference between frames will be explained.

In FIG. 7(a), the frame comb filter 4 has a configuration as shown in FIG. 8(a).

In the figure, a composite color television signal input from an input terminal 1 is delayed by one frame period through a one frame memory 2. The input signal and output signal of the one-frame memory 2 are respectively input to the frame<C type filter 4. First, the subtracter 800 takes the difference between the two by 1, then the coefficient multiplier 801 doubles the difference and supplies it to the BPF 802. Then, the frequency band is limited by the BPF 802, and the signal is supplied as a carrier color signal Cv to the mixer 5 in FIG. 7fa).

Next, a description will be given of the line comb filter 3 which obtains a carrier color signal by taking the difference between lines.

In FIG. 7(a), the line comb filter 3 is the eighth
The configuration is as shown in Figure (b).

In the same figure, the output signal of one frame memory 2 is BrF
303, and its frequency band is limited. 1H
The output of the BPF 803 is input to the delay circuit 804 . First, the 1H delay circuit 804 is
The difference between the input and output is determined, and the carrier color signals are separated. The signal is then doubled through a coefficient multiplier 806 and supplied to the mixer 5 in FIG. 7(a) as a carrier color signal C-.

Next, the configuration of the mixer 5 is shown in FIG. 8(C). This is to synthesize the carrier color signal C using the following equation.

C=KCL+ (1-K) Cν =K (C11-Cy)+Cy In the same figure, first, the subtracter 807 subtracts Cb and Cy, and then the subtractor 808 subtracts this from K(0≦≦
1) Multiply, then delay circuit 80 by adder 810
9 and the output of the coefficient multiplier 808 to obtain a carrier color signal C.

Here, the control signals supplied to the coefficient multiplier 808 are those generated by the motion detection and control circuit 6. That is, in the motion detection and control circuit 6, one frame memo! 12
The movement of the image on the screen is detected dot by dot from the input and output signals of , and when there is no movement, K is output as a value close to OK, and when there is movement, K is output as a value close to 1. Ru.

Therefore, in the mixer 5, according to the control signal K, a large amount of the carrier color signal C1 separated by the frame comb filter 4 is output in areas where there is no movement on the screen, and more of the carrier color signal C1 separated by the frame comb filter 4 is output in areas with movement. A large number of carrier color signals CL are output.

Now, the configuration of the motion detection and control circuit 6 is shown in FIG. 8(d).
Show K.

In the figure, first, the output signal of the one-frame memory 2 is input to the chroma inverter 812, and the chroma inverter 812 inverts the phase of only the carrier color signal component in the signal. Then, the subtracter 813 subtracts the signal obtained by delaying the input signal of the one frame memory 2 by the delay circuit 811 and the output of the chroma inverter 812.
The difference is converted into 0≦≦1 by the nonlinear conversion circuit 814.
is converted into a control signal K. Then, as shown in FIG. 7(a), the signal is supplied to the mixer 5 via a delay circuit 704.

Next, the carrier color signal C output from the mixer 5 is subtracted by the subtracter 51 from the signal obtained by delaying the output signal of the one frame memory 2 by the delay circuit 701, thereby obtaining the luminance signal Y. And the luminance signal output terminal 70
2.

Furthermore, a carrier color signal C, which is the output of the mixer 5, is output from the carrier color signal output terminal 703.

By the above-described operation, the luminance signal and the carrier color signal are accurately separated and output from the NTSC signal, so that high-quality reproduction is possible.

It should be noted that each delay circuit shown in FIGS. 7(a) and 8 is provided for the purpose of offsetting the delay time of each circuit element in other signal paths, respectively.
Hereinafter, the delay circuit will be omitted in order to simplify the explanation.

By the way, when high-quality still images are reproduced using the conventional Y/C separation circuit as described above, the following configuration has conventionally been used.

That is, the circuit shown in FIG. 7(b) is placed before the circuit shown in FIG. 7(a).
The circuit shown in FIG. 7 is connected (that is, the output of the switching circuit 713 of FIG. 7 (bJ, which will be described later) is connected to the input terminal 1 of FIG. 7(a)).

In the case of a still image, the phase of the carrier color signal is reversed every frame, but the same signal is repeated every two frames. Taking advantage of this fact, this circuit uses two 1-frame memories to reproduce still images.

In FIG. 7(b), 711 is an input terminal to which an NTSC composite color television signal is input, 712 is a mode signal input terminal to which a mode signal indicating whether the still image playback mode or video playback mode is input, and 714 .715 is each one frame memory, and 713 is a switch.

A mode signal input from mode signal input terminal 712 controls switching of switch 713.

In the figure, in the video playback mode, the mode signal from the mode signal input terminal 712 causes the switch 713 to switch as shown, and the composite color television signal from the input terminal 711 is directly transmitted to the switch 713. This becomes the output. Then, the output of the switch 713 is inputted to the input terminal 1 of FIG. 7(a), and the above-described operation is performed thereafter.

As a result, normal high-quality video playback is performed.

In addition, the output of the switch 713 is the one frame memory 7
14 and are sequentially written. The signals written in the 1-frame memory 714 are then sequentially read out and written into the 1-frame memory 715 at the subsequent stage.

On the other hand, in still image playback mode, mode signal input terminal 7
The mode signal from 12 causes the switch 713 to switch to the opposite side from that shown, and the output of the 1-frame memory 715 is output from the switch 713. As a result, the signal read out from the 1-frame memory 715 is written to the 1-frame memory 714 again, that is, the signal for the 2 frames stored in the 1-frame memories 714 and 715 at the time of switching. The color television signal is circulated through one frame memories 714 and 715 in sequence. Therefore, the same composite color television signal for two frames is repeatedly input to the input terminal 1 in FIG. 7(a).

Note that since the composite color television signal that is repeatedly input into the circuit of FIG. 7(a) is for two frames, the phase of the carrier color signal in the composite color television signal is 1.
Repeat inversion every frame.

Therefore, the Y/C separation operation in the frame comb filter 4 shown in FIG. 7(a) is also possible as usual. In this manner, the above-described Y/C separation operation is performed in the circuit shown in FIG. 7(a), and a high-quality still image can be obtained.

However, when there is an object that moves rapidly within the video screen, the position of the object varies greatly from field to field, and the object moves a considerable distance during two frames (four fields).

In such a case, if you perform still image playback as described above,
The object ends up being a still image with large fluctuations.

Furthermore, due to interlaced scanning, deterioration occurs such as line flicker and rough scanning line structures becoming visible. Therefore, intuitively, the image quality does not appear to be the same as the electrically determined number of scanning lines, and it is well known that the effective number of scanning lines is approximately α6 to α7 times the number of electrical scanning lines. There is.

(For example, "Screen system/scanning system J for high-definition television, NHK Giken Monthly Report, 1982-11)" - On the other hand, the receiving side interpolates the scanning lines and converts the signal into a sequentially scanned signal. There are known devices that avoid the above deterioration by displaying
In the example shown in Publication No. 7, the movement of the image is detected, and when the movement is small, interpolation is performed between fields to create an interpolated scan line, and when the movement is large, it is assumed that it is a moving image and the field is interpolated. It performs motion-adaptive processing such as internal interpolation.

The outline of this signal processing circuit will be explained using FIG. 9.

FIG. 9 is a block diagram showing an example of a signal processing circuit that performs scanning line interpolation according to the prior art, and 901 is an input terminal;
902 and 903 are first and second field memories; 90
4 is a scanning line interpolation circuit, 6 is a motion detection circuit, 9 is a double speed conversion circuit, and 906 and 907 are first . second time compression circuit, 9
08 is a selection circuit, and 909 is an output terminal.

In the figure, a 2=1 interlaced scanning signal from an input terminal 901 and a signal obtained by extending this for one frame period are input to the motion detection circuit 6, and the absolute value of the interframe difference signal is calculated. to detect image movement. As described above, the characteristics of the scanning line interpolation circuit 904 are controlled by the amount of movement of this image.

When creating interpolated scanning lines, the input signal performs interlaced scanning, so the scanning lines of the fields before and after one field scan the position of the scanning line to be interpolated in the current field. Therefore, these scanning line signals can be directly used as interpolated scanning line signals.

However, such inter-field interpolation can only be performed for still images. For moving images, two images separated by -seconds are superimposed, resulting in major deterioration such as multi-line blur.

Therefore, when the amount of movement in the image detected by the motion detection circuit 6 is large and therefore it is determined that it is a moving image, only the scanning line signal of the current field is used, for example, by taking the average of two consecutive scanning lines. The above deterioration is avoided by creating an interpolated scanning line signal.

[Problem that the invention seeks to solve]

As described above, in the conventional example, interlaced scanning signals are sequentially scanned without deteriorating the degree of resolution for still images (and without causing deterioration such as multi-line blurring for moving images). It is converted into a scanning signal.

However, when still images are played back by combining such a motion-adaptive signal processing circuit with the Y/C separation circuit shown in Figure 7, the output of the Y/C separation circuit will be affected by fluctuations in moving images. Since the still image is large, the output signal of the scanning line interpolation circuit also fluctuates, resulting in a reproduced still image.

In addition, in the motion adaptive signal processing circuit such as the conventional example described above, as another method of still image reproduction, by using the field memory or frame memory that it has,
) It is possible to obtain a 9-z image (still reproduced image). That is, a frozen image can be obtained by stopping updating of the memory contents and repeatedly reading out the same contents. However, a problem in this case is that image motion cannot be detected. In other words, as mentioned above, image motion detection is performed by taking the difference between signals separated by one frame period, so if you stop updating the frame memory in freeze mode, it is possible to obtain signals separated by one frame period. Therefore, it is not possible to detect the movement of the image.

For this reason, motion adaptive signal processing cannot be performed during freezing. At this time, if full-screen still image processing is attempted, the moving image portion will become a double image, resulting in an extremely unnatural image.

Furthermore, if you try to perform full-screen video processing, you will only be able to obtain images with reduced resolution.

Furthermore, until the freeze mode is set, motion adaptive processing is performed, so the still part of the image has a high resolution, but as soon as it freezes, the resolution of this part decreases, resulting in an unnatural image. [It will be put away.

As mentioned above, in the prior art, when a still image is replayed, large fluctuations occur in the reproduced screen when an object moves violently on the screen. Additionally, if full-screen video processing is performed to prevent this, there is a problem in that the resolution of the still image playback screen decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing circuit that can reproduce high-quality still images without the above-mentioned deterioration even when a moving image is frozen.

[Means for solving problems]

The above object includes a Y/C separation circuit having a first memory having a capacity of at least one frame, a scanning line interpolation circuit having a second memory having a capacity of at least one field, and a scanning line interpolation circuit having a first memory having a capacity of at least one frame; Based on the detection results, the above Y
A video signal processing circuit having a motion detection circuit for motion adaptively controlling the /C separation circuit and the scanning line interpolation circuit, a third memory having a capacity of about 1 field, an M4 memory having a capacity of about 1 field, Separated signal writing means for storing in a third memory the Y/C separated output signal subjected to motion adaptive processing by the Y/C separating circuit, and scanning line interpolation subjected to motion adaptive processing by the scanning line interpolation circuit. This is achieved by providing an interpolation signal writing means for storing the signal in the fourth memory, and a reading means for repeatedly reading the memory contents of the third memory and the fourth memory (one frame in total).

[Effect]

During still image playback, the separation signal writing means
The signal after motion adaptive Y/C separation is written into the third field memory, and the signal after motion adaptive scanning line interpolation is written into the fourth field memory by the interpolation signal writing means, and these signals are read by the reading means. By repeatedly reading out the data, it is possible to obtain a Y/C separation output and an interpolation output that match the image of one field period, thereby obtaining a still image without fluctuation.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention,
Video signals are shown by solid lines, control signals are shown by broken lines, 1 is an input terminal for a composite color television signal, 2 and 10 are first and second frame memories, 3.11 is a line comb filter, 4, 12 is a frame comb filter, 5.13
is a mixer, 6 is a motion detection circuit, 7 is a field memory,
8, 14 are first and second scanning line interpolation circuits, 9, 15 are double speed conversion circuits 1.17 are color difference signal demodulation circuits, 1B, 19
゜20.21, 22, 23 are the 1st. Second. 6th. Fourth,
Third. 6th switch, S+, 82, S
s.

84, Ss, 86 are Swiss f-18~230
Indicates a control signal. Further, 24 is a luminance signal output terminal, 25
is a carrier color signal output terminal.

First, the normal operation will be explained regarding the brightness signal system.

Normally, each switch is tilted toward the side a in FIG. 1.

A 2:1 interlaced scanning television signal (hereinafter referred to as an input signal) inputted from an input terminal 1 is delayed by one frame in a first frame memory 2. Further, a signal obtained by delaying the input signal by one frame outputted from the first frame memory 2 and the input signal are input to a motion detection circuit 6 to determine the amount of motion of the image.

Next, regarding Y/C separation, the line comb filter 3 in FIG. A carrier color signal is obtained by processing similar to that described in FIGS. 7 and 8, and is converted into an image motion by a mixer 5 controlled by the amount of motion obtained by the motion detection circuit 6. The subtracter 61 subtracts the color signal subjected to the motion adaptive processing from the input signal and outputs a luminance signal subjected to the motion adaptive processing.

The scanning line interpolation circuit 8 receives the luminance signal subjected to the motion adaptive processing and the signal delayed by one field by the first field memory 7, and outputs an interpolated scanning line signal.

FIG. 2 is a detailed block diagram of the interpolation circuit shown in FIG. 1. In FIG. 2(a), the output of line P19 in FIG. (Brightness signal) A signal output terminal 211 receives an output delayed by one field from the first field memory 7 with respect to the input 212. The amount of movement of the image detected by the motion detection circuit B shown in FIG. 1 is input to the terminal 213. The input from the terminal 212 is 1H by the 1H delay circuit 202.
Delayed by a time corresponding to the horizontal scan-period.

Adder 205 adds the above signal and the input signal from terminal 212.
The signal (average value data) which is added by the coefficient multiplier 204 and then multiplied by 1/2 by the coefficient multiplier 204 is input to the mixer 214 . The other input of the mixer 214 receives from the terminal 211 a signal delayed by one field with respect to the output signal of the coefficient multiplier 204.The mixer 214 receives the amount of motion of the image from the input terminal 213. , This creates interpolated values that include more average value data (intra-field processing) for moving images, and creates interpolated values that include more one-field delayed data (inter-field processing) for still images. Output from. In this way, the optimal interpolation value according to the movement is created.

The interpolated scanning line signal obtained as described above and the output from the subtracter 31, that is, the luminance signal subjected to motion adaptive processing, are input to a double speed converter 9 (FIG. 1) K. As shown in FIG. 9, the double speed converter 9 compresses the time axis of the input signal by half using time axis compression circuits 906 and 907, and switches the time axis for each scanning line after time compression using a switch 908. and output it.

This signal is output from the output terminal 24 as a sequential scanning signal. Such progressive scanning signals can be used for motion adaptive processing using Y/C
Since both the separation system and the interpolation system are used, high-resolution images are obtained for still images, and high-quality images without double blurring are obtained for moving images, although the resolution of the moving image portion is reduced. I can do things. Specifically, the still image part uses frame comb Y/C separation and interfield interpolation processing, and the moving image part uses line comb Y/C separation and interfield interpolation processing.

Next, a signal 8 for controlling the switches 18 to 25 shown in FIG.
The generation circuits 1 to S6 will be explained.

FIG. 3 is a block diagram of the control signal generation circuit in FIG. 1, and FIG. 4 is its timing diagram.

In FIG. 3, 401 is a freeze switch; 40
2 is an input terminal, 405 and 404 are D flip-flops (
405 is an AND gate. Generally, freezing starts at any timing as shown in Figure 4 (
It is set as shown in b).

Therefore, it is not necessarily synchronized with screen switching.

In this case, if freezing is started in the middle of a certain field, the subsequent one field period will be frozen, resulting in a moving image that is discontinuous at the top and bottom of the screen. To avoid this, Figure 3 is replaced with Figure 4 (
As shown in c) and (d), the signal (a) in which the freeze signal is synchronized with the vertical retrace period (for example, the vertical synchronization signal Vax
xa) by DF'F' 403.

It is latched and used at 404. Free switch 401
is input to the first DFF 405, latched at time to by VBYNO input from the input terminal 402, and the signal S1
get. This output is input to the second DFF404 and Vs
x NO is latched at time t1 to obtain a signal further delayed by one field. Signal S2 is the first DFF 40
AND AN of the output of s and the output of the second DFF 404
Get a D. As described above, the signals S1 and Sl are delayed as shown in FIG. 4, and can be used as the signals S1 and Sl used in the explanation of FIG. Further, Ss and Ss are signals having the same timing as Sl, and 8a and Sb have the same timing as Sl.

Next, the freeze time will be explained. First, each of the first, third, and third switches 18.20.2 of the Y/C separation system
2 is connected to the b side, which is the opposite side to that shown in FIG. 1, by means of control signals 8+, Ss, Ss. Therefore, the luminance signal output from the subtracter 31 and subjected to motion adaptive signal processing is written into the first frame memory 2 for one field period instead of the input signal. 1st line f-18
After one field period after the control signal S1 is input to
The second switch 19 is connected to the first side by the signal S2. At this time, updating of the memory contents of the first frame memory 2 is stopped by the signal S1, and the memory contents for one field are simply read out by the signal S2.

Regarding the interpolation system, the third switch 20 is connected to the side shown in FIG. 1 by the control signal Sg at the same timing as the control signal S1. As a result, the interpolated signal subjected to the motion adaptive signal processing is written into the first field memory 7 for one field period.

Further, the fourth switch 21 is connected to the first side shown in the figure at the same timing as the signal S2. At this time, the first field memory 7 performs the same operation as the first frame memory 2. As described above ((Then, after time t1 shown in FIG. 4, to-
The motion adaptive Y/C separated scanning line (original scanning line) signal is repeatedly output from the first frame memory for one field signal during t+, and the first field memo! From J7, interpolated scanning line signals subjected to motion adaptive processing in the field are repeatedly output.

As in normal times, the time axes of both of the two scanning line signals are compressed to 1/2, and the scanning line signals are sequentially outputted by switching and outputting each scanning line period after the time axis compression.

Next, normal operation for color signals will be explained. A signal with a frequency of about 5 to 4 MHz is extracted from the composite color television signal input from the input terminal 1 using BPFL (S).Next, in the color difference demodulation circuit 17, a low frequency component is extracted using a color subcarrier and a color signal is extracted. Demodulated and color difference signal (R-Y
), (B-Y) are output. However, this color difference signal still contains a luminance signal component. The processing up to the output of the sixth switch 23 is the same as that for the luminance system. At this time, the second frame memory 10, the line comb filter 11, the frame (the square filter 12, the mixer 1) shown in FIG.
In step 3, the remaining luminance signal components are removed.

Furthermore, since the frame memory 10 has a narrow color difference signal band, the memory capacity can be reduced to a greater extent than the frame memory 2.

Next, a scanning line interpolation circuit for color signals will be explained. An example of the configuration of the color signal interpolation circuit 14 is shown in FIG.
C) Show K.

The interpolation circuit for the color signal can be simpler than the interpolation circuit for the luminance signal shown in FIG. 2(a) because the frequency band of the color signal is narrow. In Figures 2(a) and (b), 20
1.207 is an input terminal 205, 206 to which the output of the sixth switch 23 in FIG. 1 is input; 209.210 is an output terminal.

FIG. 2(b) is a circuit for obtaining the average value of the upper and lower lines as interpolated scanning line data, and is the same circuit as FIG. 2(a). FIG. 2C shows a so-called double-write interpolation circuit that uses a signal delayed by one line as interpolation scanning line data. Alternatively, processing may be performed using a field memory as shown in FIG. 2(a).

As described above, a high-quality color difference signal (RY) is obtained.

(BY) is obtained. Next, a frozen image can be obtained by synchronizing the third line y'''22 in FIG. 1 with the first switch 18 and the sixth switch 26 with the second switch 19.The operation is described above. This is the same as the luminance system and interpolation system.

According to this embodiment, even when an image with rapid movement is frozen, the above process allows the still image to be reproduced without shaking. In addition, the frame memory used for motion detection is shared between the motion adaptive Y/C separation circuit and the scanning line interpolation circuit, and the Y/C separation system and interpolation system memory are also used during frozen image playback. High-quality still images can be reproduced without requiring a large increase in circuitry.

FIG. 3 is a block diagram showing another embodiment of the present invention, in which circuit blocks having the same functions as those in FIG. 1 are given the same reference numerals.

A feature of the embodiment shown in FIG. 3 is that, as a memory for still image reproduction, a second field memory is used to write the luminance signal output after motion adaptive Y'/C separation by a switch controlled by a control signal 81. 501, and a third field memory 5 into which the output after motion adaptive scan line interpolation is written by a switch 20 controlled by a control signal S3.
02 and a fourth field memory 503 into which the motion-adaptive processed color signal is written by the switch 22 controlled by the control signal Ss.

The normal operation in FIG. 3 is the same as in FIG. 1. The operation for still images will be explained below. After the freeze signal is input, the switch 18°20.22 is connected to the third side by the control signals S1, Ss, Ss.

Similar to the operation in Figure 1, the second and third field memos!
1501.505, luminance and color difference signals subjected to motion adaptive processing for one field period are stored in the fourth field memory 5.
A scanning line interpolation signal subjected to motion adaptive processing for one field period is input to 02, and after one field period, the switches 19,
21 and 23 are connected to b@ on the opposite side to that shown in FIG. 3, and a still image without fluctuation is thereafter reproduced in the same manner as the operation in FIG. 1.

According to the embodiment shown in FIG. 3, although the circuit scale is increased compared to the embodiment shown in FIG. 1, it is possible to reproduce still images without fluctuation even in images with rapid movement. Furthermore, types P1s and 2o which are the above-mentioned writing means.

22 is omitted because the field memory (1501, 502, and 503 are set to a write-inhibited state and the data in the memory is always read out).Also, Sl and 82 are explained as being shifted by one field as in Fig. 3. However, in this embodiment, even if the same control signal is used from S+ to S2, it is possible to reproduce a still image without fluctuation.

Therefore, the control signal generation circuit can be simplified.

FIG. 6 is a block diagram showing a further embodiment of the present invention, in which circuit blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals. Further, 601 is a yield memory.

The feature of the embodiment shown in FIG. 6 is that the processing circuit for the color signal system and the processing circuit for the luminance signal system are used together, and the signal obtained by demodulating the carrier color signal obtained by processing the luminance signal system is used as the color signal. In some cases, a separately provided field memory 601 is provided during still image playback.

In the figure, the switches 22 and 23 operate in the same manner as in FIG. 1, and the field memory 601 repeatedly outputs color signals subjected to motion adaptive processing for one field period after inputting the freeze switch.

Note that since the field memory used here has a narrow color signal frequency band, the memory capacity can be reduced to a greater extent than in the field memory 7 shown in FIG.

According to the embodiment shown in FIG. 6, a still image without fluctuation can be reproduced even in contrast to nine images with rapid movement, and furthermore, the circuit scale can be reduced compared to that in FIG. 1.

Furthermore, in the configurations of the embodiments shown in FIGS. 1, 3, and 6, frame memories and field memories of a delay line type that perform one frame delay and one field delay are also used, and the image display position It is also possible to use a video memory type in which memory addresses correspond one-to-one.

Next, the capacity of the frame memory will be explained.

For example, the sampling clock is 4 times his color subcarrier, 1
4.3 MHz, one horizontal scanning period is 910f
sample, and one frame is 910X262.5X2
=477.75Kf number of picture elements. Furthermore, with video memory type memory, the memory capacity corresponding to the horizontal retrace period and vertical retrace period is reduced.
It is also possible to configure a frame memory or one field memory with a smaller capacity. The memory capacity under similar conditions is approximately 768 f samples during one horizontal scan return (effective scanning period) excluding the retrace period, and 768 x 240 H x 2 = 568.64 Kf samples for one frame.
09.11, it is possible to use a frame memory with a capacity smaller than that of picture elements.

[Effects of the Invention] As explained above, according to the present invention, it is possible to obtain a Y/C separated signal and a scanning line interpolation signal that have been subjected to motion adaptive processing even during a freeze. It becomes possible to display a high-quality frame image even when compared to the conventional technology, and it is possible to provide a video signal processing circuit with excellent functions, while eliminating the drawbacks of the above-mentioned prior art.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a more detailed block diagram of the interpolation circuit of FIG. 1, and FIG. 3 is a block diagram showing an example of the control signal generator of the present invention. 4 is a timing diagram for explaining the operation of FIG. 3, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram showing still another embodiment of the present invention. FIG. 7 is a block diagram showing a conventional Y/C separation circuit, FIG. 8 is a block diagram showing an example of frame comb and line comb filters, mixers, motion detection and control circuits, and FIG. 9 is a conventional scanning circuit. FIG. 2 is a block diagram showing an example of a signal processing circuit that performs line interpolation. 1... Input terminal, 2.10...
... Frame memory, 6 ...... Intuition detection circuit, 8, 14 ...... Scanning line interpolation circuit, 9
, 15...... Double speed conversion circuit (time axis compression circuit) 7,501.502.503. 60.1...Field memory, 18,
19,20゜21.22.23...Switch, 401...Switch. -Go,

Claims (1)

[Claims] 1. A Y/C separation circuit comprising a first memory having a capacity of at least one frame, a scanning line interpolation circuit comprising a second memory having a capacity of at least one field, and an image motion A video signal processing circuit comprising: a motion detection circuit that detects motion detection circuit and motion adaptively controls the Y/C separation circuit and the scanning line interpolation circuit based on the detection result;
A third memory having a field capacity, a fourth memory having approximately one field capacity, and a Y/C separated output signal subjected to motion adaptive processing by the Y/C separating circuit.
separation signal writing means for storing in the fourth memory, interpolation signal writing means for storing in the fourth memory the scanning line interpolation output signal subjected to motion adaptive processing by the scanning line interpolation circuit; A video signal processing circuit comprising a memory and reading means for repeatedly reading out the stored contents of the fourth memory, and configured to be capable of displaying a high-quality freeze image for both moving images and still images. 2. The video signal processing circuit according to claim 1, wherein the third memory is a part of the first memory. 3. The video signal processing circuit according to claim 1, wherein the fourth memory is the same memory as the second memory.