JPH06333946A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a thin film transistor which can realize good electrical connection between each electrode and an amorphous silicon thin film and can be stably manufactured even when the transistor is miniaturized by providing a reactive layer and low-resistance semiconductor layer in the areas of the amorphous silicon thin film which are not in contact with 7t source and drain electrodes and inorganic protective film. CONSTITUTION:The transistor has a gate electrode 2 formed on an insulating substrate 1, gate insulating film 3 covering the electrode 2, and amorphous silicon thin film 4 formed in a prescribed shape on the film 3 in conformity with the electrode 2. In addition, the transistor also has an inorganic protective film 5 formed on the thin film 4 in corresponding to the electrode 2 and a source and drain electrodes 6 and 7 formed in such a state that the electrodes 6 and 7 are brought into contact with both end sections of the thin film 4 and not brought into contact with the film 5. Moreover, the transistor also has a reactive layer 8 and low-resistance semiconductor layer 9 formed by ion implantation in the areas of the thin film 4 which are not in contact with the electrodes 6 and 7 and film 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a manufacturing method thereof, for example, a thin film transistor used as an active element of an active matrix liquid crystal display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art An image display device using a liquid crystal display device is
Row and column electrodes arranged at a predetermined pitch on each substrate are arranged so as to be orthogonal to each other, and the minimum region partitioned by these row and column electrodes is defined as a pixel, and a nematic type or the like is placed between them. A matrix type in which a liquid crystal composition is sandwiched is generally used. Among them, as a large-capacity and high-precision liquid crystal display device for TV images and graphic displays, a semiconductor switching element is provided for each pixel as a driving and control means for each pixel so that high-contrast display without crosstalk can be performed. An active matrix type in which is arranged has been put to practical use.

As such a switching element, a thin film transistor is usually used because it can perform a transmissive display and can easily increase the area. Furthermore, a three-terminal type thin film transistor using an amorphous silicon thin film is the most general because it can be formed on a large area substrate and can be processed at a low temperature.

The structure of a three-terminal type thin film transistor is roughly classified into a coplanar type and a staggered type according to the relative relationship between the gate electrode, the semiconductor thin film layer, the source and the drain electrode. In the case of an amorphous silicon thin film transistor, a staggered type, which has many faces that are significant in terms of the manufacturing process, is often used. Among them, a gate electrode, a gate insulating film layer, an amorphous silicon thin film layer, a low resistance semiconductor An inverted staggered type structure having a structure in which a thin film layer, a source, and a drain electrode are formed in this order is common.

An example of such an inverted staggered amorphous silicon thin film transistor is shown in FIGS. 6 (A) and 6 (B).
Amorphous silicon thin film 4 and low resistance semiconductor thin film layer 9 as shown in FIG.
In addition, a structure having a structure in which the workability of the low-resistance semiconductor thin film layer 9 is improved by forming an inorganic protective film 5 made of silicon nitride, for example, and processing it into a predetermined shape is also adopted. .

In order to improve the performance and miniaturization of thin film transistors, it is necessary to accurately match the inorganic protective film with the gate electrode. For this, see FIG.
As shown in (B), after the gate electrode 2 is formed on the insulating substrate 1 and processed into a predetermined shape, the entire surface is covered with the gate insulating film 3
Cover with. Then, the amorphous silicon thin film 4 and the inorganic protective film 5
And the photoresist layer 10 is formed on the inorganic protective film 5.
Apply. Then, the photoresist layer 10 is patterned by exposing from the back surface side of the insulating substrate 1 using the gate electrode 2 as a mask in the direction of the arrow and further exposing from the substrate surface side using a normal photomask.
Then, the inorganic protective film 5 is processed and formed into a shape defined by the patterned photoresist layer 10.

In this method, in principle, the inorganic protective film 5 is not displaced with respect to the gate electrode 2, and in addition, the accuracy of the processing dimension is improved, and the performance of the thin film transistor is improved.
Can be miniaturized.

On the other hand, with respect to the structure of the thin film transistor itself, the above-mentioned low resistance semiconductor thin film layer poses a problem. For example, as shown in FIG. 6, a low resistance semiconductor thin film layer 9 is formed between the amorphous silicon thin film layer 4 and the source 6 or drain electrode layer 7. The low resistance semiconductor thin film layer 9 has a function of electrically connecting the amorphous silicon thin film layer 4 and the source 6 or the drain electrode layer 7 in an ohmic state.
Such a low-resistance semiconductor thin film layer 9 is formed on the amorphous silicon thin film layer by a plasma CVD method, for example, using a gas containing an element that can serve as a donor for silicon such as phosphorus as a raw material. The method is common. However, the plasma CVD method used for this method has problems such as easy generation of dust and poor operation rate.

On the other hand, IEEE TRANSACTION ON ELEC
As disclosed in the technical literature of TRON DEVICE, VOL.ED-32, No. 9, 1985, a method of forming a low resistance semiconductor thin film layer by an ion implantation method has also been proposed. Figure 5 (A) and (B)
An example of forming a low resistance semiconductor thin film layer by this ion implantation method is shown in FIG. The gate electrode layer 2 is processed and formed into a predetermined shape on the insulating substrate 1 by a normal photolithography method. Then, a silicon nitride film is formed on the gate electrode as a gate insulating film 3 so as to cover the gate electrode layer 2 by a CVD method such as plasma, atmospheric pressure or reduced pressure, using monosilane as a raw material to a thickness of 4000 angstroms. Continuing,
For example, an amorphous silicon thin film layer 4 having a thickness of 500 Å and an inorganic protective film 5 having a thickness of 2000 Å are formed.

Next, a photoresist (not shown) is applied on the inorganic protective film 5, exposed from the back surface side of the insulating substrate 1 to align with the gate electrode 2, and exposed again from the substrate surface by an ordinary photomask. Then, the photoresist in the unnecessary region is removed, and the inorganic protective film 5 is processed and formed into a predetermined shape.
After that, the amorphous silicon thin film layer 4 is processed and formed into a predetermined shape by an ordinary photolithography method.

Further, an ion of an element that can serve as a donor,
For example, phosphorus ions are used at an acceleration voltage of 10 KV and a dose of 1E16 / cm2.
Inject. At this time, since the above-mentioned inorganic protective film 5 can serve as a stopper at the time of phosphorus ion implantation, the channel portion ions of the thin film transistor are not implanted, and the low resistance semiconductor thin film layer 9 aligned with the inorganic protective film 5 is formed. Then, for example, Mo, which becomes the source 6 and the drain electrode 7,
Is formed into a film having a thickness of 2000 angstrom, and is processed and formed into a predetermined shape by an ordinary photolithography method.

In such an ion implantation method, the amorphous silicon thin film layer itself formed in the previous step is modified into a low resistance semiconductor thin film layer by ion implantation, so that the problem as seen in the plasma CVD method occurs. Absent. Further, since ion implantation is performed on the amorphous silicon thin film layer and can be performed in a self-aligned manner by using the inorganic protective film 5 processed into a predetermined shape as a mask, the thin film transistor can be improved in performance and miniaturized.

[0013]

However, for example, in the structure and manufacturing method of the thin film transistor as shown in FIG. 5, there is a problem in the shape processing of the source and drain electrodes. In other words, the number of arrayed electrodes is increasing more and more in line with the demand for higher precision of liquid crystal display devices, and the thin film transistors are also required to be smaller. The photolithography method using the above photomask has reached the limit anymore, and further miniaturization was impossible.

When the ion species are implanted into the amorphous silicon thin film layer, the surface of the amorphous silicon thin film layer is physically and chemically altered, so that the source and drain electrodes are formed thereafter. There is also a problem in improving the performance of thin film transistors, such as difficulty in obtaining sufficient electrical connection.

[0015]

The present invention corresponds to a gate electrode formed on an insulating substrate in a predetermined shape, a gate insulating film covering the gate electrode, and the gate electrode on the gate insulating film. Then, an amorphous silicon thin film formed in a predetermined shape, an inorganic protective film formed in a predetermined shape on the amorphous silicon thin film in correspondence with the gate electrode, and the amorphous silicon thin film Source and drain electrodes that are in contact with both ends and are formed in a predetermined shape without contact with the inorganic protective film, and none of the source and drain electrodes of the amorphous silicon thin film and the inorganic protective film. A thin film transistor having a reaction layer and a low resistance semiconductor layer formed by ion implantation in a region, and a step of forming a gate electrode on an insulating substrate to form a predetermined shape, and including the gate electrode. A step of sequentially forming a gate insulating film, an amorphous silicon thin film, and an inorganic protective film on the insulating substrate; a step of processing and forming the shape of the inorganic protective film so as to correspond to the gate electrode; A step of forming so that the length of at least both ends of the silicon thin film is larger than the length of the corresponding portion of the protective film; and a source on the entire surface of the substrate,
Forming a drain electrode and forming a reaction layer at a direct contact portion between the amorphous silicon thin film and the source and drain electrodes; and processing the source and drain electrodes so that a part of the reaction layer is exposed A method of manufacturing a thin film transistor comprising a step of forming and a step of implanting ions containing impurities into the amorphous silicon thin film corresponding to a part of the exposed region of the reaction layer.

[0016]

The present invention has been made in view of the above problems,
Source and drain electrodes are formed on the amorphous silicon thin film before the step of implanting ionic species, and a reaction layer is formed between the amorphous silicon thin film and the source and drain electrodes when the source and drain electrodes are formed. Thus, good electrical connection is realized between each electrode and the amorphous silicon thin film.

Further, the shape of the source and drain electrodes does not overlap with the end portions of the inorganic protective film, and the amorphous silicon thin film in the region not covered by the inorganic protective film and the source and drain electrodes can be ion-implanted. it can. Therefore,
In particular, since the distance between the source and drain electrodes can be made wider than before, it is easy to process the source and drain electrodes, and the thin film transistor can be made sufficiently stable without using a special method even for miniaturization of the thin film transistor. Can be manufactured.

[0018]

EXAMPLES Examples of the present invention will be described in detail below. FIG. 1 shows a schematic structure of a thin film transistor according to an embodiment of the present invention, and FIGS. 2A to 2D are process drawings for explaining the manufacturing process thereof.

A gate electrode layer is formed on the insulating substrate 1, and the gate electrode 2 is processed and formed into a predetermined shape by an ordinary photolithography method. So as to cover this gate electrode 2,
By a CVD method such as plasma, atmospheric pressure or reduced pressure, a silicon nitride film is formed to a thickness of 4000 angstroms by using monosilane as a raw material to form the gate insulating film 3. Then 50
An amorphous silicon thin film 4 having a thickness of 0 Å, an inorganic protective film 5 having a thickness of 4000 Å, and a photoresist layer 10 are sequentially formed. The photoresist layer 10 is exposed from the back surface of the insulating substrate 1 in the direction of the arrow so as to be aligned with the gate electrode 2 as shown in FIG.
Then, as shown in FIG. 2B, the photoresist layer in an unnecessary region is removed by exposing the substrate surface again using a normal photomask, and the inorganic protective film layer 5 having a predetermined shape is processed and formed. To do.

After that, an amorphous silicon thin film 4 having a predetermined shape is processed and formed by a usual photolithography method. At this time, the lengths of both ends of the amorphous silicon thin film 4 are equal to those of the inorganic protective film layer 5.
Is formed to be longer than the length of both ends. Then, on top of this, source and drain electrodes, for example, Mo of 4000
The film is formed to a thickness of angstrom. As such an electrode material, various materials such as Al, Cr, and Ni can be used as long as they function as an electrode and form a reaction layer with an amorphous silicon thin film. It may have multiple layers.

Next, as shown in FIG. 2 (C), the reaction layers 8 of the amorphous silicon thin film 4 and the reaction layer 8 of both sides are formed in the regions where the inorganic protective film layers 5 do not exist and which are in direct contact with the source and drain electrodes.
For example, heat treatment is performed at 200 ° C. for 1 hour in order to form Then, as shown in FIG. 2D, a source 6 and a drain electrode 7 having a predetermined shape are formed by an ordinary photolithography method. At this time, the source 6 and the drain electrode 7
And the inorganic protective film layer 5 do not overlap, and the reaction layer 8 is exposed. Therefore, even if the thin film transistor is miniaturized, the distance between the source electrode 6 and the drain electrode 7 is sufficiently wide, and the photolithography method with higher precision than the conventional one can be easily performed. When the reaction layer 8 is formed by the above heat treatment, the sheet resistance is 20 KΩ / □, and the source and drain electrodes are aligned with the inorganic protective film layer 5.

After that, an ion of an element that can serve as a donor,
For example, phosphorus ions may be applied to the acceleration voltage 10 from the direction of the arrow in FIG.
Implant with KV and dose of 1E16 / cm2. At this time, since the inorganic protective film layer 5 serves as an implantation stopper during phosphorus ion implantation,
Ions are not implanted into the channel portion of the thin film transistor, and the low resistance semiconductor layer 9 aligned with the inorganic protective film layer 5 is formed. The ion implantation conditions can be appropriately selected.

Now, in the step of forming the amorphous silicon thin film 4 after the formation of the inorganic protective film layer 5 shown in FIG. 2 (B), for example, when a chlorine-based etching gas is used, it is shown in FIG. 3 (A). As described above, the inorganic protective film layer 5 serves as an etching mask when the amorphous silicon thin film is etched, because there is sufficient selectivity between the amorphous silicon and the silicon nitride that is the material of the inorganic protective film. On the other hand, when a fluorine-based etching gas is used, Fig. 3 (B)
As shown in, there is no selectivity between amorphous silicon and silicon nitride. Therefore, when the amorphous silicon thin film is etched, the end portion of the inorganic protective film layer 5 is also etched and removed.

Next, FIGS. 4A to 4D show a second embodiment of the present invention. In the embodiment shown in FIG. 2 described above, after the gate electrode 2 is processed and formed into a predetermined shape, the gate insulating film 3, the amorphous silicon thin film, the inorganic protective film layer and the photoresist layer are sequentially formed, and exposed and etched. First, the inorganic protective film layer 5 and then the amorphous silicon thin film 4 are processed into a predetermined shape by the photolithography method.

On the other hand, in the embodiment shown in FIG. 4, after forming the gate electrode 2 into a predetermined shape, the gate insulating film 3 and the thickness of 4000 angstroms made of silicon nitride are formed.
A 500 angstrom amorphous silicon thin film is formed in the same manner as in the embodiment of FIG. Then, as shown in FIG. 4 (A), the amorphous silicon thin film 4 is formed into a predetermined shape by a normal photolithography method. Then, an inorganic protective film layer 5 having a thickness of 4000 Å is formed, and a photoresist layer 10 is formed on the inorganic protective film layer 5, and the back surface of the substrate 1 is aligned with the gate electrode 2 as shown in FIG. 4 (B). To expose.

Then, the substrate surface is exposed again by using a normal photomask to form the photoresist layer 10 in a predetermined shape, and the inorganic protective film layer 5 is formed in a predetermined shape using the photoresist layer 10 as a mask. To do. The subsequent process is
As shown in FIGS. 4C and 4D, a predetermined thin film transistor is formed in the same manner as in FIGS. 2C and 2D.

[0027]

As described above, according to the present invention, the source and drain electrodes are formed on the amorphous silicon thin film before the step of implanting the ion species, and the amorphous silicon thin film is formed at the time of forming the source and drain electrodes. By forming a reaction layer between the source electrode and the drain electrode, a good electrical connection can be realized between each electrode and the amorphous silicon thin film.

Further, the shape of the source and drain electrodes may not be overlapped with the end portion of the inorganic protective film, and ions may be implanted into the amorphous silicon thin film in the region not covered by the inorganic protective film and the source and drain electrodes. it can. Therefore,
In particular, since the distance between the source and drain electrodes can be made wider than before, it is easy to process the source and drain electrodes, and the thin film transistor can be made sufficiently stable without using a special method even for miniaturization of the thin film transistor. Can be manufactured.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a structure of a thin film transistor according to an embodiment of the present invention.

2A to 2D are process drawings for explaining a method of manufacturing the thin film transistor of FIG.

3A and 3B are plan views showing the configuration of the thin film transistor according to the manufacturing process of FIG.

4A to 4D are process drawings for explaining a method of manufacturing a thin film transistor according to a second embodiment of the present invention.

5A and 5B are process drawings for explaining a conventional method of manufacturing a thin film transistor.

6A and 6B are process drawings for explaining a conventional method for manufacturing a thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Gate electrode 3 ... Gate insulating film 4 ... Amorphous silicon thin film 5 ... Inorganic protective film 6 ... Source electrode 7 ... Drain electrode 8 ... Reaction layer 9 ... Low resistance semiconductor layer 10 ... Photoresist layer

Claims (3)

[Claims] 1. A gate electrode formed in a predetermined shape on an insulating substrate, a gate insulating film covering the gate electrode, and formed in a predetermined shape on the gate insulating film so as to correspond to the gate electrode. An amorphous silicon thin film, an inorganic protective film formed on the amorphous silicon thin film in a predetermined shape corresponding to the gate electrode, and contacting both ends of the amorphous silicon thin film with the inorganic protective film. Source and drain electrodes formed in a predetermined shape without being in contact with the film, a reaction layer in a region of the amorphous silicon thin film not in contact with the source and drain electrodes and the inorganic protective film, and ion implantation And a low-resistance semiconductor layer formed by the above method. 2. A step of forming a gate electrode on an insulating substrate and processing and forming it into a predetermined shape, and a gate insulating film, an amorphous silicon thin film, and an inorganic protective film are sequentially formed on the insulating substrate including the gate electrode. A step of forming a film, a step of processing the shape of the inorganic protective film so as to correspond to the gate electrode, and a length of at least both ends of the amorphous silicon thin film is greater than a length of a corresponding portion of the protective film. And forming a source and drain electrodes on the entire surface of the substrate to form a reaction layer at a direct contact portion between the amorphous silicon thin film and the source and drain electrodes, A step of processing and forming the source and drain electrodes so that a part of the reaction layer is exposed; and a step of implanting ions containing impurities into the amorphous silicon thin film corresponding to an exposed region of a part of the reaction layer Characterized by having And a method for manufacturing a thin film transistor. 3. The method of manufacturing a thin film transistor according to claim 2, wherein the step of processing and forming the amorphous silicon thin film is before the step of forming the inorganic protective film.