JPH06332735A - Abnormality detecting circuit for microcomputer system - Google Patents

Abstract

PURPOSE:To enable a microcomputer system to operate in a normal state after a temporary fault is restored by supplying an abnormality signal to a watch dog timer at the time of the abnormality detection of a memory, and repeatedly resetting a CPU. CONSTITUTION:A CPU 3' operates the abnormality check of a ROM 5 in a time T1 section after an ignition switch 2 is turned on, and operates the abnormality check of a RAM 4 in a following time T2 section. At the time of judging the presence of the abnormality as the result of the abnormality check, a watch dog timer 8' outputs a reset signal, and initializes the CPU 3'. Then, the CPU 3' operates the abnormality check similar to the previous time in a time T3 section following the time T2 section, and in a time T4 section following the time T3 section. Thus, at the time of the temporary abnormality which can be restored, a normal state can be automatically recovered while the ignition switch is turned on as it is, so that reliability on the system can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality detecting circuit for a microcomputer system in various electric equipment systems mounted on an automobile or the like.

[0002]

2. Description of the Related Art An abnormality detection circuit of this type of microcomputer system will be described with reference to FIG. In FIG. 3, the battery 1
Power from the CP via the ignition switch 2
U3 and RAM (write / read memory) 4 and R
It is supplied to a microcomputer 6 including an OM (read only memory) 5 and a watchdog timer 7 which detects and resets the runaway of the CPU 3.

The CPU 3 to which power is supplied detects the memory abnormality of the ROM 5 via the signal line A at the initial stage of the power supply, and further detects the memory abnormality of the RAM 4 via the signal line B. When there is an abnormality in one of them, the CPU 3 stops the supply of the control signal to the actuator (not shown). When there is no abnormality, various control signals created according to the built-in program are supplied to the actuator.

On the other hand, the CPU 3 constantly supplies a pulse of a predetermined frequency to the watchdog timer 7 through the signal line D during normal operation, but when the program runaway starts, The pulse is switched, and the watchdog timer 7 detects it by being latched in a high level state, for example, and supplies a reset signal to the CPU 3 via the signal line C. As a result, the CPU 3 starts executing the program again from the initial state.

[0005]

However, in the above-mentioned conventional abnormality detection circuit of the microcomputer system,
The microcomputer checks the writing / reading memory and the reading-only memory once, and if the result is abnormal, it stops the output of the control signal to the control target such as the actuator. However, there is a problem that the microcomputer system does not operate until the power is turned on again even when the power supply is turned on again even when the power supply is turned on again even when the power supply is turned on again in some abnormal state and naturally recovers.

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a configuration in which a failure check of a write / read combined memory and a read only memory is performed repeatedly. .

[0007]

An abnormality detection circuit of a microcomputer system according to the present invention includes a writing / reading memory, a reading only memory, and an abnormality check of the writing / reading memory and the reading only memory in an initial state. In an abnormality detection circuit of a microcomputer system including a microcomputer for performing and a watchdog timer for detecting a runaway of the microcomputer and supplying a reset signal, the CPU 3 detects an abnormality in the writing / reading memory and the read-only memory. At times, an abnormal signal is supplied to the watchdog timer to repeatedly reset the CPU.

[0008]

According to the present invention, when an abnormality is detected in either the write / read combined memory or the read-only memory, the CPU repeatedly executes the abnormality check until it is determined to be normal, so that the temporary When an abnormal state occurs and the normal state is restored, the microcomputer system starts operating in the normal state as soon as the normal state is restored.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment according to the present invention will be described below with reference to FIGS.
It will be described based on. In FIG. 1, the same or equivalent components as those of the conventional example shown in FIG. 3 are designated by the same reference numerals, detailed description thereof will be omitted, and only different portions will be described.

In FIG. 1, a CPU 3'is different from the CPU 3 described in the above conventional example in the following points. That is, the conventional CPU 3 ′ performs an abnormality check of the writing / reading memory 4 and the read-only memory 5 once,
When it is determined that there is an abnormality, the control signal is not output to the actuator, but the CPU 3 ′ in FIG. 1 does not operate at time T1 after the ignition switch 2 is turned on, for example.
In the section (see FIG. 2), the ROM (read-only memory) 5 is checked for abnormalities, during which the CPU 3 ′ outputs a pulse signal of a predetermined frequency shown in the time T1 section of FIG. 2 to the watchdog timer 8 ′, Time T2 which continues again
RAM (read / write memory) between sections 4
Error check is performed, a pulse signal of a frequency different from the previous time is output during that time (see FIG. 2), and if the result of both error checks is "no abnormality", the CPU 3'creates a control signal. Signal processing step. Further, in this case, the watchdog timer 8'does not output a reset signal to the CPU 3 ', but when it judges that there is an abnormality, it outputs a reset signal to initialize the CPU 3'. As a result, the CPU 3'again performs the abnormality check similar to the previous time in the section of time T3 following the section of time T2 and the section of time T4 following it.

This repetitive operation is repeatedly performed until the result of the abnormality check is "no abnormality". When it is determined that there is no abnormality, various control signals are created and output to the actuator.

[0012]

As described above, according to the present invention, in the case of a recoverable temporary abnormality, the system automatically returns to the normal state even when the ignition switch is on, so that the reliability of the system is improved. Is demonstrated.

[Brief description of drawings]

FIG. 1 is a circuit configuration block diagram showing an embodiment of an abnormality detection circuit of a microcomputer system according to the present invention.

FIG. 2 is an operation explanatory view of a main part of FIG.

FIG. 3 is a circuit configuration block diagram of a conventional circuit.

[Explanation of symbols]

 1 Battery 2 Ignition Switch 3, 3'CPU 4 Write / Read Memory 5 Read Only Memory 6 Microcomputer

Claims (1)

[Claims] 1. A writing / reading memory (4)
And a read-only memory (5), a microcomputer (3) for checking the write / read combined memory (4) and the read-only memory (5) in an initial state, and a runaway of the microcomputer (3) is detected. In the abnormality detection circuit of the microcomputer system including a watchdog timer that supplies a reset signal, the microcomputer (3) detects the abnormality of the writing / reading memory (4) and the read-only memory (5). An abnormality detection circuit for a microcomputer system, characterized in that an abnormality signal is supplied to the watchdog timer to repeatedly reset the microcomputer (3).