JPH0880810A - Power cut-off detecting device in equipment with security mechanism - Google Patents

Abstract

PURPOSE: To provide a power cut-off detecting device surely capable of detecting the generation of a power cut-off state in equipment with a security mechanism. CONSTITUTION: When power supply to-equipment is cut-off, a flip-flop circuit 8 is reset. Where the flip-flop circuit 8 is reset at the time of reset starting, judging that power supply was cut-off, a micro computer 2 executes a security process. After that, the computer 2 stores the result of the execution of the security process in an EEPROM 3 and then sets the flip-flop circuit 8. The security performance of the equipment is further improved by replacing the flip-flop circuit 8 with a shift resister or RAM comprising a plurality of bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting the occurrence of a power-off state in a device having a security mechanism for the purpose of preventing theft.

[0002]

2. Description of the Related Art In recent years, from the viewpoint of theft prevention, there is a tendency to install a security mechanism in in-vehicle devices such as car stereos. A code security method is a typical method for realizing such a security mechanism.
The vehicle-mounted device is generally realized as a microcomputer system, and is directly connected to a battery power source without a switch for the purpose of holding its memory. When the code security method detects that the power supply connection was once disconnected and then reconnected, it may have been stolen.Therefore, the security mode is entered and the code input is requested. If it is not, the microcomputer is configured so as not to start the operation. As described above, the reason why the security mode is entered when the power is turned on is that when the power line is cut off, the power supply for moving the security mechanism itself is also lost and the power cutoff determination process cannot be executed.

In addition, a device using a microcomputer system includes
Generally, in order to cancel a trouble state such as a runaway of a microcomputer, a reset switch for returning the microcomputer to the same state as when the power is turned on is often provided. That is, in response to the operation of such a reset switch, the microcomputer starts from the same instruction address as when the power was turned on.

If the reset mode is operated to shift to the security mode, it is troublesome to release the mode. In order to avoid this, it is necessary for the microcomputer to enter the security mode only when the power is turned on again by determining whether the power is turned on again or the reset switch is operated at reset start (rising). is there. Therefore, a microcomputer-controlled device with a security mechanism is provided with a configuration for detecting the occurrence of power cutoff immediately before starting.

FIG. 7 is a block diagram showing an example of such a conventional power disconnection detecting device. In this figure, reference numeral VB is a battery power source of, for example, 12V, reference numeral 1 is a connecting portion between the power supply VB and a microcomputer-controlled device having a security mechanism, and reference numeral 2 is a control center of the device and a determination for detecting power-off. A microcomputer for processing, reference numeral 3 is an EEPROM for storing data that needs to be retained even in a power-off state,
Reference numeral 4 is a waveform shaping circuit for shaping the waveform of the power source VB, reference numeral 5 is a delay circuit for delaying the output of the waveform shaping circuit 4 for a predetermined time, and reference numeral 6 is a microcomputer 2 from the power source VB.
A 5V generation circuit for generating 5V to be supplied to
Reference numeral 7 indicates a reset switch for resetting the microcomputer 2 in the same state as when the power was turned on.

The processing procedure at the time of starting the microcomputer 2 in FIG. 7 will be described with reference to the schematic flowchart of FIG. First, the power supply is interrupted by disconnection of the connecting portion 1, and the EEP
Since there is a possibility that the data other than those stored in the ROM 3 are destroyed, a predetermined initialization process is executed (step 802). Next, it is determined whether the output 51 of the delay circuit 5 is at low level (step 8).
04). If it is at a low level, it is found that the power supply was in a power-off state immediately before the start, and it can be determined that the power supply has been restarted. In that case, since theft may have occurred, the process proceeds to the security code input process as described above (step 80).
6). If it is not low level, it is determined that the start is caused by turning on the reset switch, and the code input process is omitted (step 808).

[0007]

However, the detection of power supply disconnection by such a configuration cannot necessarily realize the detection with certainty. That is,
The signal 51 for detecting the connection state of the power source is the power source VB.
Is a signal delayed to the extent that the output of the waveform is shaped and the microcomputer 2 started after power connection can read it as the power connection state immediately before start. Therefore, for example, when it is determined in step 804 that the power has been cut off, the process proceeds to step 806, and when the reset switch 7 is pressed at the time when the code input process is to be executed, the microcomputer 2 becomes the start state again, and the microcomputer 2 starts again. Steps 802 and 804 are executed, but at that time, the delay time capable of detecting the power-off has passed, it is judged that only the reset switch ON has occurred, and the normal operation is performed without executing the code input process. there is a possibility.
As described above, the conventional device does not guarantee a reliable security operation.

In view of the above situation, an object of the present invention is to provide a power cutoff detecting device capable of surely detecting the occurrence of a power cutoff state in a device with a security mechanism.

[0009]

In order to achieve the above object, the present invention adopts the technical constitution as described below. That is, the power-off detection device in a device with a security mechanism according to the present invention is a device for detecting that a power-off state has occurred in a device with a security mechanism, and the power supply to the device is cut off. And a power-off storage unit that destroys memory contents,
And a microcomputer that executes a predetermined security process by determining that the power is cut off when the stored contents of the power-off storage unit is destroyed at the time of reset start.

Further, according to the present invention, the power-off detection device further comprises a non-volatile memory, and the microcomputer stores the predetermined security processing execution result in the non-volatile memory, and then the power source. It is configured to set predetermined data in the disconnection storage unit.

Further, according to the present invention, the power-off storage unit is constituted by a plurality of bits.

Further, according to the present invention, the microcomputer monitors whether the stored contents of the power-off storage unit is destroyed in a predetermined cycle and issues a software reset when the contents are destroyed. Composed.

[0013]

In the power-off detecting device constructed as described above, the occurrence of the power-off state is surely stored in the power-off storage unit. In addition, by storing the security process execution result in the non-volatile memory and then setting predetermined data in the power-off storage unit, an erroneous determination is made even if the reset switch operation is performed after the determination at the start. Will disappear. Further, the power-off storage unit is configured to have a plurality of bits and is complicated, so that the security against malicious operations is improved. Further, the microcomputer monitors the stored contents of the power-off storage unit for a predetermined period and issues a software reset when the contents are destroyed, so that the power-off detection is performed but the microcomputer does Even when the computer is held for a long time and the microcomputer is not reset, it is possible to reliably detect the occurrence of power-off.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the hardware configuration of a power disconnection detecting apparatus according to the first embodiment of the present invention. In this figure, the same components as those of FIG. 7 according to the conventional example are designated by the same reference numerals, and the description thereof will be omitted. The difference from the conventional circuit (FIG. 7) is that a flip-flop 8 is used instead of the delay circuit 5 in the conventional circuit. This flip-flop 8
By inputting the output of the waveform shaping circuit 4 to the reset terminal R, the low level, that is, the disconnection of the power supply VB is detected to enter the reset state. Further, the flip-flop is in the reset state even when the power supply to itself is once cut off and then supplied again. That is, the reset state is entered by detecting both the momentary power-off state and the long-term power-off state. Naturally, the flip-flop 8 is not reset when the reset switch 7 is turned on.

The processing procedure at the time of start of the microcomputer 2 in the first embodiment having the hardware configuration of FIG. 1 will be described with reference to the flowchart of FIG. First, when the power is turned on or the reset switch is turned on, a predetermined initialization process is executed (step 102). Next, in order to confirm whether the security is set, the security flag stored in the EEPROM 3 is read and it is determined whether it is ON (step 104). If the security flag is OFF, the process described below is skipped. If the security flag is ON, that is, security is set, it is determined whether the flip-flop 8 is in the reset state (step 106). If it is in the set state, it can be determined that the power was not cut off,
The following processing is skipped. If it is in the reset state, the process proceeds to step 108.

At step 108, it is determined whether or not the power flag stored in the EEPROM 3 is ON. The power supply flag is a flag indicating that the security code input determination process was normally performed and the power supply was in an ON state before the start. If the power supply flag is OFF, it means that there is an abnormality, and the process proceeds to step 120 for error processing. If the power flag is ON, turn the power flag OFF.
Is written in the EEPROM 3 (step 110).
As a result, it is stored that the security code input determination process has not been performed since the power was turned on. Then, by activating the signal to the set input terminal S of the flip-flop 8, the flip-flop 8 is set (step 112).

After the flip-flop 8 is set, a predetermined process for prompting the input of the security code is executed (step 114). And the entered code is EEPROM
A determination process of whether or not it matches the expected value stored in No. 3 is executed (step 116). If they do not match, the process proceeds to step 120 for error processing. If they match, it is determined that the power is not cut off or reconnected due to theft, and at this point, the power flag is turned on, the number of retries N of the code input process is set to 0, and these are stored in the EEPROM 3 (step 11).
8) Then, shift to normal device control processing.

If it is determined in step 108 that the power flag is OFF, and if the security codes do not match in step 116, a predetermined error process is executed in step 120. Next, it is judged whether or not the current retry count N exceeds a predetermined allowable count P (step 122). If N> P, step 122
In, it falls into an infinite loop and becomes inoperable. If N ≦ P, the number of retries N is incremented and written in the EEPROM 3 to store N (step 124), and the process proceeds to the code input process of step 114.

In the first embodiment as described above, the fact that the power-off is detected is held as the reset state of the flip-flop 8, and the microcomputer 2 causes the flip-flop 8 to operate.
Since the reset state is read and then the set state is set, the power-off determination processing is reliably performed.

Next, a second embodiment of the present invention will be described. The second embodiment has the hardware configuration shown in FIG. 1 like the first embodiment, but the processing procedure is improved as shown in FIG. First in the flowchart of FIG.
The same steps as those in FIG. 2 according to the embodiment are given the same step numbers, and description thereof will be omitted. The difference is that the step of setting flip-flop 8 (112 in FIG. 2) is performed after step 118 in the second embodiment (step 2).
12). In this way, the EEP of the determination result of the power flag, etc.
By setting the flip-flop 8 after the writing to the ROM 3 is completed, an erroneous determination is not made even if the reset switch operation is performed after the determination.

That is, even if the reset switch is operated before writing to the EEPROM, since the flip-flop is not set, it is possible to surely detect and judge. Even if the reset switch is operated after writing to the EEPROM, since the flip-flop is not set, the same data is written, and no erroneous determination occurs. When the reset switch is operated after setting the flip-flop, it can be detected and determined as the reset switch operation.

Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing the hardware configuration of the power-off detection device according to the third embodiment, and FIG. 5 is a schematic flowchart showing the processing procedure at the start of the microcomputer in that case. As can be easily understood by comparing FIGS. 1 and 4, a shift register 9 is adopted in place of the flip-flop 8 in the third embodiment. The flowchart of FIG. 5 is different only in that steps 106 and 212 of FIG. 3 are changed to steps 306 and 312, respectively. Flip-flops are high (H) or low (L) judgments, so if you have some knowledge,
The flip-flop can be externally changed to the set state by a malicious operation, and the microcomputer 2 can be erroneously determined. Therefore, by writing and reading specific data composed of a plurality of bits in the shift register 9, the security against such malicious operation is improved. As the data in the register, for example, if a different code such as the serial number of the device is used for each device, the protection will be further ensured. A RAM having a certain number of bits may be used instead of the shift register.

Finally, a fourth embodiment will be described.
The first, second, and third embodiments described above are configured to be activated when the microcomputer 2 is reset by turning the power OFF-ON or operating the reset switch. Therefore, if the power-off detection is performed but the microcomputer is held for a long time and is not reset, the process is not executed. Therefore, as shown in FIG. 6, the power-off detection signal (the output signal of the flip-flop 8 in the first and second embodiments) is monitored at a predetermined cycle in the main routine (step 402), and the power-off is detected. If detected, the microcomputer issues a software reset (step 404). By doing so, the detection of power supply disconnection becomes more reliable.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, of course.
It will be easy for one skilled in the art to devise various embodiments.

[0026]

As described above, according to the present invention,
By providing the power-off storage unit as described above, it is possible to provide a power-off detection device capable of reliably detecting the occurrence of a power-off state in a device with a security mechanism. Further, by storing the security process execution result in the non-volatile memory and then setting the predetermined data in the power-off storage unit, an erroneous determination is made even if the reset switch operation is performed after the determination at the start. Will disappear. Also, by configuring the power-off storage unit to be composed of a plurality of bits and making it complicated,
Security against malicious operations is improved. That is, it becomes impossible to modify the stolen product and release the security. In addition, the microcomputer monitors whether the stored contents of the power-off storage unit is destroyed at a predetermined cycle and issues a software reset when the contents are destroyed, so that the microcomputer can be powered off instantaneously. Even if the power supply is not reset, it is possible to reliably detect the occurrence of the power cut. That is, it is possible to avoid a situation in which the contents of the memory are destroyed by a momentary power failure, but the microcomputer is not reset.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a power disconnection detection device according to a first embodiment of the present invention.

FIG. 2 is a schematic flow chart showing a processing procedure at the time of starting the microcomputer in the first embodiment of the present invention.

FIG. 3 is a schematic flowchart showing a processing procedure at the time of starting the microcomputer in the second embodiment of the present invention.

FIG. 4 is a block diagram showing a hardware configuration of a power disconnection detection device according to a third embodiment of the present invention.

FIG. 5 is a schematic flowchart showing a processing procedure at the time of starting the microcomputer in the third embodiment of the present invention.

FIG. 6 is a schematic flowchart showing a processing procedure of a main routine of a microcomputer according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a conventional power disconnection detection device.

8 is a schematic flowchart showing a processing procedure when the microcomputer in FIG. 7 is started.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Connection part of power supply and equipment 2 ... Microcomputer (microcomputer) 3 ... EEPROM 4 ... Waveform shaping circuit 5 ... Delay circuit 6 ... 5V generation circuit 7 ... Reset switch 8 ... Flip-flop 9 ... Shift register VB ... Battery power supply

Claims (4)

[Claims] 1. A device for detecting that a power-off state has occurred in a device having a security mechanism, the power-off storage unit destroying stored contents when power supply to the device is cut off, When the contents of the power-off storage unit are destroyed at the time of reset start, it is determined that the power has been turned off, and a microcomputer that executes a predetermined security process is provided. Power disconnection detection device for equipment with mechanism. 2. A non-volatile memory is further provided, and the microcomputer sets the predetermined data in the power-off storage unit after storing the predetermined security processing execution result in the non-volatile memory. The power cut detection device in the device with a security mechanism according to claim 1. 3. The power cut detection device in a device with a security mechanism according to claim 1, wherein the power cut storage unit includes a plurality of bits. 4. The microcomputer monitors the contents stored in the power-off storage unit for destruction at predetermined intervals, and issues a software reset when the contents are destroyed. The power-off detection device in a device with a security mechanism according to any one of claims 1 to 3.