JPH06326135A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To execute an annealing treatment safely and stably in the manufacturing method of a GaAs MESFET. CONSTITUTION:Si ions which are user to form a source/a drain and to form an active region are implanted, at respectively prescribed concentrations, into prescribed regions on the surface layer of a semiinsulating Gaps substrate 21 (a), (b). An annealing protective film 27 is formed on the Gaps substrate 21 by an ECR method, and the protective film 27 is impregnated with an organic solvent. After that, an annealing treatment is executed at a high temperature in a nitrogen atmosphere, the Si ions which have been implanted into the GaAs substrate 21 are activated, and N<+> type heavily doped regions 28, 29 to be used as a source/a drain and an N-type active region 30 are formed (c).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device having an active region in the surface layer of a semi-insulating compound semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, in GaAs compound semiconductors, the moving speed and drift speed of electrons are several times higher than that of Si.
It is known to be suitable for materials such as high speed switching devices. Among the devices using the GaAs compound semiconductor, a Schottky gate type field effect transistor (hereinafter referred to as “MESFET: ME”) has been put into practical use.
tal Semiconductor Field Effect Transistor ”).

FIG. 5 shows the basic structure of a GaAs MESFET. Referring to the figure, GaAs MESFET
Is sandwiched by N ⁺ -type impurity regions 2 and 3 which are source and drain formed at a predetermined interval on the surface layer of the semi-insulating GaAs substrate 1 and N ⁺ -type impurity regions 2 and 3. The formed N-type active region 4 is provided. N-type impurities such as Si are diffused in high concentration in the impurity regions 2 and 3, and N-type impurities such as Si are diffused in low concentration in the active region 4. The source and drain electrodes 5 and 6 are in ohmic contact with the impurity regions 2 and 3, and the gate electrode 7 is in Schottky contact with the active region 4. In addition, the entire surface of the GaAs substrate 1
The surface is covered with a passivation film 8 for protecting contaminants from the outside.

In the above structure, the voltage applied to the Schottky gate electrode 7 causes the Schottky gate electrode 7 and the Ga
The spread of the depletion layer 9 formed near the interface with the As substrate 1 can be controlled. This controls the current flowing between the source and the drain. In the method of manufacturing the GaAs MESFET, first, the photolithography technique is used to implant Si ions as N-type impurities into a predetermined region of the GaAs substrate at a predetermined concentration. After this ion implantation, annealing treatment is performed at a high temperature in an arsine (AsH ₃ ) gas atmosphere. by this,
The Si ions implanted in the GaAs substrate are activated and a pair of N ⁺ type impurity regions and N type active regions are formed.
After that, by using the lift-off method, ohmic electrodes for source and drain are sequentially formed on the impurity region, and a Schottky gate electrode is sequentially formed on the active region. Finally, the entire surface is covered with a passivation film.

[0005]

As described above, according to the conventional method of manufacturing a GaAs MESFET, the crystal damage of the substrate introduced at the time of ion implantation is recovered, and the implanted impurity is put in a correct lattice position to serve as a donor or an acceptor. Annealing is performed in an arsine gas atmosphere for activation. The reason why arsine gas is used at the time of annealing is that As in the GaAs substrate is blown out from the substrate surface when the annealing temperature is, for example, 800 ° C. or higher. Therefore, when the pressure is increased in the arsine gas atmosphere, As is saturated and filled in the atmosphere.
As does not fly out from the GaAs substrate.

However, since arsine gas is a very toxic gas, it must be handled with care, and the fact is that annealing must always be performed while confirming safety. In view of the above, it is an object of the present invention to provide a method for manufacturing a compound semiconductor device that can perform a safe and stable annealing process.

[0007]

[Means and Actions for Solving the Problems] Claim 1 of the present invention
The method for manufacturing the compound semiconductor device described above comprises a step of implanting impurity ions into a surface layer of a semi-insulating compound semiconductor substrate, a step of forming an annealing protective film on the compound semiconductor substrate by an electron cyclotron resonance method, and an annealing step. And activating the impurity ions injected into the surface layer of the compound semiconductor substrate to form an active region.

In the above manufacturing method, after the impurity ions for forming the active region are implanted, the annealing protective film is formed on the semi-insulating compound semiconductor substrate and annealing is performed. It is possible to prevent the compound component of (3) from escaping from the substrate surface. Therefore, annealing can be performed in a relatively non-toxic atmosphere such as nitrogen without using a highly toxic arsine gas.

Further, since the electron cyclotron resonance method is adopted as the film forming method of the annealing protection film, the annealing protection film can be formed at room temperature and the compound semiconductor substrate can be subjected to no thermal stress, resulting in high quality annealing. A protective film can be obtained. A method for manufacturing a compound semiconductor device according to a second aspect is the method for manufacturing a compound semiconductor device according to the first aspect, which includes a step of impregnating an organic solvent into an annealing protective film before annealing.

In the above manufacturing method, since the organic solvent is permeated into the annealing protective film, the solvent permeating into the protective film is decomposed during annealing, and carbon in the solvent simultaneously diffuses into the compound semiconductor substrate. The diffused carbon acts as a P-type impurity in the compound semiconductor substrate. Therefore, by making the concentration boundary between the P-type impurity and the N-type impurity clear, the current leaking to the substrate can be suppressed. As a result, the short channel effect can be suppressed, and good characteristics can be obtained as a compound semiconductor device.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. 1 to 3 are sectional views showing a method of manufacturing a compound semiconductor device according to an embodiment of the present invention in the order of steps. In this embodiment, a GaAs MESFET is formed. Referring to these figures, the GaAsM of this embodiment
In the ESFET manufacturing method, first, impurity ions for forming a source and a drain are implanted. That is, as shown in FIG. 1A, a resist 24 having a pair of windows 22 and 23 at a predetermined interval on the surface of the semi-insulating GaAs substrate 21.
To form a pattern. Then, using this resist 24 as a mask, Si as an N-type impurity is formed on the GaAs substrate 21.
Ions are implanted at a high concentration. At this point, the resist 24 used as the mask has already been used and is peeled off.

When the ion implantation process for forming the source and drain is completed, impurity ions for forming the active region are implanted. That is, as shown in FIG. 1B, a resist 26 having a window 25 corresponding to an active region where an element is to be formed is patterned on the surface of the GaAs substrate 21. Then, using the resist 26 as a mask, the GaAs substrate 2
1 is implanted with Si ions as N-type impurities at a low concentration. At this point, the resist 26 used as the mask is
Since it has already been used, peel it off.

When the ion implantation process for forming the active region is completed, annealing is performed. That is, as shown in FIG. 1C, electron cyclotron resonance (hereinafter referred to as “ECR: Elec
tronCycrotron Resonance ”method.
For example, an Si ₃ N ₄ film is deposited on the s substrate 21 in an amount of 200 Å to form an annealing protection film 27. ECR is a method in which microwaves (2.45 GHz) are guided to a plasma excitation chamber by a waveguide to generate active species, and the active species are guided to a reaction chamber to form a film. Specifically, a magnetic field (875 G) satisfying the electron cyclotron resonance condition is formed in the plasma excitation chamber, and plasma is drawn out to the substrate surface by the divergent magnetic field to form a film. After forming the annealing protective film 27, an organic solvent is permeated into the protective film 27. As the organic solvent, a solution containing a methyl group in its molecular structure such as methyl alcohol or tetraammonium hydroxide is preferable. Then, about 8 in nitrogen atmosphere
Annealing is performed at a high temperature of 00 ° C. Then G
The Si ions implanted in the aAs substrate 21 are activated,
N ⁺ type high-concentration impurity region 2 serving as a source and a drain
8, 29 and the N-type active region 30 are formed.

When the annealing process is completed, ohmic electrodes for source and drain are formed. That is, FIG.
As shown in (a), a resist 31 is patterned on the annealing protection film 27. Subsequently, reverse tapered windows 32 and 33 are formed directly above the N ⁺ type high concentration impurity regions 28 and 29 by RIE (Reactive Ion Etching) using CHF ₃ / O ₂ gas. In this state, GaAs substrate 2
Towards 1, deposit vertical ohmic metal. In order to vertically deposit the ohmic metal, for example, an electron beam heating type vapor deposition method or a resistance heating type vapor deposition method may be used. The ohmic metal layer is, for example, AuGe (for example, 400
It is a film having a two-layer structure in which 0Å) is deposited and Ni (for example, 50Å) is deposited on the upper layer. Then, the resist 31 and the ohmic metal on the resist 31 are removed by the lift-off method. Further, the ohmic metal remaining on the GaAs substrate 21 is sintered. Then, Figure 2
As shown in (b), N ⁺ -type high-concentration impurity regions 28, 2
Source / drain electrodes 34, 3 in ohmic contact with
5 is formed. Sintering for making ohmic contact can be performed, for example, by performing alloying treatment in a nitrogen atmosphere at a temperature of about 450 ° C. for about 5 minutes.

When the source / drain electrode forming step is completed, a Schottky gate electrode is formed. That is, as shown in FIG. 2C, a resist 36 is patterned on the annealing protection film 27. Subsequently, an inversely tapered window 37 is formed directly above the N-type active region 30 by RIE using CHF ₃ / O ₂ gas. In this state, the gate metal is vapor-deposited on the GaAs substrate 21 by the vertical vapor deposition method. The gate metal layer is, for example, Ti (for example, 500
Å), Pt (eg, 500 Å) in the middle layer, and Au (eg, 4500 Å) in the upper layer. Then, the gate metal on the resist 36 is removed together with the resist 36 by the lift-off method. Then, Figure 3
As shown in (a), a gate metal 38 is formed in Schottky contact with the N-type active region 30.

When the gate electrode formation is completed, a passivation film is formed. That is, after performing a predetermined metallization, as shown in FIG.
An SG or Si ₃ N ₄ film is deposited to form a passivation film 39.
To form. In the above-mentioned manufacturing method, after each impurity ion (Si ion) for forming the N ⁺ type high concentration impurity regions 28 and 29 and the N type active region 30 is implanted, GaA
Since the annealing protection film 27 is formed on the s substrate 21 and annealing is performed, As in the GaAs substrate 21 can be prevented from coming off from the substrate surface during annealing. Therefore, it becomes possible to perform annealing in a relatively non-toxic atmosphere such as nitrogen without using a very toxic arsine gas.

Further, since the ECR method is adopted as the film forming method of the annealing protection film 27, the annealing protection film 2 is formed at room temperature.
7 can be formed, and thermal stress is not applied to the GaAs substrate 21. As a result, a high quality annealing protection film 27 can be obtained. Furthermore, since the organic solvent containing a methyl group in the molecular structure such as methyl alcohol or tetraammonium hydroxide is permeated into the annealing protective film 27 before annealing, the methyl group of the solvent permeating into the protective film 27 is annealed. It is sometimes decomposed and carbon simultaneously diffuses into the GaAs substrate 21. The diffused carbon is
In the GaAs substrate 21, it acts as a P-type impurity. Therefore, like the impurity distribution profile shown in FIG.
It is possible to suppress the tailing of N-type impurities (Si) that are originally implanted ions. That is, the concentration boundary between the P-type impurity and the N-type impurity shown by X in the figure becomes clear. Therefore, as a result of suppressing the current leaking to the substrate, the short channel effect can be suppressed, so that good characteristics as an FET can be obtained.

From the above, a safe and stable annealing process can be performed. The present invention is not limited to the above embodiment, and many modifications and changes can be made within the scope of the present invention. In the above embodiment, the example in which the Si ₃ N ₄ film is used as the annealing protection film has been described, but SiO ₂ or SiO _x N _y may be used as the annealing protection film.

In the above embodiment, the present invention is based on GaAs.
Although the example applied to the FET has been described, it is needless to say that the invention can be widely applied to other compound semiconductor devices having a structure in which an active region is formed in the surface layer of a semi-insulating compound semiconductor substrate, such as a GaAs diode.

[0020]

As is apparent from the above description, according to the manufacturing method of the first aspect of the present invention, the annealing protective film can prevent the compound component in the compound semiconductor substrate from coming out from the substrate surface during annealing. Annealing can be performed in a relatively non-toxic atmosphere such as nitrogen without using a very toxic arsine gas.

Further, by the electron cyclotron resonance method,
The annealing protective film can be formed at room temperature, and the compound semiconductor substrate need not be subjected to thermal stress. As a result, a high quality annealing protective film can be obtained. According to the manufacturing method of claim 2, the organic solvent that has penetrated into the protective film is decomposed during annealing, carbon in the solvent is simultaneously diffused into the compound semiconductor substrate, and the diffused carbon is a P-type impurity in the compound semiconductor substrate. , The concentration boundary between the P-type impurity and the N-type impurity becomes clear. Therefore, as a result of suppressing the current leaking to the substrate, the short channel effect can be suppressed,
Good characteristics can be obtained as a compound semiconductor device.

From the above, there is an excellent effect that a safe and stable annealing process can be performed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a compound semiconductor device according to an embodiment of the present invention in the order of steps.

2A to 2D are cross-sectional views showing a method of manufacturing the compound semiconductor device following FIG. 1 in order of steps.

3A to 3C are cross-sectional views showing the method of manufacturing the compound semiconductor device continued from FIG.

FIG. 4 is a diagram showing an impurity distribution profile.

FIG. 5 is a diagram showing a basic configuration of a GaAs MESFET.

[Explanation of symbols]

21 semi-insulating GaAs substrate 27 annealing protection film 28, 29 N ⁺ type impurity region 30 N type active region

Claims (2)

[Claims] 1. A step of implanting impurity ions into a surface layer of a semi-insulating compound semiconductor substrate, a step of forming an annealing protective film on the compound semiconductor substrate by an electron cyclotron resonance method, and an annealing process to obtain the compound semiconductor. A method of manufacturing a compound semiconductor device, comprising the step of activating impurity ions implanted in a surface layer of a substrate to form an active region. 2. The method for manufacturing a compound semiconductor device according to claim 1, comprising a step of impregnating an annealing solvent with an organic solvent before annealing.