JPH06318547A - Compound semiconductor epitaxial wafer - Google Patents

Compound semiconductor epitaxial wafer

Info

Publication number
JPH06318547A
JPH06318547A JP10561993A JP10561993A JPH06318547A JP H06318547 A JPH06318547 A JP H06318547A JP 10561993 A JP10561993 A JP 10561993A JP 10561993 A JP10561993 A JP 10561993A JP H06318547 A JPH06318547 A JP H06318547A
Authority
JP
Japan
Prior art keywords
fet
substrate
epitaxial wafer
semi
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10561993A
Other languages
Japanese (ja)
Inventor
Yukio Sasaki
幸男 佐々木
Youhei Otogi
洋平 乙木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP10561993A priority Critical patent/JPH06318547A/en
Publication of JPH06318547A publication Critical patent/JPH06318547A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To remarkably increase mutual conductance gm of an FET. CONSTITUTION:A leak current of a substrate is suppressed and good mutual conductance gm characteristic can be obtained by forming an FET from an epitaxial wafer where i-GaAs layer 2, n-GaAs layer 3, n<+>-GaAs layer 4, for example, are grown on the surface of a semi-insulated GaAs substrate 1 including carbon of the concentratmon of 0.2 to 2X10<16>cm<-3>.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、化合物半導体特にGa
As系のエピタキシャルウェハに関するものである。
BACKGROUND OF THE INVENTION The present invention relates to a compound semiconductor, especially Ga.
The present invention relates to an As-based epitaxial wafer.

【0002】[0002]

【従来の技術】従来、使用されてきた半絶縁性GaAs
基板は、抵抗率で1〜6×107 Ω・cm、炭素濃度と
しては0.2〜2×1015cm-3のものが大部分であっ
た。それ以上抵抗率が高く、炭素濃度が高いものは、S
iイオンを打ち込んだ後の活性化率が悪い事から使われ
ていなかった。また、炭素を均一に添付する技術も開発
されていなかった事とも使用されていなかった理由の一
つである。一方、半絶縁性GaAs基板上にエピタキシ
ャル成長したウェハを用いて、最近、移動帯無線用のパ
ワーFET(Field Effect Transi
stor)の開発が進んでいる。この素子は、数十mA
の電流を流し、数十mWの出力を得ようというもので、
アンドープのバッファ層や、半絶縁性基板のリーク電流
が多いと、しきい値電圧が深くなり、このためFETの
重要特性である相互コンダクタンスgmが低下してしま
う。
2. Description of the Related Art Semi-insulating GaAs which has been used conventionally
Most of the substrates had a resistivity of 1 to 6 × 10 7 Ω · cm and a carbon concentration of 0.2 to 2 × 10 15 cm −3 . If the resistivity is higher and the carbon concentration is higher than that, S
It was not used because the activation rate after implanting i-ions was poor. Moreover, it is one of the reasons that the technology for uniformly attaching carbon has not been developed and has not been used. On the other hand, recently, using a wafer epitaxially grown on a semi-insulating GaAs substrate, a power FET (Field Effect Transistor) for mobile band wireless communication has been recently used.
(stor) is under development. This element is several tens mA
The current of about 10 mW is applied to obtain the output of
If there is a large amount of leak current in the undoped buffer layer or the semi-insulating substrate, the threshold voltage becomes deep, and therefore the transconductance gm, which is an important characteristic of the FET, decreases.

【0003】前述した抵抗率の1〜6×107 Ω・cm
の半絶縁性基板を使用した場合のしきい値電圧の様子を
図3に示す。なお、評価したエピタキシャルウェハを、
図1に、図1のエピタキシャルウェハから作製したFE
T構造を図2に示す。図1、図2において、1は半絶縁
性GaAs基板、2はi−GaAs層、3はn−GaA
s層、4はn+ −GaAs層、5はソース電極、6はゲ
ート電極、7はドレイン電極である。なお図2のFET
はゲート長1μm、ゲート幅10mmである。図3から
わかるように、基板の抵抗率が高い方が、しきい値電圧
が浅くなる傾向があるが、従来のものは曲線A、Bのよ
うにまだリーク電流が多く、満足がいくFETの特性が
得られなかった。
The above-mentioned resistivity of 1 to 6 × 10 7 Ω · cm
FIG. 3 shows the state of the threshold voltage when the semi-insulating substrate of 1 is used. In addition, the evaluated epitaxial wafer,
FIG. 1 shows an FE manufactured from the epitaxial wafer of FIG.
The T structure is shown in FIG. 1 and 2, 1 is a semi-insulating GaAs substrate, 2 is an i-GaAs layer, and 3 is n-GaA.
s layer, 4 is an n + -GaAs layer, 5 is a source electrode, 6 is a gate electrode, and 7 is a drain electrode. The FET of FIG. 2
Has a gate length of 1 μm and a gate width of 10 mm. As can be seen from FIG. 3, the higher the substrate resistivity, the shallower the threshold voltage tends to be. However, the conventional one has a large leak current as shown by curves A and B, and is satisfactory for the FET. The characteristics were not obtained.

【0004】[0004]

【発明が解決しようとする課題】前述の通り、抵抗率1
〜6×107 Ω・cmの半絶縁性基板上にエピタキシャ
ル成長させ、FETを作製した場合リーク電流が大き
く、しきい値電圧が設計値より深くなり、FETの要求
特性を満足しないという問題点があった。
As described above, the resistivity is 1
When a FET is produced by epitaxially growing it on a semi-insulating substrate of ˜6 × 10 7 Ω · cm, the leak current is large, the threshold voltage becomes deeper than the design value, and there are problems that the required characteristics of the FET are not satisfied. there were.

【0005】本発明の目的は、前記した従来技術の課題
を解消し、FETの相互コンダクタンスgmを大幅に増
加させることができる半絶縁性GaAs基板を用いた化
合物半導体エピタキシャルウェハを提供することにあ
る。
An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a compound semiconductor epitaxial wafer using a semi-insulating GaAs substrate capable of significantly increasing the transconductance gm of FET. .

【0006】[0006]

【課題を解決するための手段】本発明の要旨は、エピタ
キシャル成長するための半絶縁性GaAs基板として炭
素濃度が0.2〜2×1016cm-3のものを用いたこと
にあり、これによって基板のリーク電流を大幅に減少さ
せたことにある。
The gist of the present invention resides in the use of a semi-insulating GaAs substrate having a carbon concentration of 0.2 to 2 × 10 16 cm -3 for epitaxial growth. The reason is that the leakage current of the substrate is greatly reduced.

【0007】[0007]

【作用】[Action]

(1) 抵抗率を高くするためのアクセプタとしては、炭素
以外に亜鉛、ベリリウム等が考えられるが、これらの原
素は、プロセス中での熱処理により、拡散してしまうの
で、急峻な界面が得られない。このため、炭素が最も扱
い易く、0.2〜2×1016cm-3の濃度において、効
果が高い。
(1) As acceptors for increasing the resistivity, zinc, beryllium, etc. can be considered in addition to carbon, but since these elements are diffused by the heat treatment in the process, a sharp interface is obtained. I can't. Therefore, carbon is the easiest to handle, and the effect is high at a concentration of 0.2 to 2 × 10 16 cm −3 .

【0008】なお、炭素濃度を0.2〜2×1016cm
-3とすることによりリーク電流が少なくなることについ
ては、特願平3−260779で詳述している通りであ
る。
The carbon concentration is 0.2 to 2 × 10 16 cm
As described in detail in Japanese Patent Application No. 3-260779, the leakage current is reduced by setting -3 .

【0009】(2) 炭素濃度0.2〜2×1016cm-3
対応して、半絶縁性GaAsの抵抗率は0.6〜10×
108 Ω・cmとする。6×107 Ω・cm以下のGa
As基板を用いると、リーク電流の抑止効果は小さい。
また1×109 Ω・cmを越えると、p型に反転してし
まう。
(2) Corresponding to a carbon concentration of 0.2 to 2 × 10 16 cm -3 , the resistivity of semi-insulating GaAs is 0.6 to 10 ×.
10 8 Ω · cm. Ga of 6 × 10 7 Ω · cm or less
If an As substrate is used, the effect of suppressing leakage current is small.
Further, when it exceeds 1 × 10 9 Ω · cm, it inverts to p-type.

【0010】[0010]

【実施例】【Example】

〔実施例1〕基板として、炭素濃度3.0×1015cm
-3、抵抗率1×108 Ω・cmの半絶縁性GaAs基板
を使用し、有機金属気相エピタキシャル成長(MOVP
E)法により、従来と同様に図1に示す構造のエピタキ
シャルウェハを形成し、このエピタキシャルウェハを用
い、従来と同様に図2に示す構造のFETを作製した。
このとき√(Ids)とVgsの関係を図3に示す。図
3の曲線Cの通りリーク電流は抑止されており、要求特
性を満足する、パワーFETが得られた。
[Example 1] A substrate having a carbon concentration of 3.0 x 10 15 cm
-3 , using a semi-insulating GaAs substrate with a resistivity of 1 × 10 8 Ω · cm, metal organic vapor phase epitaxial growth (MOVP)
By the E) method, an epitaxial wafer having the structure shown in FIG. 1 was formed similarly to the conventional method, and using this epitaxial wafer, an FET having the structure shown in FIG. 2 was manufactured similarly to the conventional method.
At this time, the relationship between √ (Ids) and Vgs is shown in FIG. As shown by the curve C in FIG. 3, the leak current is suppressed, and a power FET satisfying the required characteristics was obtained.

【0011】〔実施例2〕基板として炭素濃度7.0×
1015cm-3、抵抗率3×108 Ω・cmの半絶縁性G
aAs基板を使用し、実施例1と同じ条件でFETを作
製した。その結果、図3の曲線Dの通り実施例1と同様
満足するFETが得られた。
Example 2 A substrate having a carbon concentration of 7.0 ×
Semi-insulating G with 10 15 cm -3 and resistivity 3 × 10 8 Ω · cm
An FET was produced under the same conditions as in Example 1 using the aAs substrate. As a result, as shown by the curve D in FIG. 3, a FET which satisfies the same conditions as in Example 1 was obtained.

【0012】〔比較例1〕基板として、炭素濃度2.2
×1014cm-3、抵抗率1×107 Ω・cmの半絶縁性
GaAs基板を使用し、実施例1と同じ条件でFETを
作製した。その結果、図3の曲線Aのようにかなり、リ
ーク電流が多く、しきい値電圧が深くなり、満足する相
互コンダクタンスgmの特性が得られなかった。
Comparative Example 1 A substrate having a carbon concentration of 2.2
× 10 14 cm -3, use the semi-insulating GaAs substrate of resistivity of 1 × 10 7 Ω · cm, were fabricated FET under the same conditions as in Example 1. As a result, as shown by the curve A in FIG. 3, the leak current was considerably large, the threshold voltage was deep, and a satisfactory mutual conductance gm characteristic could not be obtained.

【0013】〔比較例2〕基板として、炭素濃度1.7
×1015cm-3、抵抗率5×107 Ω・cmの半絶縁性
GaAs基板を使用し、実施例1と同じ条件でFETを
作製した。その結果、図3の曲線Bの通り、比較例1よ
りは多少リーク電流は少ないが、まだ満足がいく結果は
得られなかった。
[Comparative Example 2] A substrate having a carbon concentration of 1.7
× 10 15 cm -3, use the semi-insulating GaAs substrate resistivity 5 × 10 7 Ω · cm, were fabricated FET under the same conditions as in Example 1. As a result, as shown by the curve B in FIG. 3, although the leak current was slightly smaller than that in Comparative Example 1, satisfactory results could not be obtained.

【0014】なお、上記実施例は、有機金属気相成長
(MOVPE)法で行ったが、分子線エピタキシャル
(MBE)法、あるいは単なる気相エピタキシャル(V
PE)法で成長しても、効果は同じと考えられる。
Although the above-mentioned embodiment was carried out by the metal organic chemical vapor deposition (MOVPE) method, the molecular beam epitaxy (MBE) method or the simple vapor phase epitaxy (VE) method was used.
It is considered that the same effect can be obtained even when grown by the PE method.

【0015】また、FETを作る別な手法として、半絶
縁性GaAs基板にSiイオンを打込んでアニールする
方法が、この方法でも、高抵抗の基板を用いると同様な
効果がある。
As another method of making an FET, a method of implanting Si ions into a semi-insulating GaAs substrate and annealing is also effective in this method as well when a high resistance substrate is used.

【0016】[0016]

【発明の効果】本発明によれば基板リーク電流の抑止に
よりGaAsパワーFETなどの大電流を流すFETが
作製可能となる。また、通常のローノイズFETに適用
した場合も同様に特性が向上する。
According to the present invention, an FET such as a GaAs power FET that allows a large current to flow can be manufactured by suppressing the substrate leakage current. Also, when applied to a normal low noise FET, the characteristics are similarly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】FET用のエピタキシャルウェハ構造を示す断
面図である。
FIG. 1 is a sectional view showing an epitaxial wafer structure for an FET.

【図2】図1のエピタキシャルウェハから作製したFE
T構造を示す説明図である。
2 is an FE produced from the epitaxial wafer of FIG.
It is explanatory drawing which shows T structure.

【図3】図2のFETおける√(Ids)とVgsとの
関係を示す説明図である。
FIG. 3 is an explanatory diagram showing a relationship between √ (Ids) and Vgs in the FET of FIG.

【符号の説明】[Explanation of symbols]

1 半絶縁性GaAs基板 2 i−GaAs基板 3 n−GaAs層 4 n+ −GaAs層1 Semi-insulating GaAs substrate 2 i-GaAs substrate 3 n-GaAs layer 4 n + -GaAs layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】炭素濃度が0.2〜2×1016cm-3の半
絶縁性GaAs基板の上に複数の化合物半導体薄膜が形
成されていることを特徴とする、化合物半導体エピタキ
シャルウェハ。
1. A compound semiconductor epitaxial wafer having a plurality of compound semiconductor thin films formed on a semi-insulating GaAs substrate having a carbon concentration of 0.2 to 2 × 10 16 cm −3 .
【請求項2】請求項1において、GaAs基板の抵抗率
が0.6〜10×108 Ω・cmであることを特徴とす
る化合物半導体エピタキシャルウェハ。
2. A compound semiconductor epitaxial wafer according to claim 1, wherein the GaAs substrate has a resistivity of 0.6 to 10 × 10 8 Ω · cm.
JP10561993A 1993-05-06 1993-05-06 Compound semiconductor epitaxial wafer Pending JPH06318547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10561993A JPH06318547A (en) 1993-05-06 1993-05-06 Compound semiconductor epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10561993A JPH06318547A (en) 1993-05-06 1993-05-06 Compound semiconductor epitaxial wafer

Publications (1)

Publication Number Publication Date
JPH06318547A true JPH06318547A (en) 1994-11-15

Family

ID=14412514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10561993A Pending JPH06318547A (en) 1993-05-06 1993-05-06 Compound semiconductor epitaxial wafer

Country Status (1)

Country Link
JP (1) JPH06318547A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278857A (en) * 2005-03-30 2006-10-12 Ngk Insulators Ltd Semiconductor laminate structure, semiconductor device, and equipment using the same
CN105185900A (en) * 2014-06-17 2015-12-23 旭化成微电子株式会社 Hall sensor
JP2016004918A (en) * 2014-06-17 2016-01-12 旭化成エレクトロニクス株式会社 Hall sensor
JP2016021549A (en) * 2014-06-17 2016-02-04 旭化成エレクトロニクス株式会社 Hall sensor
JP2017005017A (en) * 2015-06-05 2017-01-05 旭化成エレクトロニクス株式会社 Hall sensor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278857A (en) * 2005-03-30 2006-10-12 Ngk Insulators Ltd Semiconductor laminate structure, semiconductor device, and equipment using the same
CN105185900A (en) * 2014-06-17 2015-12-23 旭化成微电子株式会社 Hall sensor
JP2016004918A (en) * 2014-06-17 2016-01-12 旭化成エレクトロニクス株式会社 Hall sensor
JP2016021549A (en) * 2014-06-17 2016-02-04 旭化成エレクトロニクス株式会社 Hall sensor
JP2017120927A (en) * 2014-06-17 2017-07-06 旭化成エレクトロニクス株式会社 Hall sensor
CN107195772A (en) * 2014-06-17 2017-09-22 旭化成微电子株式会社 Hall sensor
JP2018137470A (en) * 2014-06-17 2018-08-30 旭化成エレクトロニクス株式会社 Hall sensor
CN107195772B (en) * 2014-06-17 2019-06-25 旭化成微电子株式会社 Hall sensor
JP2017005017A (en) * 2015-06-05 2017-01-05 旭化成エレクトロニクス株式会社 Hall sensor

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