JPH0631733Y2 - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH0631733Y2 JPH0631733Y2 JP8767587U JP8767587U JPH0631733Y2 JP H0631733 Y2 JPH0631733 Y2 JP H0631733Y2 JP 8767587 U JP8767587 U JP 8767587U JP 8767587 U JP8767587 U JP 8767587U JP H0631733 Y2 JPH0631733 Y2 JP H0631733Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- inspection
- printed wiring
- wiring board
- reference point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Testing Of Individual Semiconductor Devices (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は表面実装型集積回路を搭載する印刷配線板に関
し、特に集積回路接続用パッドと検査用ランドとを接続
する回路パターンを有する印刷配線板に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a printed wiring board on which a surface mount type integrated circuit is mounted, and in particular, a printed wiring having a circuit pattern for connecting an integrated circuit connecting pad and an inspection land. Regarding the board.
第２図は従来印刷配線板上の集積回路接続用パッドと検
査用ランドとを接続する回路パターン図である。FIG. 2 is a circuit pattern diagram for connecting an integrated circuit connecting pad and an inspection land on a conventional printed wiring board.
従来、このように実装密度及び回路パターンが高密度化
した表面実装型集積回路の搭載に用いられる印刷配線板
上のパターンは集積回路接続用パッド１と検査用ランド
３とを設計基準の指示どおりに回路パターン２で接続し
ている。Conventionally, a pattern on a printed wiring board used for mounting a surface mounting type integrated circuit in which the packaging density and the circuit pattern are highly densified as described above includes an integrated circuit connecting pad 1 and an inspection land 3 as instructed by a design standard. To the circuit pattern 2.
上述した従来の表面実装集積回路の搭載に用いられる印
刷配線板上の集積回路接続用パッドと検査用ランドとを
接続する回路パターンは、汎用型布線検査機を使用する
ために検査用ランドを基準点よりＸ，Ｙ方向ともに２．
５４mm間隔で整数倍した位置（以下、２．５４mm格子上
と記す）に載せると集積回路接続用パッドと検査用ラン
ドまでの距離が長くなるので実装密度が上がらないとい
う欠点がある。また従来の集積回路接続用パッドと検査
用パッドとを接続する回路パターンの幅は設計基準の指
示により他の信号ラインと同じ幅を使用しているので、
集積回路接続用パッドと検査用ランドの間も布線検査を
行う必要があるという欠点をも有する。The circuit pattern for connecting the integrated circuit connection pad and the inspection land on the printed wiring board used for mounting the above-mentioned conventional surface mount integrated circuit has the inspection land for using the general-purpose wiring inspection machine. Both X and Y directions from the reference point 2.
If it is placed at a position that is an integer multiple at 54 mm intervals (hereinafter referred to as 2.54 mm on the grid), the distance between the integrated circuit connection pad and the inspection land becomes long, so that there is a drawback that the packaging density cannot be increased. Since the width of the circuit pattern connecting the conventional integrated circuit connection pad and the inspection pad is the same as that of the other signal line according to the instruction of the design standard,
It also has a drawback that a wiring inspection needs to be performed between the integrated circuit connecting pad and the inspection land.
本考案の目的は、上述の欠点を解決した表面実装型集積
回路を搭載する印刷配線板を提供することである。An object of the present invention is to provide a printed wiring board mounting a surface mount type integrated circuit which solves the above-mentioned drawbacks.
本考案によれば、１３２ピンの（端子ピッチ０．６５m
m）を搭載する印刷配線板において、集積回路の各ピン
の近くに基準点よりＸ，Ｙ方向ともに２．５４mm間隔で
整数倍した位置に配した検査用のランドを有し、検査用
ランドと集積回路接続用パッドを結ぶ回路パターンの幅
が最大０．２５mmで、回路最小間隙が０．３３５mmであ
り、前記集積回路接続用パッドより外側へ引き出された
前記回路パターンに接続した前記検査ランドの前記基準
点より遠方の前記検査用ランドのみを結んだ仮想外周線
の内側の面積が２５．８１cm2以下であることを特徴と
するパターンを有する印刷配線板が得られる。According to the present invention, 132-pin (terminal pitch 0.65 m
In the printed wiring board on which m) is mounted, there are inspection lands arranged near the pins of the integrated circuit at integer multiples at 2.54 mm intervals in both the X and Y directions from the reference point. The width of the circuit pattern connecting the integrated circuit connecting pads is 0.25 mm at maximum and the circuit minimum gap is 0.335 mm, and the inspection lands connected to the circuit pattern drawn out from the integrated circuit connecting pad are connected. A printed wiring board having a pattern characterized in that the area inside the virtual outer peripheral line connecting only the inspection lands far from the reference point is 25.81 cm 2 or less is obtained.
すなわち、本考案によれば上述した従来の表面実装型集
積回路の搭載に用いられる印刷配線板上の集積回路接続
用パッドと検査用ランドとを接続する回路パターンに対
し、数種の格子を使用して集積回路接続用パッドと検査
用ランドとの距離を短くすることができるので印刷配線
基板の実装密度を上げることが可能となる。That is, according to the present invention, several kinds of grids are used for the circuit pattern for connecting the integrated circuit connection pad and the inspection land on the printed wiring board used for mounting the above-mentioned conventional surface mount type integrated circuit. Since the distance between the integrated circuit connecting pad and the inspection land can be shortened, the mounting density of the printed wiring board can be increased.
以下、図面を参照して本考案を詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図は本考案の一実施例を示す印刷配線板上の集積回
路接続用パッドと検査用ランドとを接続する回路パター
ン図である。FIG. 1 is a circuit pattern diagram for connecting an integrated circuit connecting pad and an inspection land on a printed wiring board according to an embodiment of the present invention.
第１図において、１は集積回路接続用パッドであり、基
準点４を中心として左右上下にそれぞれ３３個ずつ並ん
でいる。集積回路接続用パッド１の各々の間隔は０．６
５mmとなっている。集積回路接続用パッド１の外側に検
査用ランド３が２列にそれぞれ２．５４mm格子上に載っ
て並んでいる。集積回路接続用パッド１の中心を始点座
標とし、検査用ランド３の中心を終点座標として回路パ
ターン２が接続されている。次に基準点４を原点座標
（００，００）として始点・屈曲点終点の座標値を示
す。単位はそれぞれミリメートルである。In FIG. 1, 1 is a pad for connecting an integrated circuit, and 33 pads are arranged on the left, right, top and bottom around the reference point 4. The distance between the integrated circuit connecting pads 1 is 0.6.
It is 5 mm. Outside the integrated circuit connection pad 1, the inspection lands 3 are arranged in two rows on a 2.54 mm grid. The circuit pattern 2 is connected with the center of the integrated circuit connecting pad 1 as the starting point coordinate and the center of the inspection land 3 as the ending point coordinate. Next, with reference point 4 as the origin coordinate (00,00), the coordinate values of the start point and the bending point end point are shown. The unit is millimeter.
(1) （-10.4,15.34）→（-10.4,16.828）→（-20.32,2
2.225）→（-20.32,2.86） (2) （-9.75,15.34）→（-9.75,17.146）→（-19.05,2
2.225）→（-19.05,23.495）→（-17.78,24.766）→（-
17.78,25.4） (3) （-9.1,15.34）→（-9.1,17.463）→（-17.78,22.
225）→（-17.78,22.86） (4) （-8.45,15.34）→（-8.45,17.781）→（-16.51,2
2.225）→（-16.51,23.495）→（-15.24,24.766）→（-
15.24,25.4） (5) （-7.8,15.34）→（-7.8,18.098）→（-15.24,22.
225）→（-15.24,22.86） (6) （-7.15,15.34）→（-7.15,18.416）→（-13.97,2
2.225）→（-13.97,23.495）→（-12.7,24.766）→（-1
2.7,25.4） (7) （-6.5,15.34）→（-6.5,18.733）→（-12.7,22.2
25）→（-12.7,22.86） (8) （-5.85,15.34）→（-5.85,19.051）→（-11.43,2
2.225）→（-11.43,23.495）→（-10.16,24.766）→（-
10.16,25.4） (9) （-5.2,15.34）→（-5.2,19.368）→（-10.16,22.
225）→（-10.16,22.86） (10) （-4.55,15.34）→（-4.55,19.686）→（-8.89,2
2.225）→（-8.89,23.495）→（-7.62,24.766）→（-7.
62,25.4） (11) （-3.9,15.34）→（-3.9,20.003）→（-7.62,22.
225）→（-7.62,22.86） (12) （-3.25,15.34）→（-3.25,20.321）→（-6.35,2
2.225）→（-6.35,23.496）→（-5.08,24.766）→（-5.
08,25.4） (13) （-2.6,15.34）→（-2.6,20.638）→（-5.08,22.
225）→（-5.08,22.86） (14) （-1.95,15.34）→（-1.95,20.956）→（-3.81,2
2.225）→（3.81,23.496）→（-2.54,24.766）→（-2.5
4,25.4） (15) （-1.3,15.34）→（-1.3,21.273）→（-2.54,22.
225）→（-2.54,22.86） (16) （-0.65,15.34）→（-0.65,21.591）→（-1.27,2
2.225）→（-1.27,23.496）→（0.0,24.766）→（0.0,2
5.4） (17) （0.0,15.34）→（0.0,22.86） (18) （0.65,15.34）→（0.65,21.591）→（1.27,22.2
25）→（1.27,23.496）→（2.54,24.766）→（2.54,25.
4） (19) （1.3,15.34）→（1.3,21.273）→（2.54,22.22
5）→（2.54,22.86） (20) （1.95,15.34）→（1.95,20.956）→（3.81,22.2
25）→（3.81,23.496）→（5.08,24.766）→（5.08,25.
4） (21) （2.6,15.34）→（2.6,20.638）→（5.08,22.22
5）→（5.08,22.86） (22) （3.25,15.34）→（3.25,20.321）→（6.35,22.2
25）→（6.35,23.496）→（7.62,24.766）→（7.62,25.
4） (23) （3.9,15.34）→（3.9,20.003）→（7.62,22.22
5）→（7.62,22.86） (24) （4.55,15.34）→（4.55,19.686）→（8.89,22.2
25）→（8.89,23.496）→（10.16,24.766）→（10.16,2
5.4） (25) （5.2,15.34）→（5.2,19.368）→（10.16,22.22
5）→（10.16,22.86） (26) （5.85,15.34）→（5.85,19.051）→（11.43,22.
225）→（11.43,23.496）→（12.7,24.766）→（12.7,2
5.4） (27) （6.5,15.34）→（6.5,18.733）→（12.7,22.22
5）→（12.7,22.86） (28) （7.15,15.34）→（7.15,18.416）→’13.97,22.
225）→（13.97,23.496）→（15.24,24.766）→（15.2
4,25.4） (29) （7.8,15.34）→（7.8,18.098）→（15.24,22.22
5）→（15.24,22.86） (30) （8.45,15.34）→（8.45,17.781）→（16.51,22.
225）→（16.51,23.496）→（17.78,24.766）→（17.7
8,25.4） (31) （9.1,15.34）→（9.1,17.463）→（17.78,22.22
5）→（17.78,22.86） (32) （9.75,15.34）→（9.75,17.146）→（19.05,22.
225）→（19.05,23.496）→（20.32,24.766）→（20.3
2,25.4） (33) （10.4,15.34）→（10.4,16.828）→（20.32,22.
225）→（20.32,22.86） 以上は、回路パターン２の１／４の座標値を示してい
る。残りの座標値は、記述した座標値を基準点４を中心
として９０度，１８０度，２７０度それぞれ回転するこ
とによって得ることができる。(1) (-10.4,15.34) → (-10.4,16.828) → (-20.32,2)
2.225) → (-20.32,2.86) (2) (-9.75,15.34) → (-9.75,17.146) → (-19.05,2)
2.225) → (-19.05,23.495) → (-17.78,24.766) → (-
17.78,25.4) (3) (-9.1,15.34) → (-9.1,17.463) → (-17.78,22.
225) → (-17.78,22.86) (4) (-8.45,15.34) → (-8.45,17.781) → (-16.51,2)
2.225) → (-16.51,23.495) → (-15.24,24.766) → (-
15.24,25.4) (5) (-7.8,15.34) → (-7.8,18.098) → (-15.24,22.
225) → (-15.24,22.86) (6) (-7.15,15.34) → (-7.15,18.416) → (-13.97,2)
2.225) → (-13.97,23.495) → (-12.7,24.766) → (-1
2.7,25.4) (7) (-6.5,15.34) → (-6.5,18.733) → (-12.7,22.2)
25) → (-12.7,22.86) (8) (-5.85,15.34) → (-5.85,19.051) → (-11.43,2)
2.225) → (-11.43,23.495) → (-10.16,24.766) → (-
10.16,25.4) (9) (-5.2,15.34) → (-5.2,19.368) → (-10.16,22.
225) → (-10.16,22.86) (10) (-4.55,15.34) → (-4.55,19.686) → (-8.89,2)
2.225) → (-8.89,23.495) → (-7.62,24.766) → (-7.
62,25.4) (11) (-3.9,15.34) → (-3.9,20.003) → (-7.62,22.
225) → (-7.62,22.86) (12) (-3.25,15.34) → (-3.25,20.321) → (-6.35,2)
2.225) → (-6.35,23.496) → (-5.08,24.766) → (-5.
08,25.4) (13) (-2.6,15.34) → (-2.6,20.638) → (-5.08,22.
225) → (-5.08,22.86) (14) (-1.95,15.34) → (-1.95,20.956) → (-3.81,2
2.225) → (3.81,23.496) → (-2.54,24.766) → (-2.5
4,25.4) (15) (-1.3,15.34) → (-1.3,21.273) → (-2.54,22.
225) → (-2.54,22.86) (16) (-0.65,15.34) → (-0.65,21.591) → (-1.27,2)
2.225) → (-1.27,23.496) → (0.0,24.766) → (0.0,2
5.4) (17) (0.0,15.34) → (0.0,22.86) (18) (0.65,15.34) → (0.65,21.591) → (1.27,22.2
25) → (1.27,23.496) → (2.54,24.766) → (2.54,25.
4) (19) (1.3,15.34) → (1.3,21.273) → (2.54,22.22)
5) → (2.54,22.86) (20) (1.95,15.34) → (1.95,20.956) → (3.81,22.2)
25) → (3.81,23.496) → (5.08,24.766) → (5.08,25.
4) (21) (2.6,15.34) → (2.6,20.638) → (5.08,22.22)
5) → (5.08,22.86) (22) (3.25,15.34) → (3.25,20.321) → (6.35,22.2)
25) → (6.35,23.496) → (7.62,24.766) → (7.62,25.
4) (23) (3.9,15.34) → (3.9,20.003) → (7.62,22.22
5) → (7.62,22.86) (24) (4.55,15.34) → (4.55,19.686) → (8.89,22.2)
25) → (8.89,23.496) → (10.16,24.766) → (10.16,2
5.4) (25) (5.2,15.34) → (5.2,19.368) → (10.16,22.22)
5) → (10.16,22.86) (26) (5.85,15.34) → (5.85,19.051) → (11.43,22.
225) → (11.43,23.496) → (12.7,24.766) → (12.7,2
5.4) (27) (6.5,15.34) → (6.5,18.733) → (12.7,22.22
5) → (12.7,22.86) (28) (7.15,15.34) → (7.15,18.416) → '13 .97,22.
225) → (13.97,23.496) → (15.24,24.766) → (15.2
4,25.4) (29) (7.8,15.34) → (7.8,18.098) → (15.24,22.22
5) → (15.24,22.86) (30) (8.45,15.34) → (8.45,17.781) → (16.51,22.
225) → (16.51,23.496) → (17.78,24.766) → (17.7
8,25.4) (31) (9.1,15.34) → (9.1,17.463) → (17.78,22.22)
5) → (17.78,22.86) (32) (9.75,15.34) → (9.75,17.146) → (19.05,22.
225) → (19.05,23.496) → (20.32,24.766) → (20.3
2,25.4) (33) (10.4,15.34) → (10.4,16.828) → (20.32,22.
225) → (20.32, 22.86) The above shows the coordinate values of ¼ of the circuit pattern 2. The remaining coordinate values can be obtained by rotating the described coordinate values about the reference point 4 by 90 degrees, 180 degrees, and 270 degrees, respectively.
以下、本考案により得られる効果を列挙すればつぎの通
りである。The effects obtained by the present invention are listed below.
(i) １３２ピンの表面実装型集積回路を搭載する印刷
配線板上において、表面実装型集積回路の占有する面積
（検査用ランドを含む）が２５．８１cm2以下となるた
め実装密度が上がる。(i) On a printed wiring board on which a 132-pin surface-mount integrated circuit is mounted, the area (including the inspection land) occupied by the surface-mount integrated circuit is 25.81 cm 2 or less, which increases the mounting density.
(ii) 検査用ランドが２．５４格子上にのっているの
で、汎用布線検査機が使用できる。(ii) Since the inspection land is on the 2.54 grid, a general-purpose wiring inspection machine can be used.
(iii) 集積回路接続用パッドと検査用ランドを結ぶ回
路パターン幅を、インチ間２本で使用する回路パターン
幅よりも太い０．２５mmとし、回路間隙をインチ間２本
で保たれる間隙よりも広い０．３３５mmとしてあるため
信頼性があり、オープン・ショート等のトラブルがない
のでこの間の布線検査を行う必要がない。(iii) The width of the circuit pattern connecting the integrated circuit connection pad and the inspection land is 0.25 mm, which is thicker than the circuit pattern width used for two inches, and the circuit gap is larger than the gap maintained by two inches. Since the width is 0.335 mm, it is reliable, and there is no trouble such as open and short, so there is no need to perform wiring inspection during this period.
第１図は、本考案の一実施例を示す印刷配線板上の集積
回路接続用パッドと検査用ランドを接続する回路パター
ン図、第２図は従来印刷配線板上の集積回路接続用パッ
ドと検査用ランドとを接続する回路パターン図である。 １……集積回路接続用パッド、２……回路パターン、３
……検査用ランド、４……基準点、５……絶縁層、６…
…自動実装用位置合わせマーク、７……仮想外周線。FIG. 1 is a circuit pattern diagram for connecting an integrated circuit connection pad on a printed wiring board and an inspection land according to an embodiment of the present invention, and FIG. 2 is an integrated circuit connection pad on a conventional printed wiring board. It is a circuit pattern diagram which connects with the inspection land. 1 ... Pad for connecting integrated circuit, 2 ... Circuit pattern, 3
...... Inspection land, 4 ... Reference point, 5 ... Insulation layer, 6 ...
… Alignment mark for automatic mounting, 7… Virtual peripheral line.
Claims (1)
ッチ０．６５mm）を搭載する印刷配線板において、集積
回路の各ピンの近くに基準点よりＸ，Ｙ方向ともに２．
５４mm間隔で整数倍した位置に配置した検査用ランドを
有し、この検査用ランドと集積回路接続用パッドを結ぶ
回路パターンの幅が最大０．２５mmで、回路最小間隙が
０．３３５mmであり、前記集積回路接続用パッドより外
側へ引き出された前記回路パターンに接続した前記検査
用ランドの前記基準点より遠方の前記検査用ランドのみ
を結んだ仮想外周線の内側の面積が２５．８１cm2以下
のパターンを有することを特徴とする印刷配線板。1. A printed wiring board on which a 132-pin surface mount integrated circuit (terminal pitch: 0.65 mm) is mounted is located near each pin of the integrated circuit in both X and Y directions from a reference point.
It has inspection lands arranged at integer multiples at 54 mm intervals, the maximum width of the circuit pattern connecting the inspection lands and integrated circuit connection pads is 0.25 mm, and the minimum circuit gap is 0.335 mm. The area inside the virtual outer peripheral line that connects only the inspection land far from the reference point of the inspection land connected to the circuit pattern drawn to the outside from the integrated circuit connection pad is 25.81 cm 2 or less. A printed wiring board having the following pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8767587U JPH0631733Y2 (en) | 1987-06-05 | 1987-06-05 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8767587U JPH0631733Y2 (en) | 1987-06-05 | 1987-06-05 | Printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63200173U JPS63200173U (en) | 1988-12-23 |
| JPH0631733Y2 true JPH0631733Y2 (en) | 1994-08-22 |
Family
ID=30945101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8767587U Expired - Lifetime JPH0631733Y2 (en) | 1987-06-05 | 1987-06-05 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0631733Y2 (en) |
-
1987
- 1987-06-05 JP JP8767587U patent/JPH0631733Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63200173U (en) | 1988-12-23 |
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