JPH06313874A - Drive method for liquid crystal display element - Google Patents

Abstract

PURPOSE:To enable optimum display quality to be maintained by providing a pulse count control circuit at the pre-stage of a liquid crystal alternated signal generation circuit, counting the pulses of an inputted synchronous signal, and eliminating an unnecessary portion of the pulses for output. CONSTITUTION:A synchronous signal LP for one time of scanning and a synchronous signal FRM for one screen, or the signal LP and a liquid crystal alternated signal M respectively received from a liquid crystal display controller circuit, are inputted to a liquid crystal alternated signal generation circuit 7. A liquid crystal alternated signal M' different from the signal M is thereby generated and used for driving a liquid crystal display element. In this case, a pulse count control circuit 6 sets the count value of a subtraction counter on the basis of a timing signal introduced from a drive duty setting circuit 5. Also, the pulse count of the signal LP contained in one cycle of the signal FRM is modulated to the count value of the subtraction counter for generating a synchronous signal LP'. Furthermore, the signal LP' is as well introduced to the liquid crystal alternated signal generation circuit 7 for outputting the different liquid crystal alternated signal M'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a liquid crystal alternating signal generating circuit built-in or externally attached.

[0002]

2. Description of the Related Art In a large-capacity liquid crystal display device, in order to improve display quality such as crosstalk, horizontal stripes, and screen flickering, an appropriate liquid crystal alternating current is selected according to the characteristics of the liquid crystal material of the liquid crystal display element and the driving duty. In many cases, a liquid crystal alternating signal generating circuit that generates a signal (M ') is used.

In the prior art, a synchronizing signal (LP) from a liquid crystal display controller circuit is directly input to the liquid crystal alternating signal generating circuit to generate the liquid crystal alternating signal (M ') suitable for a liquid crystal display device. It was

[0004]

When the synchronizing signal (LP) is directly input to the liquid crystal alternating current signal generating circuit as described above, an appropriate liquid crystal alternating current signal (M ') for a certain drive duty is obtained. When a liquid crystal display device using the liquid crystal alternating signal generation circuit set to be output is driven with different drive duty, it is said that display quality is deteriorated, such as an increase in crosstalk, flicker on the screen, and horizontal stripes. It had drawbacks.

[0005]

In order to solve the above problems, according to the present invention, a sync signal (L) for one scan included in one cycle of a sync signal (FRM) for one screen input.
A pulse number control circuit which counts the number of pulses in P) and, when a required number of pulses or more is input, deletes the unnecessary portion and outputs it is added to the preceding stage of the liquid crystal alternating signal generation circuit.

[0006]

With the circuit configuration as described above, the number of pulses of the synchronizing signal (LP) input to the liquid crystal alternating signal generation circuit is always kept constant even when the drive duty of the liquid crystal display controller circuit changes. Accordingly, the liquid crystal display element is always driven at the drive duty set by the pulse number control circuit, and if the liquid crystal alternating signal generation circuit is set in advance for the drive duty, an appropriate liquid crystal alternating signal ( Since it is driven by M '), the display quality does not change.

[0007]

EXAMPLES The present invention will be described below with reference to examples. FIG. 1 is a circuit diagram of a pulse number control circuit according to the present invention. In FIG. 1, 1 input from the liquid crystal display controller circuit
Sync signal for scanning (LP) and sync signal for one screen (FR
M) is introduced into the subtraction counter 1 through the NOT circuit 3,
1 to 1 depending on the synchronization signal (FRM) and the synchronization signal (LP)
The number of pulses of the synchronization signal (LP) is arbitrarily set within the range of n (n ≦ 256). Then, the synchronizing signal (L) modulated through the JK flip-flop 2 and the AND circuit 4
P ') is output to the liquid crystal alternating signal generation circuit. The number of pulses of the subtraction counter 1 is set by the subtraction counter 1
Is determined by the combination of jumpers J1 to J8 connected to the terminals J0 to J7 of
A modulated sync signal (L) including (m + 1) pulses
P ') is output to the liquid crystal alternating signal generation circuit.

The operation of FIG. 1 will be described below with reference to the time chart of FIG. In FIG. 2, FRM is a sync signal for one screen, LP is a sync signal for one scan, CLOCK is a clock signal of the subtraction counter 1, inversion (CO / ZO) is an output signal of the subtraction counter 1, and inversion (Q) is J. -The output signal of the K flip-flop 2 and LP 'respectively represent the modulated synchronizing signal output from the pulse number control circuit.

The subtraction counter 1 has a count value set to m (arbitrary) in advance by a combination of J1 to J8. The synchronization signal (LP) inverted by the NOT circuit 3 is input as the clock signal (CLOCK) of the subtraction counter 1. The subtraction counter 1 performs subtraction at the rising edge of the pulse of the clock signal, and when the count value becomes 0, the "L" level is output for one cycle until the next pulse is input. (Refer to the inverted (CO / ZO) waveform in FIG. 2) This pulse signal (inverted (CO / ZO)) is the JK flip
It is input to the flop 2, and the inversion (Q) of the output changes from "H" level to "L" level at the rising edge of the pulse, and maintains "L" level until it is reset by the synchronization signal (FRM) (Fig. 2 inversion (Q) waveform).

This output and the synchronizing signal (LP) are introduced into the AND circuit 4, so that unnecessary (n- (m +) is obtained from the synchronizing signal (LP) inputted from the liquid crystal controller circuit.
1)) The waveform becomes a waveform with the number of pulses removed (L in FIG. 2).
(See P waveform). Further, the synchronization signal (FRM) functions as a reset signal for the subtraction counter 1 and the JK flip-flop 2 and repeats the above operation in a cycle of one screen.

FIG. 3 is a circuit block diagram of an IC in which the pulse number control circuit and the liquid crystal AC signal generation circuit according to the present invention are integrated on one chip. In FIG. 3, in the pulse number control circuit 6, the count value of the internal subtraction counter is set by the timing signal introduced from the drive duty setting circuit 5, and one scan included in one cycle of the synchronization signal (FRM) for one screen. A synchronizing signal (LP ') obtained by modulating the number of pulses of the minute synchronizing signal (LP) according to the count value is introduced into the liquid crystal alternating signal generating circuit 7. Then, in the liquid crystal alternating signal generating circuit 7, the synchronizing signal (LP '), the synchronizing signal for one screen (FRM) or the liquid crystal alternating signal (M) output from the liquid crystal display controller circuit and a combination of the external terminals are used for the liquid crystal. The liquid crystal alternating signal (M ') different from the alternating signal (M) is output. The count value of the subtraction counter is set in eight ways by combining the external terminals A to C.

[0012]

As described above, according to the present invention, the driving duty of the liquid crystal display controller circuit, that is, the number of pulses of the synchronizing signal (LP) for one scanning included in one cycle of the synchronizing signal (FRM) for one screen. Even if changes, the number of pulses input to the liquid crystal alternating signal generation circuit is always constant,
A liquid crystal display controller circuit having a drive duty different from that of the liquid crystal display controller circuit is set in advance by setting the liquid crystal alternating signal generation circuit so that an appropriate liquid crystal alternating signal (M ′) is generated for the drive duty. Even when it is driven by, it is possible to always maintain the optimum display quality without requiring adjustment of the liquid crystal alternating signal generation circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart diagram of FIG.

FIG. 3 is a circuit block diagram of an IC incorporating the present invention in an embodiment of the present invention.

FIG. 4 is a circuit block diagram of a conventional drive circuit for a liquid crystal display element.

[Explanation of symbols]

 1 Subtraction counter 2 JK flip-flop 3 NOT circuit 4 AND circuit 5 Liquid crystal duty setting circuit 6 Pulse number control circuit 7 Liquid crystal alternating signal generation circuit

Claims (1)

[Claims] 1. A periodic signal (LP) for one scan and a periodic signal (FRM) for one screen output from a liquid crystal display controller circuit, or a synchronization signal (LP) for one scan.
And a liquid crystal alternating signal (M) are input to a liquid crystal alternating signal generating circuit to generate a liquid crystal alternating signal (M ′) different from the liquid crystal alternating signal (M) and used to drive a liquid crystal display element. In a method of driving a liquid crystal display device, a sync signal (LP) for one scan and a sync signal (FRM) for one screen are input, and a sync signal (L) different from the periodic signal for one scan is input.
P ') is provided to the liquid crystal alternating signal generation circuit to provide a pulse number control circuit to determine the drive duty of the liquid crystal display element for the synchronization signal (FR) for one screen.
The sync signal (L) for one scan included in one cycle of M)
A method of driving a liquid crystal display element, wherein the number of pulses of P) can be set arbitrarily regardless of the connected liquid crystal display controller.