JPH03186890A - System and circuit for display driving - Google Patents

Abstract

PURPOSE:To set up display contrast by simple constitution without increasing the number of external terminals by inputting information for specifying pulse width time-dividedly with display data through a display data terminal. CONSTITUTION:In the high level period of a terminal, the inverse of IE, picture element data DATA are inputted to any one of signal line driving circuits DDV1 to DDV3. When the final data out of the picture element data DATA are inputted, a carry signal, the inverse of CAR, from the signal line driving circuit DDV3 is changed from the high level to the low level. Thereby, data inputted synchronously with a clock pulse CL2 at the succeeding timing are not picture element data but is time-sequentially inputted pulse width information for specifying gradation display. Thus, the pulse width can be optionally set up without increasing the number of external terminals.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a display driving method and its display driving circuit,
For example, the present invention relates to a technique that is effective for use in a signal line drive circuit for a liquid crystal display device with a simple matrix configuration that performs gradation display.

[Conventional technology]

Gradation display of liquid crystal display devices is attracting attention.

As one of the gradation display methods of such a liquid crystal display device,
Some devices set pulse width information corresponding to display data from an external terminal. An example of such a gradation display method is the ``gradation driver LSI T9'' sold by Toshiba.
There is 831J.

[Problem to be solved by the invention]

In the above method, a preset table of gradation data and pulse width is set and selected using an external terminal. Therefore, there is a problem in that settings are limited depending on the number of terminals. Furthermore, in an LSI for driving a liquid crystal, most of the external terminals are used for driving the liquid crystal. Therefore, if a control terminal is used for gradation display as described above, the number of terminals for driving the liquid crystal decreases accordingly. That is, in order to achieve high image quality in liquid crystal display panels, the number of pixels is increasing in density and increasing in number. However, when increasing the number of pixels like this,
Correspondingly, there is a problem in that the number of driving LSIs increases. Therefore, an important issue for driving LSIs is how many driving signals can be output.

The purpose of this invention is to
It is an object of the present invention to provide a display driving method and its display driving circuit that enable setting of display contrast with a simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, information specifying the pulse width is input in a time-sharing manner with the display data using a display data terminal to a display device whose contrast is changed according to the pulse width.

[For production]

According to the above-described means, the pulse width can be arbitrarily set without increasing the number of external terminals.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a liquid crystal display device to which the present invention is applied.

In a liquid crystal display panel LCD, scanning line electrodes (common electrodes) are arranged to extend horizontally, and signal line electrodes (pixel electrodes)
It has a simple matrix configuration in which the elements are arranged so as to extend in the vertical direction.

The liquid crystal display panel LCD includes M scanning line electrodes, and a scanning line drive circuit LDV is provided corresponding to the M scanning line electrodes. The scanning line drive circuit LDV drives M scanning line electrodes into one
The selection is made sequentially and alternatively during the frame.

In the liquid crystal display panel LCD, the signal line electrode is NX3.
The signal line drive circuits DDV1 to DDV3 are provided correspondingly. One signal line drive circuit DD
V1 receives pixel data and forms N signal line drive signals. Other signal line drive circuit DDV2. In DDV3 as well, N signal drive signals are formed in the same manner as described above. In this way, three signal line drive circuits DDV1 to D
By arranging the DV3 in parallel, it is possible to drive the liquid crystal display panel LCD having the signal line electrodes consisting of the NX three lines.

In this embodiment, each pixel is bright/
Instead of a binary display of dark, it has a gradation display function consisting of four values including bright/dark. Of the four-value gradation display, two values, bright and dark, are fixed, and the contrast (brightness) of the remaining two gradation displays can be adjusted from the outside.

In this embodiment, unlike the prior art, a special external terminal is not provided for setting the contrast in such gradation display, but an external terminal for inputting pixel data DATA is used. That is, the pixel data DATA is sent to each signal line drive circuit DDV in synchronization with the clock pulse CL2.
1 to DDV3, and then output in synchronization with the clock pulse CLI. Although not particularly limited,
The pixel data DATA consists of 8 bits, and 2 bits of pixel data are allocated to each pixel for the above-mentioned four-value gradation display. Therefore, by taking in pixel data DATA for one clock cycle, pixel data for four pixels is input. In this case, as described above, a signal line drive circuit consisting of three pieces is used, and the pixel data D
The signal line to which ATA is supplied is connected in parallel to the data terminals of the three signal line drive circuits DDV1 to DDV3. Therefore, in order to sequentially take in the pixel data DAT8 in each signal line drive circuit DDV~DDV3, the chip enable signal E is received and passed. In other words, the leftmost signal line drive circuit DDV
The chip enable terminal E of No. 1 is always kept in a selected state by being constantly supplied with the ground potential of the circuit. When the signal line drive circuit DDV 1 finishes capturing pixel data assigned to itself, it outputs a carry signal CA.
Output R. This signal CAR is input to the chip enable terminal E of the next signal line drive circuit DDV2. As a result, at the next timing, the pixel data DATA is captured in the signal line drive circuit DDV2. Similarly to the above, when the signal line drive circuit DDV2 finishes taking in the pixel data assigned to itself, it outputs a carry signal C.
Output AR. This signal CAR is input to the chip enable terminal E of the next signal line drive circuit DDV3.

As a result, at the next timing, the signal line drive circuit DDV
3, pixel data DATA is taken in.

Then, similarly to the above, the signal line drive circuit DDV3 outputs the carry signal CAR when the capture of the pixel data assigned to itself is completed, similarly to the above. In this embodiment, the carry signal CAR in the signal line drive circuit that takes in pixel data last as described above is used as a timing signal for distinguishing contrast setting signals of display data. That is, this signal CAR is applied to the terminal I provided in all the signal line drive circuits DDV1 to DDV3.
It is input to E. When this terminal IE is set to a low level, the data terminal to which pixel data DATA is input is used to input pulse width setting information for gradation display.

FIG. 2 is a timing diagram showing an example of the operation of inputting the pulse width setting information.

That is, the period in which the terminal IE is at high level as described above is a period in which the pixel data DATA is input to any one of the signal line drive circuits DDV1 to DDV3. When the final data of the pixel data DATA is input,
Accordingly, the carry signal C of the signal line drive circuit DDV3
AR changes from high level to low level. Therefore,
At the next timing, the data input in synchronization with clock pulse CL2 is not pixel data, but gradation display "
Pulse width information specifying gradation level "1" and gradation level "2" indicating intermediate brightness from gradation level "0" (dark) to gradation level "3" (bright) is inputted in time series.

Here, although not particularly limited, gradation "1" and gradation "2"
Pulse width information A and B provided for each signal line indicate the start point and end point of the pulse width corresponding to the signal line assigned an odd number, and pulse width information C and D are provided for the signal line assigned an even number. It shows the start point and end point of the pulse width corresponding to the signal line.

In this way, an arbitrary pulse width can be set by combining the start point (rising) and end point (falling).

These pulse setting information are taken into the register.

In this embodiment, the signal lines are divided into odd numbers and even numbers, and the brightness can be independently set for each of the same gradations of "1" or "2". This is to correct the pattern dependence of the effective voltage on the signal line electrodes in the liquid crystal display panel LCD. If there is no problem with the pattern dependence of the effective voltage on the signal line electrode as described above, the above pulse width setting information should be such that the same gradation "1" or "2" is the same pulse width for that line. It may be something.

By adopting the configuration in which the pulse width setting information is input from the data terminal to which the pixel data DATA is input in this way, the contrast of the intermediate gradation can be set without increasing the number of terminals.

FIG. 3 shows a block diagram of one embodiment of the signal line driving circuit.

Pulse width setting information A (C) input from the data terminal to which the above pixel data DATA is input is taken into the start point resistor SPR, and pulse width setting information IB (D) is input to the end point resistor PR. be taken in.

0 counter circuit C0UNT outputs pulse width information whose unit pulse width is one cycle of clock pulse CL2 by controlling the counting operation of clock pulse CL2 by these information I[IA and B. The pulse generation circuit PG generates a fixed pulse width corresponding to the gradation "technical" and gradation "2" and a fixed pulse width corresponding to the gradation "3" from the counting output of the counter circuit and the pulse width setting information A and B, respectively. generates a pulse signal with a pulse width set according to

Pixel data of the next scan line to be displayed during the display period is serially input to the line memory LM, and is output in parallel as pixel data corresponding to each signal line. Note that when the pixel data consists of 8 bits as described above and four-level gradation display is performed, each pixel has 2 bits of data, so the data for 4 pixels is serialized.

Based on the pixel data corresponding to each of the signal line electrodes, a pulse width selection circuit SEL consisting of a multiplexer or the like is switch-controlled, and a pulse signal having a pulse width of 1 or more corresponding to the pixel data is selected, and the drive circuit DR
This will be communicated to V. The drive circuit DRV amplifies the signal and outputs it in parallel to the signal line electrodes of each liquid crystal display device.

FIG. 5 shows a multi-value (
A waveform diagram showing an example of a drive signal (115 bias) is shown.

In the same figure, a drive signal COM for one scanning line electrode and a drive signal 5EGI for a non-selected (dark) signal line electrode with gradation "0" are shown.
An example of the drive signal 5EG2 for the selected (bright) signal line electrode is shown. In this case, the drive signal 5EG2 of the selected (bright) signal line electrode has two halftones as shown by the dotted line in the figure, in addition to the bright (gradation "3") shown by the solid line, in other words, Examples of signals of gradation "1" and gradation "2" are depicted. These gradation "1", gradation "2" and gradation "
3", a pulse with a pulse width of Wl to W3 is formed. Therefore, among the voltages (AC voltage) applied between the scanning line electrode COM and the signal line electrode 5EG2,
In the case of halftone display, the pulse widths W1 and W in the drive signal 5EG2 are
As shown in Figure 2, the waveform is such that the pulse backing is missing by 2V15. As a result, the effective driving voltage is reduced, so that halftone display corresponding to gradation "1" or "2" can be performed. At this time, since the pulse widths W1 and W2 can be adjusted as described above for each scanning line electrode, it is possible to display a halftone with a corresponding contrast.

Note that, although not particularly limited, the counter circuit C0 in FIG.
UNT is the selected level V1 or V2 in the scan line electrode.
The counting operation of the clock pulse CK2 is performed within the period. Therefore, when the next scanning line electrode is set to the selected level, the same counting operation as described above is performed again accordingly. As a result, pulse signals having pulse widths W1 and W2 as described above are formed corresponding to each scanning electrode.

As in this embodiment, there is a one-to-one correspondence between the pixel data string and the contrast of the halftone, so the halftone can be finely adjusted using software 3 to make the figure stand out according to the characteristics of the figure to be displayed. It becomes possible to display various gradations. Further, while looking at the display screen, it is possible to switch to a more easily viewable gradation display by inputting a key operation or the like.

FIG. 4 shows a block diagram of another embodiment of the signal line driving circuit according to the present invention.

In this embodiment, the signal line drive circuits DDV1 to DDV
3 is distinguished by the pixel data and pulse width setting information supplied from the data terminal, and the identification signal DT/PS. For example, if the identification signal DT/PS is high level, the data D
The ATA is pixel data, which is input in synchronization with the clock pulse CL2, and taken into the line memory LM as described above. When the identification signal DT/PS is at a low level, the data DATA is treated as pulse width setting information, is input in synchronization with the clock pulse CL2, and is input to the register SP as described above.
R, EPR, etc. The signal CL1 is a horizontal synchronizing signal, and is used, for example, to clear the register 4, etc., if pulse width information is set for each line.

In this configuration, pixel data from a frame memory or the like that stores pixel blocks for at least one screen is supplied together with the identification signal DT/PS generated by the display controller. This identification signal is monitored by a microprocessor or the like, and when the pulse width setting period in which the signal DT/PS is set to low level is reached, the pulse width information is inputted from the microprocessor or the like. Alternatively, pulse width setting information is stored for each line along with pixel data in the frame memory, and the pixel data and pulse width setting information are read out by the display control device in synchronization with display timing of the display device. The signal line driving circuit DDV may be configured to take in the line memory LM, start point register SPR, and end point register EPR, respectively.

In the configuration shown in FIG. 1, the low level of the terminal IB is monitored by the microphone processor and the display controller, and in synchronization with the low level, the pulse width setting information A to D is output as shown in the waveform diagram of FIG. 2. It is only necessary to cause the events to occur in chronological order.

The effects obtained from the above examples are as follows. That is, (1) information specifying the pulse width is input in a time-sharing manner with the display data using a display data terminal to a display device whose contrast is changed according to the pulse width. This configuration has the effect that the pulse width for gradation display can be arbitrarily set without increasing the number of external terminals.

(2) By adopting a configuration in which the information specifying the pulse width is input using the blanking period of the display device, the time-sharing pulse width can be inputted without forming a special timing signal. This has the effect of making it possible to input setting information.

(3) According to (11) above, most of the external terminals can be used for driving signal lines.This allows a single display semiconductor integrated circuit device to drive a larger number of signal lines. Therefore, it is possible to reduce the number of semiconductor integrated circuit devices required to drive a display panel with high density and high density elements.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in addition to the four levels of gradation described above, liquid crystal displays can display more gradations, such as 8 gradations using 3-bit pixel data and 166 gradations using 4-bit pixel data. It's fine. On the contrary, the liquid crystal display may perform binary display without performing gradation display. In this case, the contrast can be changed by changing the pulse width for displaying brightness of brightness/darkness. In this embodiment, since the brightness of each line can be arbitrarily set by software, this may be used to display the cursor.

The number of signal line driving LSIs used to configure a liquid crystal display device is set from the number of signal lines of the liquid crystal display panel and the number of output terminals of the signal line driving LSI that drives them. Depending on the liquid crystal display panel, it may be configured with only one signal line driving L31.

The pulse width setting information may be inputted together with pixel data during the display period instead of using the horizontal blanking period or the vertical blanking period as in the above embodiment. That is, pulse width setting information is inserted next to pixel data of a specific plurality of bits. With this configuration, during a serial/parallel conversion operation in which serially input pixel data is taken into a line memory or the like, pulse width setting information can be distinguished from the number of bits and input to a register or the like. In this configuration, when a plurality of signal line drive circuits are provided as in the embodiment described above, pulse width setting information as described above is input every time pixel data is input to each signal line drive circuit.

Further, the pulse width setting information may be inputted with information indicating on-the-spot decrement with respect to the reference pulse width. In this configuration, when no data is input to the pulse width setting register, halftone display, etc. is performed according to the reference pulse width, and the minute pulse width ΔW set by the pulse width setting information is used as the reference. It is added to and subtracted from the pulse W. The pulse width can be increased or decreased by ±ΔW with respect to the reference pulse W by using, for example, an AND gate circuit or an OR gate circuit as a circuit that increases or decreases the pulse width.

With the configuration in which the pulse width of ΔW is increased or decreased in this way, the number of bits of the pulse width setting information can be reduced.

Circuits that generate pulses with a pulse width according to pulse width setting information include those that generate digitally using registers and counter circuits as described above, as well as lamps that generate using constant current, etc. It is possible to adopt an exclusive embodiment in which the voltage and the pulse width setting voltage are input to the voltage comparator circuit. The pulse width setting voltage may be obtained by converting digitally input pulse width setting information 9 into an analog voltage using a D/A conversion circuit. In this way, a circuit that forms a pulse signal having a pulse width according to pulse width setting information based on digital information can take various embodiments.

In addition to the above-mentioned 115 bias method, the display driving method may be any method as long as the brightness changes according to changes in pulse width.

Further, the display device used in the display drive method and display drive circuit according to the present invention is the liquid crystal display device LC as described above.
In addition to D, a plasma display panel (PDP), electroluminescence (EL), etc. may be used.

The present invention can be widely used as a display driving method and its display driving circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, information specifying the above-mentioned pulse width is input in a time-sharing manner with the display data using a display data terminal to a display device whose contrast is changed according to the pulse width. With this configuration, the pulse width for gradation display can be arbitrarily set without increasing the number of external terminals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device to which the present invention is applied, FIG. 2 is a timing diagram for explaining an example of its operation, and FIG. 3 is a signal diagram according to the present invention. FIG. 4 is a block diagram showing one embodiment of the line driving circuit. FIG. 4 is a block diagram showing another embodiment of the signal line driving circuit according to the present invention. FIG. 5 is a block diagram showing another embodiment of the signal line driving circuit according to the invention. FIG. 3 is a waveform diagram showing an example of a multi-value drive signal that is formed. LCD...Liquid crystal display panel, LDV...Scanning line drive circuit, DDV1~DDV3...Signal line drive circuit, C0UN
T: Counter circuit, SPR: Start point register, EPR: Endpoint register, LM: Line memory, PG: Pulse generation circuit, SEL: Pulse width selection circuit, DRV: Driver (drive circuit)

Claims (1)

[Claims] 1. Information specifying the pulse width can be input to a display device whose contrast changes according to the pulse width in a time-sharing manner with the display data using a display data terminal. Characteristic display drive method. 2. A display driving method characterized in that the information specifying the pulse width is input using a blanking period of the display device. 3. A register that takes in the pulse width setting signal inputted in a time-sharing manner from the display data terminal, a pulse generation circuit that forms a pulse signal with a pulse width according to the setting signal taken into this register, and this pulse generation circuit. 1. A display drive circuit comprising: a drive circuit that forms a display drive signal to be supplied to a display device from a pulse signal formed by the display data and a display data. 4. The pulse signal of the pulse width formed according to the pulse width setting signal specifies an intermediate brightness of a display device that performs gradation display, as set forth in claim 3. display drive circuit.