JPH0630502B2 - Data bus relay device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a relay device for a data transfer bus. More specifically, the upstream side and the downstream side of a bus to be relayed are driven by different power supply devices. The present invention relates to such a data bus relay device.

(Prior Art) FIG. 3 is a configuration block diagram of a data bus relay device in which the upstream side and the downstream side of a bus to be relayed are driven by different power supply devices.

In the figure, BS1 is an upstream bus, to which a computer 1 and an I / O device 2 that manage the entire system are connected.
Reference numeral 3 denotes a first power supply device, which supplies operating power to the computer 1 and the I / O device 2 connected to the upstream bus BS1. BS2 is a downstream bus that has multiple I / O devices 4,
5 and 6 are connected. 7 is installed between the upstream bus BS1 and the downstream bus BS2, and the upstream bus BS1 and the downstream bus
It is a relay device that relays the data bus passing through BS2. A second power supply device 8 supplies operating power to the relay device 7 and the plurality of I / O devices 4, 5 and 6 connected to the downstream bus BS2.

(Problems to be Solved by the Invention) In the system configured as described above, for example, the second
If the power supply 8 of the computer fails and the power is restored in a short time, and the access from the computer 1 to any of the I / O devices fails, the cause is the failure of the I / O device. However, there is a problem in that it is not possible to determine whether the power supply device 8 is due to a power failure and the error processing thereafter is not deterministic.

In addition, the power failure of only the second power supply device, the first power supply device 3
Can be easily generated when the input power supply system is different, or when the loads are different even in the same power supply system.

As one method for solving the above-mentioned problems, a method of coordinating between the first power supply device 3 and the second power supply device 8 can be considered. That is, when the second power supply device 8 detects a power failure and turns off its output, the first power supply device 3
It is also transmitted to the first power supply device, which causes a power failure. Due to the power failure of the first power supply device 3, the computer 1 can recognize the occurrence of the power failure.

However, according to such a method, a direct signal transmitting means between the first power supply device 3 and the second power supply device 8 is required, and each power supply device has to have a special configuration. Moreover, in a system in which a plurality of downstream buses BS2 are connected to the upstream bus BS1 via a plurality of relay devices, the failure of one power supply unit causes the entire system to go down. There is a problem that can not be maintained.

The present invention has been made in view of such problems,
The purpose is that even when the power failure occurs in the second power supply and the access from the computer 1 to the I / O device connected to the downstream bus BS2 fails, the access failure is due to the power failure of the power supply. Therefore, it is intended to realize a data bus relay device which can be recognized as the above and can accurately perform error processing at the time of access failure.

(Means for Solving Problems) According to the present invention for solving the above problems, a computer serving as a master of data transfer, an upstream bus connected to the computer, and a computer connected to the computer and the upstream bus are connected. A first power supply device for supplying electric power to the device, a downstream bus, a relay device installed between the upstream bus and the downstream bus for relaying data between the buses, and the downstream side The relay device includes an I / O device connected to a bus for exchanging data with the computer, and a second power supply device for supplying power to the I / O device and the relay device. , A power failure detecting means for detecting a power failure of the second power supply device, a flip-flop set when the power failure is detected by the power failure detecting means, and a state of the flip-flop via the upstream bus. Can be read With a and is characterized in that a circuit means for resetting the flip-flop via the upstream bus.

(Operation) When a power failure occurs in the power supply device 8 and an accident occurs in which the power supply device 8 is restored again, the state is stored in the flip-flop 75. Therefore, the computer 1 accesses the I / O device and, if it fails, reads the state of the flip-flop to determine whether the access failure is due to the power supply device or due to the I / O device. You can know exactly what it is.

(Example) FIG. 1 is a configuration block diagram showing an example of an apparatus according to the present invention. In the figure, those parts corresponding to those in FIG. 3 are designated by the same reference numerals. A computer 1 is a master of data transfer. Upstream bus connected to this computer
The BS1 and the downstream side bus BS2 are composed of a control signal bus B1 for transferring a control signal and a data bus B2 for transferring an address signal and a data signal. 4, 5 and 6 are I / O devices that are connected to the downstream side bus BS2 and exchange data with the computer 1, and 7 connects the upstream side bus and the downstream side bus to relay data between both buses. The I / O devices 4, 5 and 6 which are relay devices to perform
At the same time, power is supplied from the second power supply device 8 to operate.

In this relay device 7, 71 is a bus relay control unit for inputting a control signal from the computer 1 via a control signal bus B1 to control each part in the relay device and for generating a control signal to a downstream side bus BS2. , 72, 73 are bus buffer units inserted in the data bus B2. 74 is the second power supply device 8
From the power failure of the power supply unit 8 by inputting a power status signal from the power supply apparatus, and detecting the power failure of the power supply and its recovery, 75 receiving the signal from the power failure detection means 74. Is detected, the state of the flip-flop 75 is set so that the computer 1 can read the state of the flip-flop 75 via the upstream bus BS1 and the flip-flop 75 is reset via the upstream bus BS1. Address decoding unit 7 for decoding the address signal in the read reset circuit
7 and a gate 78. Here, the gate 78 is controlled by an enable signal EN which instructs the address decoding unit 77 to read the state of the flip-flop 75.

Next, the operation of the apparatus configured as described above will be described separately for normal operation and power failure.

(During normal operation) In the relay device 7, the bus relay control unit 71 inputs a control signal from the computer 1 via the upstream bus BS1 to control the opening / closing of the bus buffer units 72 and 73, and at the same time to the downstream side. Produces control signal for side bus BS2. The address decoder unit 77 receives an address signal from the computer 1 via the upstream bus BS1 and determines whether to relay the address signal to the downstream bus BS2 or access the flip-flop 75. In addition, the read / write (R
/ W) and the timing signal are given, and the bus relay control unit 7
Bus 1 indicating that the downstream bus BS2 is selected in 1
The access signal is being output.

As a result, in the relay device 7, the computer 1 has the upstream bus BS.
1, acting as a relay device to access I / O devices via the downstream bus BS2, and address signals from the computer 1
It relays the write data signal to the I / O device and the read data signal from the I / O device.

(When a power failure occurs) During normal operation, the second power supply device 8 has a power failure for some reason, and during the power failure, the computer 1 has a downstream bus.
When the I / O device connected to BS2 is accessed and the access fails (no response), the computer 1 makes an access to read the state of the flip-flop 75 in the relay device 7. On the other hand, the power failure detection means 7 in the relay device 7
4 detects a power failure of the second power supply device 8 and sets the flip-flop 75 (state "1") at the time when the power supply is detected to be restored. If the power is not restored even after the power is cut off, the relay device 7 is not supplied with power and cannot operate.

FIG. 2 is a flowchart showing an example of the operation performed by the computer 1.

As a result of reading the state of the flowchart 75, if the computer 1 is not responding (state of “0”), the system including the power supply device 8 and connected to the downstream side bus BS2 (second bus system)
The whole is recognized as fail. If there is any response, it is determined whether the state of the flip-flop 75 is "1" or "0". Here, if it is "1", the second power supply device 8
Recognizes that access has failed due to a power failure, and resets the flip-flop 75. Also,
If it is "0", it is recognized as an access failure due to a failure of the I / O device, and the error processing of the I / O device defined by the prediction system is executed.

As described above, according to the device of the present invention, the computer 1
Can access the I / O device, and if that access fails, it can be accurately determined whether the cause is the I / O device itself, a power outage, or a relay device failure. Error handling and maintenance work can be performed easily. Further, in order to realize such an effect, a special configuration is not required for the power supply device, so that an inexpensive and versatile power supply device can be used.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an example of a device according to the present invention, FIG. 2 is a flowchart showing its operation, and FIG. 3 is a configuration block diagram of a data bus relay device. 1 ... Computer, BS1 ... Upstream bus, BS2 ... Downstream bus, 3,8 ... Power supply device, 2,4,5,6 ... I / O device, 7 ... Relay device, 74 ... Blackout detection means, 75 ...
Flip-flop, 76 ... Readout reset circuit

Claims (1)

[Claims] 1. A computer that is a master for data transfer, an upstream bus connected to this computer, and a first power supply device that supplies power to devices connected to the computer and the upstream bus. Data is exchanged between a downstream bus, a relay device installed between the upstream bus and the downstream bus for relaying data between the buses, and connected to the downstream bus to exchange data with the computer I And an I / O device and a second power supply device that supplies power to the I / O device and the relay device, and a power failure detection unit that detects a power failure of the second power supply device in the relay device. A flip-flop which is set when the power failure is detected by the power failure detection means, and a state of the flip-flop can be read out via the upstream bus and a flip-flop via the upstream bus. And a circuit unit for resetting the data bus.