JPH06302954A - Manufacture of circuit board - Google Patents

Manufacture of circuit board

Info

Publication number
JPH06302954A
JPH06302954A JP8436193A JP8436193A JPH06302954A JP H06302954 A JPH06302954 A JP H06302954A JP 8436193 A JP8436193 A JP 8436193A JP 8436193 A JP8436193 A JP 8436193A JP H06302954 A JPH06302954 A JP H06302954A
Authority
JP
Japan
Prior art keywords
substrate
hole
holes
polishing
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8436193A
Other languages
Japanese (ja)
Inventor
Tomoki Okamoto
朋己 岡本
Toshiji Shimamoto
敏次 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokuyama Corp
Original Assignee
Tokuyama Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokuyama Corp filed Critical Tokuyama Corp
Priority to JP8436193A priority Critical patent/JPH06302954A/en
Publication of JPH06302954A publication Critical patent/JPH06302954A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide highly reliable conducting through holes by fixing a substrate to a supporting base having such recessed sections that can cover projecting sections at the locations corresponding to the through holes and polishing away the projecting sections. CONSTITUTION:After forming 1,150 through holes 2 through a substrate 1 made of a copper-clad epoxy laminated board whose base material is glass and filling the holes 2 with copper paste by a screen printing method as a curable conductive material 3, and then, solidifying the paste, the substrate 1 is fixed on a supporting base 4 composed of a copper-clad epoxy laminated board whose base material is glass. Then a positive etching pattern is formed by polishing the projecting parts of the solidified copper paste bodies from the nonsupported surface of the substrate 1 and plating electrolytic copper 5 to the smoothed surface of the substrate 1, and then, laminating a dry film as an etching resist 6 and performing exposure and development. Therefore, highly reliable conducting through holes can be obtained, because uniform and smooth polishing can be performed when the etching resist 6 is removed after etching.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、回路基板の新規な製造
方法に関する。詳しくは、スルーホール内部へのメッキ
を行うこと無く、周囲の配線パターンと該スルーホール
との接続を確実に行うことが可能な回路基板の製造方法
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel method for manufacturing a circuit board. More specifically, it is a method of manufacturing a circuit board that can reliably connect the surrounding wiring pattern to the through hole without plating the inside of the through hole.

【0002】[0002]

【従来の技術】従来、回路基板の導通スルーホールの形
成は、種々の方法が知られている。例えば、両面に導電
層を有する絶縁基板(以下、単に『基板』という。)に
貫通孔を形成し、該貫通孔に銅ペースト・銀ペーストに
代表される硬化性導電物質を基板表面より突出する状態
で充填、硬化した後、該突出部を研磨除去して導通スル
ーホールを形成する方法が知られている。
2. Description of the Related Art Conventionally, various methods are known for forming conductive through holes in a circuit board. For example, a through hole is formed in an insulating substrate having conductive layers on both sides (hereinafter, simply referred to as “substrate”), and a curable conductive material typified by copper paste / silver paste is projected from the substrate surface into the through hole. A method is known in which, after being filled and cured in the state, the protruding portion is removed by polishing to form a conductive through hole.

【0003】[0003]

【発明が解決しようとする課題】上記突出部の硬化体の
研磨除去には、一般にベルトサンダー、スラリー研磨、
バフ研磨、スクラブ研磨等の通常の導電層の研磨に用い
られる研磨方法が好適に用いられる。該基板が比較的厚
い場合は、良好な基板を製造できるが、基板厚みが薄い
場合、例えば1mm以下、特に0.5mm以下の場合に
おいて、上記の研磨の際、スルーホール上端が欠けた
り、スルーホール内壁と硬化性導電物質との界面におけ
るクラック等が発生し、スルーホール接続信頼性が低下
するという問題があることがわかった。
Generally, a belt sander, slurry polishing,
A polishing method used for polishing an ordinary conductive layer such as buffing and scrubbing is preferably used. When the substrate is relatively thick, a good substrate can be manufactured. However, when the substrate is thin, for example, 1 mm or less, particularly 0.5 mm or less, the above-mentioned polishing causes the upper end of the through hole to be chipped, It was found that there is a problem that cracks and the like occur at the interface between the inner wall of the hole and the curable conductive material, and the reliability of through-hole connection is reduced.

【0004】[0004]

【課題を解決するための手段】本発明者らは、上記の問
題を解決すべく鋭意研究を重ねた結果、基板に設けられ
たスルーホール用貫通孔に硬化性導電物質を基板表面よ
り突出する状態で充填し、次いで硬化した後、該硬化体
と基板表面よりなる面を平滑に研磨する際、基板厚みが
薄い場合は基板表面の突出部が研磨作業中に上下の揺れ
を誘導し、そのためにクラックの発生原因となっている
事を確認した。そのために、本発明にあっては、スルー
ホールに対応する箇所に該突出部を包むような凹部を有
する支持台で、該基板を固定化し、非支持台面の該基板
上の突出部を研磨除去することを提供する。本発明にあ
っては、スルーホール上端の欠け、スルーホール内壁と
硬化性導電物質との界面におけるクラック等の発生が効
果的に抑制され、信頼性の高い導通スルーホールを歩留
まり良く形成できる。
As a result of intensive studies to solve the above problems, the inventors of the present invention project a curable conductive material from the surface of a substrate into a through hole for a through hole provided in the substrate. After filling in the state, and then curing, when polishing the surface consisting of the cured body and the substrate surface smoothly, if the substrate thickness is thin, the protrusion on the substrate surface induces vertical shaking during polishing, It was confirmed that this was the cause of the crack. Therefore, in the present invention, the substrate is fixed by a supporting table having a concave portion that wraps the projecting portion at a position corresponding to the through hole, and the projecting portion on the substrate on the non-supporting table surface is removed by polishing. Provide what to do. In the present invention, it is possible to effectively suppress the occurrence of cracks at the upper end of the through hole, cracks at the interface between the inner wall of the through hole and the curable conductive material, and to form highly reliable conductive through holes with a high yield.

【0005】即ち、本発明は、基板に設けられたスルー
ホール用貫通孔に硬化性導電物質を基板表面より突出す
る状態で充填し、次いで該硬化性導電物質を硬化した
後、該スルーホールに対応する箇所に該硬化体の突出部
を包むような凹部を有する支持台で該基板を固定化し、
非支持台面の該基板上の該突出部を研磨除去することを
特徴とする回路基板の製造方法である。
That is, according to the present invention, a through hole for a through hole provided in a substrate is filled with a curable conductive material so as to project from the surface of the substrate, and then the curable conductive material is cured, and then the through hole is filled in the through hole. Immobilizing the substrate with a support having a concave portion that wraps the protruding portion of the cured body at a corresponding position,
It is a method of manufacturing a circuit board, characterized in that the protruding portion on the substrate on the non-supporting base surface is removed by polishing.

【0006】本発明において、基板は、種々の公知の材
質、構造を有する絶縁板の両面に、銅、ニッケル等の導
電層を有するものが特に制限無く使用される。代表的な
ものを例示すれば、紙基材−フェノール樹脂積層基板、
紙基材−エポキシ樹脂積層基板、紙基材−ポリエステル
樹脂積層基板、ガラス基材−エポキシ樹脂積層基板、紙
基材−テフロン樹脂積層基板、ガラス基材−ポリイミド
樹脂積層基板、ガラス基材−BT(ビスマレイミド−ト
リアジン)レジン樹脂積層基板、コンポジット樹脂基板
等の合成樹脂基板や、ポリイミド樹脂、ポリエステル樹
脂等のフレキシブル基板や、アルミニウム、鉄、ステン
レス等の金属をエポキシ樹脂等で覆って絶縁処理した金
属系絶縁基板、あるいはセラミックス基板等が挙げられ
る。また、上記導電層の厚みについては特に制限されな
いが、一般には5〜70μmが適当である。
In the present invention, as the substrate, an insulating plate having various known materials and structures and having conductive layers such as copper and nickel on both surfaces is used without particular limitation. As a typical example, a paper base material-phenolic resin laminated substrate,
Paper substrate-epoxy resin laminated substrate, paper substrate-polyester resin laminated substrate, glass substrate-epoxy resin laminated substrate, paper substrate-Teflon resin laminated substrate, glass substrate-polyimide resin laminated substrate, glass substrate-BT (Bismaleimide-triazine) Resin resin laminated substrate, synthetic resin substrate such as composite resin substrate, flexible substrate such as polyimide resin or polyester resin, or metal such as aluminum, iron or stainless steel covered with epoxy resin or the like for insulation treatment Examples include metal-based insulating substrates and ceramic substrates. The thickness of the conductive layer is not particularly limited, but generally 5 to 70 μm is suitable.

【0007】本発明で用いる基板の厚みは、特に制限さ
れず、0.1mm〜2.0mmから選択すれば良い。特
に本発明が効果的なのは、基板の厚みが1mm以下、好
ましくは0.5mm以下のものである。
The thickness of the substrate used in the present invention is not particularly limited and may be selected from 0.1 mm to 2.0 mm. The present invention is particularly effective when the substrate has a thickness of 1 mm or less, preferably 0.5 mm or less.

【0008】上記の基板には、先ずスルーホール用の貫
通孔が設けられる。上記貫通孔の径は、特に制限される
のものではなく、任意に設定することができる。特に、
本発明にあって、上記貫通孔の径は、硬化性導電物質を
充填することが可能な程度の孔径以上、通常0.3mm
以上、好ましくは、0.3〜2mmより選択する事がで
きる。上記貫通孔の形成方法としては、ドリリング加
工、パンチング加工、レーザー加工等の通常の回路基板
の製造と同様の公知の手段が特に限定されずに用いられ
る。
First, a through hole for a through hole is provided on the above substrate. The diameter of the through hole is not particularly limited and can be set arbitrarily. In particular,
In the present invention, the diameter of the through hole is equal to or larger than the diameter of the hole capable of being filled with the curable conductive material, and is usually 0.3 mm.
Above, preferably, it can be selected from 0.3 to 2 mm. As the method of forming the through holes, known methods similar to those for manufacturing a usual circuit board such as drilling, punching, and laser processing are used without particular limitation.

【0009】本発明において、上記貫通孔には、導電性
を有する硬化体を与える硬化性導電物質を充填して硬化
させる。該硬化性導電物質は、金、銀、銅、ニッケル、
鉛、カーボン等の導電材料とエポキシ樹脂、フェノール
樹脂等の架橋性の熱硬化性樹脂とを必要により有機溶剤
と共に混合してペースト状とした公知の硬化性導電物質
を限定なく使用することができる。これらの硬化性導電
物質の中では、エッチングに使用するエッチング液、例
えば、塩化第二鉄エッチング液、塩化第二銅エッチング
液、過硫酸アンモニウムエッチング液、過硫酸ナトリウ
ムエッチング液、過硫酸カリウムエッチング液、過酸化
水素/硫酸エッチング液、硫酸アンモニウム錯イオンを
主成分とするアルカリ性エッチング液等のエッチング液
により実質的に溶解されない硬化体を与えるものが好適
に使用される。
In the present invention, the through hole is filled with a curable conductive substance which gives a cured product having conductivity and is cured. The curable conductive material is gold, silver, copper, nickel,
A known curable conductive substance that is made into a paste by mixing a conductive material such as lead or carbon with a crosslinkable thermosetting resin such as an epoxy resin or a phenol resin together with an organic solvent as necessary can be used without limitation. . Among these curable conductive substances, the etching solution used for etching, for example, ferric chloride etching solution, cupric chloride etching solution, ammonium persulfate etching solution, sodium persulfate etching solution, potassium persulfate etching solution, A material that gives a cured product that is not substantially dissolved by an etching solution such as a hydrogen peroxide / sulfuric acid etching solution or an alkaline etching solution containing ammonium sulfate complex ions as a main component is preferably used.

【0010】また、上記硬化性導電物質は、良好なスル
ーホール抵抗を得るために、硬化後の電気抵抗が、1×
10-2Ω・cm以下となるように、導電材料の選択、及
び使用量を調節することが好ましい。
Further, the above-mentioned curable conductive material has an electric resistance after curing of 1 × in order to obtain good through-hole resistance.
It is preferable to select the conductive material and adjust the amount used so that it becomes 10 −2 Ω · cm or less.

【0011】上記硬化性導電物質の、基板の貫通孔への
充填は、該硬化性導電物質が貫通孔の全空間を満たし、
且つ導電層の両表面より若干、具体的には、0.1mm
以上、好ましくは、0.1〜2mm突出する程度に充填
する方法であれば特に制限されない。硬化性導電物質の
代表的な充填法を例示すれば、印刷法によって1回或い
は複数回の塗布を行う方法、基板の表裏両面側から表裏
一対のスキージで圧入する方法、ロールコーター或いは
カーテンコーターによって充填し、余分の塗料をスキー
ジで掻き取る方法等の手段が好適に用いられる。
The filling of the above-mentioned curable conductive material into the through holes of the substrate is carried out by filling the entire space of the through holes with the curable conductive material.
A little from both surfaces of the conductive layer, specifically, 0.1 mm
As described above, there is no particular limitation as long as it is a method of filling so as to project by 0.1 to 2 mm. A typical filling method of the curable conductive material is, for example, a method of applying one or more times by a printing method, a method of press-fitting with a pair of front and back squeegees from both sides of the substrate, a roll coater or a curtain coater. Means such as a method of filling and scraping off excess paint with a squeegee are preferably used.

【0012】また、貫通孔に充填された硬化性導電物質
の硬化は、熱風炉、赤外線炉、遠赤外線炉、紫外線硬化
炉、電子線硬化炉等の公知の硬化方法より、硬化性導電
物質の硬化に適するものを適宜選んで硬化させれば良
い。
Further, the curable conductive material filled in the through holes is cured by a known curing method such as a hot air oven, an infrared oven, a far infrared oven, an ultraviolet curing oven, an electron beam curing oven. What is suitable for curing may be appropriately selected and cured.

【0013】次いで、本発明においては上記突出部を研
磨除去する。該研磨除去の態様は、突出部のみを研磨除
去してもよく、基板及び硬化性導電物質の硬化体の両者
を研磨除去し表面を平滑にしてもよい。研磨除去する方
法は、特に制限されず、公知の研磨方法が使用できる。
例えば、ベルトサンダー、スラリー研磨、バフ研磨、ス
クラブ研磨等の方法が好適に用いられる。
Next, in the present invention, the above-mentioned protruding portion is removed by polishing. In the polishing removal mode, only the protrusion may be removed by polishing, or both the substrate and the cured body of the curable conductive material may be removed by polishing to smooth the surface. A method of polishing and removing is not particularly limited, and a known polishing method can be used.
For example, methods such as belt sanding, slurry polishing, buff polishing, and scrub polishing are preferably used.

【0014】本発明は、上記研磨を行う際、基板のスル
ーホールに対応する箇所に該硬化体の突出部を包むよう
な凹部を有する支持台上で上記基板を固定化し、非支持
台面の該基板上の該突出部を研磨除去することが特に重
要である。
According to the present invention, when the above-mentioned polishing is performed, the substrate is fixed on a supporting table having a recessed portion that wraps the protruding portion of the cured body at a position corresponding to the through hole of the substrate, and the non-supporting surface of the substrate is fixed. It is particularly important to polish off the protrusions on the substrate.

【0015】硬化性導電物質を所定の貫通孔に充填、硬
化した後の基板には、前記したように、両表面のスルー
ホールに対応する部分に0.1mm以上の突出部を有す
る。また、上記研磨を行うための装置は、ベルト、或い
はロールにより基板を搬送する方式が一般的である。従
って、上記支持台を使用しない場合には、該基板上面を
研磨する際、基板下面の突出部に起因して、下記の問題
を生じる。即ち、ベルトによる搬送方式における研磨で
は、基板下面とベルトの間に空隙が存在し、研磨の際、
基板は下面の突出部によってのみ支持されるため、研磨
時に基板上面から圧力が加えられると、スルーホール近
傍の基板部分に曲げ応力が加わり、スルーホール内壁付
近に欠陥を生じ易くなる。一方、ロールによる搬送方式
では、基板下面の突出部がロールを通過する際、基板が
持ち上げられるため、研磨時の圧力が変動することによ
り研磨ムラが発生し易くなる。また、上記の問題は、基
板厚みが薄い場合、或いはフレキシブル基板等を用いた
場合のように、基板自身の強度が実質的に不足する場合
において特に顕著である。
As described above, the substrate after the predetermined through hole is filled with the curable conductive material and cured, has the protrusions of 0.1 mm or more in the portions corresponding to the through holes on both surfaces. In addition, a device for carrying out the above-mentioned polishing is generally a system in which a substrate is conveyed by a belt or a roll. Therefore, when the support is not used, the following problems occur due to the protrusion on the lower surface of the substrate when polishing the upper surface of the substrate. That is, in the polishing in the conveyance method by the belt, there is a gap between the lower surface of the substrate and the belt, and during the polishing,
Since the substrate is supported only by the protrusions on the lower surface, when pressure is applied from the upper surface of the substrate during polishing, bending stress is applied to the substrate portion in the vicinity of the through hole, and defects easily occur near the inner wall of the through hole. On the other hand, in the transfer method using a roll, since the substrate is lifted when the protruding portion on the lower surface of the substrate passes through the roll, fluctuations in the pressure during polishing easily cause uneven polishing. Further, the above problem is particularly remarkable when the thickness of the substrate is thin or when the strength of the substrate itself is substantially insufficient as in the case of using a flexible substrate or the like.

【0016】これに対し、本発明は支持台を使用し、該
支持台上に基板を固定化して研磨を行うことにより、研
磨の際に発生するスルーホール近傍の基板へのストレス
を緩和するとともに、基板の板厚が薄い場合や、フレキ
シブル基板等を用いた場合のように、基板自身の強度が
実質的に不足するような場合においても、スルーホール
上端での欠け、スルーホール内壁と硬化性導電物質との
界面におけるクラックの発生等を効果的に抑制でき、均
一で、且つ平滑な研磨が可能になる。
On the other hand, according to the present invention, a support base is used, the substrate is fixed on the support base, and polishing is performed, so that the stress on the substrate in the vicinity of the through hole generated during polishing is alleviated. Even when the thickness of the board is thin or when the strength of the board itself is substantially insufficient, such as when a flexible board is used, chipping at the upper end of the through hole, hardening of the inner wall of the through hole and curability The generation of cracks at the interface with the conductive material can be effectively suppressed, and uniform and smooth polishing can be performed.

【0017】本発明における支持台に設けられた凹部
は、基板のスルーホールに対応する箇所に設けられる。
また、凹部の形状、及び大きさは、基板両表面に存在す
る突起を完全に収納できる体積以上であれば特に制限さ
れず、凹みでも貫通孔でも良い。
The recess provided on the support base in the present invention is provided at a position corresponding to the through hole of the substrate.
Further, the shape and size of the concave portion are not particularly limited as long as the projections on both surfaces of the substrate can be completely accommodated, and may be a concave portion or a through hole.

【0018】本発明において、上記支持台の厚み、及び
材質等は、各種の研磨方法に応じて、研磨時のストレス
に実質的に耐え得るものであれば特に制限されない。例
えば、板厚1.0mm以上のガラス基材−エポキシ樹脂
積層板、板厚0.5mm以上の鉄板等が好適に使用でき
る。
In the present invention, the thickness, material and the like of the support base are not particularly limited as long as they can substantially withstand the stress during polishing according to various polishing methods. For example, a glass substrate-epoxy resin laminate having a plate thickness of 1.0 mm or more, an iron plate having a plate thickness of 0.5 mm or more, and the like can be preferably used.

【0019】スルーホール部分を含む基板の平滑化され
た面上には、必要に応じメッキ層を形成しても良い。該
メッキ層の形成方法は、無電解メッキ及び/叉は電解メ
ッキにより、スルーホール部分を含む基板表面の全面に
メッキ層を形成するのが一般的である。ここで用いられ
る無電解メッキ層或いは電解メッキ層の材質は、公知の
導電性金属が特に制限されずに用いられるが、一般に
は、前記導電性を有する硬化体を与える硬化性導電物質
の材質として使用される銅等の導電性金属と同じ材質を
選択するのが好ましい。該メッキ層の厚みは、特に制限
はないが、メッキによるスルーホールの信頼性が向上
し、且つメッキ層の厚みむらが生じない程度の厚みが好
ましい。具体的に例示すれば、100μm以下、またス
ルーホールの信頼性の向上を考慮すると、5μm以上が
好ましい。特に好ましくは、5〜50μmである。
If necessary, a plating layer may be formed on the smoothed surface of the substrate including the through holes. The plating layer is generally formed by electroless plating and / or electrolytic plating to form the plating layer on the entire surface of the substrate including the through holes. As the material of the electroless plating layer or the electrolytic plating layer used here, a known conductive metal is used without particular limitation, but in general, as a material of a curable conductive substance that gives a cured product having the conductivity, It is preferable to select the same material as the conductive metal used such as copper. The thickness of the plated layer is not particularly limited, but is preferably such that the reliability of the through hole due to plating is improved and uneven thickness of the plated layer does not occur. As a specific example, 100 μm or less is preferable, and 5 μm or more is preferable in consideration of improvement in reliability of through holes. Particularly preferably, it is 5 to 50 μm.

【0020】また、スルーホール部分を含む基板表面に
は、配線パターンが形成される。該配線パターンの形成
は、硬化性導電物質の充填、硬化の工程の前、後のどち
らでも良い。該配線パターンの形成方法は、エッチング
レジストによりエッチングパターンを形成し、エッチン
グを行う方法が一般的である。ここで用いられるエッチ
ングレジストはドライフィルム、レジストインク等が特
に制限なく使用され、パターンのファイン度によって適
宜選択して使用すれば良い。また、エッチングレジスト
パターンはエッチング法によってポジパターン或いはネ
ガパターンを適宜採用すれば良い。例えば、テンティン
グ法に代表されるエッチング法ではポジパターンを、半
田剥離法、SES法に代表されるエッチング法ではネガ
パターンを採用すれば良い。
A wiring pattern is formed on the surface of the substrate including the through holes. The wiring pattern may be formed either before or after the step of filling and hardening the curable conductive material. As a method of forming the wiring pattern, a method of forming an etching pattern with an etching resist and performing etching is generally used. As the etching resist used here, a dry film, a resist ink or the like is used without particular limitation, and it may be appropriately selected and used depending on the fineness of the pattern. Further, as the etching resist pattern, a positive pattern or a negative pattern may be appropriately adopted by the etching method. For example, a positive pattern may be adopted in the etching method typified by the tenting method, and a negative pattern may be adopted in the etching method typified by the solder peeling method and the SES method.

【0021】[0021]

【発明の効果】本発明の方法によれば、スルーホール内
部にメッキ層を形成すること無く、導通スルーホールを
形成することができる。また、上記基板の製造工程中、
基板表面の研磨の際に、特定の位置に凹みを有する支持
台上に基板を固定化することにより、均一で、且つ平滑
な研磨が可能になるため、信頼性の高い導通スルーホー
ルが得られる。また、基板の板厚が薄い場合や、フレキ
シブル基板等を用いた場合のように、基板自身の強度が
実質的に不足するような場合においても、容易に導通ス
ルーホールが形成できる。
According to the method of the present invention, a conductive through hole can be formed without forming a plating layer inside the through hole. Also, during the manufacturing process of the substrate,
When polishing the surface of the substrate, by fixing the substrate on a support that has a recess at a specific position, uniform and smooth polishing can be performed, so a highly reliable conductive through hole can be obtained. . In addition, the conductive through hole can be easily formed even when the substrate is thin, or when the substrate itself is substantially insufficient in strength such as when using a flexible substrate or the like.

【0022】[0022]

【実施例】以下、本発明を具体的に説明するために実施
例を示すが、本発明はこれらの実施例に限定されるもの
ではない。
EXAMPLES Examples will be shown below for specifically explaining the present invention, but the present invention is not limited to these examples.

【0023】実施例1 以下の方法により、導電性を有する硬化体を与える硬化
性導電物質を調製し、回路基板の製造を実施した。即
ち、平均粒径6.8μm、タップ密度2.99g/cm
3、比表面積4200cm2/gの樹枝状電解銅粉に、リ
ノール酸を銅粉表面に対し、0.25×10-5mmol
/cm2の割合で配合し、窒素雰囲気下で15分間、乳
鉢により予備混合した。このようにして得た前処理銅粉
を、ネオペンチルグリコールジグリシジルエーテル(エ
ポキシ当量=150)/ノボラック型フェノール樹脂
(ヒドロキシ当量=105)=74/26(重量比)の
バインダー100重量部に対し、456重量部添加し、
更に、2−エチル−4−メチルイミダゾールを、バイン
ダー100重量部に対し、2.8重量部添加した後、3
本ロールミルで30分間混練して銅ペーストとした。
Example 1 A curable conductive substance which gives a cured product having conductivity was prepared by the following method, and a circuit board was manufactured. That is, the average particle size is 6.8 μm and the tap density is 2.99 g / cm.
3 , dendritic electrolytic copper powder having a specific surface area of 4200 cm 2 / g, linoleic acid to the copper powder surface 0.25 × 10 -5 mmol
/ Cm 2 and compounded in a mortar for 15 minutes under a nitrogen atmosphere. The pretreated copper powder thus obtained was used with respect to 100 parts by weight of a binder of neopentyl glycol diglycidyl ether (epoxy equivalent = 150) / novolac type phenol resin (hydroxy equivalent = 105) = 74/26 (weight ratio). Add 456 parts by weight,
Furthermore, after adding 2.8 parts by weight of 2-ethyl-4-methylimidazole to 100 parts by weight of the binder, 3
This roll mill kneaded the mixture for 30 minutes to obtain a copper paste.

【0024】次に、図1に示す工程に従って回路基板の
製造を実施した。即ち、(a)基板1として、300×
340mm、厚さ0.4mmのガラス基材エポキシ樹脂
銅張積層板を使用して、(b)直径,0.4mm、基板
1枚あたり1150穴の貫通孔2を、ドリル加工により
作成した。(c)該貫通孔2に硬化性導電物質3とし
て、上記の方法で調製した銅ペーストをスクリーン印刷
法により充填した。該銅ペーストを熱風炉にて50℃9
0分、180℃100分の条件で硬化した。硬化後の銅
ペーストは、基板表面から150〜350μm突出して
いた。(d−1)次に、該基板のスルーホールに対応す
る箇所に2.0mmφの貫通孔を有する300×340
mm、厚さ1.6mmのガラス基材エポキシ樹脂銅張積
層板よりなる支持台4の上に上記基板を固定化し、バフ
研磨機を使用して320番及び600番のバフを順次使
用して、非支持台面の該基板上の銅ペースト硬化体の突
出部を研磨し、該硬化体を含む基板表面を平滑化した
(d−3)。(e)次いで平滑化された基板表面に、厚
さ15μmの電解銅メッキ5を施した。(f)次に、電
解銅メッキ面にエッチングレジスト6としてドライフィ
ルム(ハーキュレス(株)社製「アクアマーCF」1.
5mil)をラミネートし、露光、現像してスルーホール
部に接続するエッチングポジパターンを形成した。
(g)その後、塩化第2銅エッチング液でエッチングを
行い、(h)エッチングレジストを剥離する事によって
配線パターンを形成した。形成されたスルーホールの抵
抗値を、該スルーホールに表裏で接続する配線パターン
間で、4端子法により測定した。その結果、3450穴
の測定を行い、平均で20.3mΩ/穴、標準偏差が2
8.3mΩ/穴、200mΩ/穴以上の不良スルーホー
ルは0穴であった。
Next, a circuit board was manufactured according to the steps shown in FIG. That is, (a) as the substrate 1, 300 ×
Using a glass-based epoxy resin copper clad laminate having a thickness of 340 mm and a thickness of 0.4 mm, (b) a through hole 2 having a diameter of 0.4 mm and 1150 holes per substrate was created by drilling. (C) The through-hole 2 was filled with the copper paste prepared by the above method as the curable conductive material 3 by the screen printing method. The copper paste is heated in a hot air oven at 50 ° C. 9
It was cured under conditions of 0 minutes and 180 ° C. for 100 minutes. The cured copper paste had a protrusion of 150 to 350 μm from the substrate surface. (D-1) Next, 300 × 340 having a through hole of 2.0 mmφ at a position corresponding to the through hole of the substrate.
mm, 1.6 mm in thickness, the above substrate is fixed on a support base 4 made of a glass-based epoxy resin copper clad laminate, and 320 buffs and 600 buffs are sequentially used using a buffing machine. The protruding portion of the copper paste cured product on the substrate on the non-support base was polished to smooth the substrate surface containing the cured product (d-3). (E) Then, the smoothed substrate surface was subjected to electrolytic copper plating 5 having a thickness of 15 μm. (F) Next, a dry film (“Aquamar CF” manufactured by Hercules Co., Ltd.) 1.
5 mil) was laminated, exposed and developed to form an etching positive pattern connected to the through hole portion.
(G) After that, etching was performed with a cupric chloride etching solution, and (h) the etching resist was peeled off to form a wiring pattern. The resistance value of the formed through hole was measured by the 4-terminal method between the wiring patterns connected to the through hole on the front and back sides. As a result, 3450 holes were measured, the average was 20.3 mΩ / hole, and the standard deviation was 2
The number of defective through holes of 8.3 mΩ / hole and 200 mΩ / hole or more was 0.

【0025】実施例2 図1に示す工程中、基板表面より突出した硬化体の研磨
に用いる支持台を、上記基板のスルーホールに対応する
箇所に直径2.0mm、深さ1.0mmの凹部を有する
厚さ2.0mmのステンレス板よりなる支持台(d−
2)とした他は、全て実施例1と同様にして配線パター
ンを形成した。形成されたスルーホールの抵抗値は、3
450穴の平均で28.6mΩ/穴、標準偏差が13.
3mΩ/穴、200mΩ/穴以上の不良スルーホールは
0穴であった。
Example 2 In the process shown in FIG. 1, a supporting base used for polishing a hardened material protruding from the surface of the substrate was used as a recess having a diameter of 2.0 mm and a depth of 1.0 mm at a position corresponding to the through hole of the substrate. With a 2.0 mm thick stainless steel plate (d-
Wiring patterns were formed in the same manner as in Example 1 except that the above 2) was adopted. The resistance value of the formed through hole is 3
The average of 450 holes is 28.6 mΩ / hole, and the standard deviation is 13.
The number of defective through holes of 3 mΩ / hole and 200 mΩ / hole or more was 0.

【0026】比較例1 図1に示す工程中、基板表面より突出した硬化体の研磨
に用いる支持台を用いずに、バフ研磨機を使用して32
0番及び600番のバフを順次使用して研磨した他は、
全て実施例1と同様にして配線パターンを形成した。形
成されたスルーホールの抵抗値は、3450穴の平均で
50.0mΩ/穴、標準偏差が106.2mΩ/穴であ
り、200mΩ/穴を越える不良スルーホールが57穴
存在した。この不良スルーホールについて断面観察を行
い、不良原因を解析したところ、全てのスルーホールに
おいて、スルーホール上端の欠け、或いはスルーホール
内壁と硬化性導電物質との界面におけるクラックの発生
のいずれかが観察された。
Comparative Example 1 In the process shown in FIG. 1, a buffing machine was used to remove 32 without using a supporting base used for polishing a hardened material protruding from the substrate surface.
Other than polishing by sequentially using the 0th and 600th buffs,
A wiring pattern was formed in the same manner as in Example 1. The resistance value of the formed through holes was 50.0 mΩ / hole on the average of 3450 holes, the standard deviation was 106.2 mΩ / hole, and there were 57 defective through holes exceeding 200 mΩ / hole. When a cross-section was observed for this defective through hole and the cause of the defect was analyzed, it was observed that, in all through holes, the top of the through hole was chipped or a crack was generated at the interface between the inner wall of the through hole and the curable conductive material. Was done.

【図面の簡単な説明】[Brief description of drawings]

【図1】 図1は、本発明の方法の代表的な態様を示す
工程図である。
FIG. 1 is a process drawing showing a typical embodiment of the method of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 貫通孔 3 硬化性導電物質 4 本発明における支持台 5 メッキ層 6 エッチングレジスト DESCRIPTION OF SYMBOLS 1 Substrate 2 Through hole 3 Curable conductive substance 4 Support base 5 of the present invention 5 Plating layer 6 Etching resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板に設けられたスルーホール用貫通孔
に硬化性導電物質を基板表面より突出する状態で充填
し、次いで該硬化性導電物質を硬化した後、該スルーホ
ールに対応する箇所に該硬化体の突出部を包むような凹
部を有する支持台で該基板を固定化し、非支持台面の該
基板上の該突出部を研磨除去することを特徴とする回路
基板の製造方法。
1. A through hole for a through hole provided in a substrate is filled with a curable conductive substance in a state of protruding from the surface of the substrate, and then the curable conductive substance is cured, and then, at a position corresponding to the through hole. A method for manufacturing a circuit board, characterized in that the substrate is fixed with a support having a concave portion that surrounds the protruding portion of the cured body, and the protruding portion on the substrate on the surface of the non-supporting base is removed by polishing.
JP8436193A 1993-04-12 1993-04-12 Manufacture of circuit board Pending JPH06302954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8436193A JPH06302954A (en) 1993-04-12 1993-04-12 Manufacture of circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8436193A JPH06302954A (en) 1993-04-12 1993-04-12 Manufacture of circuit board

Publications (1)

Publication Number Publication Date
JPH06302954A true JPH06302954A (en) 1994-10-28

Family

ID=13828391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8436193A Pending JPH06302954A (en) 1993-04-12 1993-04-12 Manufacture of circuit board

Country Status (1)

Country Link
JP (1) JPH06302954A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
JP2010135376A (en) * 2008-12-02 2010-06-17 Sumitomo Electric Printed Circuit Inc Connection method and connection structure for printed wiring board
CN107580423A (en) * 2017-08-30 2018-01-12 奥士康精密电路(惠州)有限公司 A kind of method of the residual copper of reduction PCB internal layers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
JP2010135376A (en) * 2008-12-02 2010-06-17 Sumitomo Electric Printed Circuit Inc Connection method and connection structure for printed wiring board
CN107580423A (en) * 2017-08-30 2018-01-12 奥士康精密电路(惠州)有限公司 A kind of method of the residual copper of reduction PCB internal layers

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